diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/cbx_1__0__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/cbx_1__0__icv_in_design.gds.gz new file mode 100644 index 0000000..62cf187 Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/cbx_1__0__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/cbx_1__1__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/cbx_1__1__icv_in_design.gds.gz new file mode 100644 index 0000000..5e278bd Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/cbx_1__1__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/cbx_1__2__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/cbx_1__2__icv_in_design.gds.gz new file mode 100644 index 0000000..48d355a Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/cbx_1__2__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/cby_0__1__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/cby_0__1__icv_in_design.gds.gz new file mode 100644 index 0000000..48d601f Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/cby_0__1__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/cby_1__1__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/cby_1__1__icv_in_design.gds.gz new file mode 100644 index 0000000..11f309c Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/cby_1__1__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/cby_2__1__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/cby_2__1__icv_in_design.gds.gz new file mode 100644 index 0000000..c99accd Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/cby_2__1__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_0__0__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_0__0__icv_in_design.gds.gz new file mode 100644 index 0000000..37e6862 Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_0__0__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_0__1__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_0__1__icv_in_design.gds.gz new file mode 100644 index 0000000..32c00a2 Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_0__1__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_0__2__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_0__2__icv_in_design.gds.gz new file mode 100644 index 0000000..b461938 Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_0__2__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_1__0__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_1__0__icv_in_design.gds.gz new file mode 100644 index 0000000..d33068b Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_1__0__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_1__1__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_1__1__icv_in_design.gds.gz new file mode 100644 index 0000000..9adbf77 Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_1__1__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_1__2__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_1__2__icv_in_design.gds.gz new file mode 100644 index 0000000..8feb32b Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_1__2__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_2__0__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_2__0__icv_in_design.gds.gz new file mode 100644 index 0000000..0c2de41 Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_2__0__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_2__1__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_2__1__icv_in_design.gds.gz new file mode 100644 index 0000000..f9dc3c3 Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_2__1__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_2__2__icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_2__2__icv_in_design.gds.gz new file mode 100644 index 0000000..060c6f4 Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/modules/gds/sb_2__2__icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/cbx_1__0__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/cbx_1__0__icv_in_design.lef new file mode 100644 index 0000000..0af65cd --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/cbx_1__0__icv_in_design.lef @@ -0,0 +1,2143 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO cbx_1__0_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 75.44 BY 76.16 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.23 0.8 36.53 ; + END + END pReset[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 23.99 0.8 24.29 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 48.04 0.595 48.18 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 53.48 0.595 53.62 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.03 0.8 43.33 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 39.88 0.595 40.02 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.39 0.8 44.69 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 41.67 0.8 41.97 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 42.26 0.595 42.4 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 48.47 0.8 48.77 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 50.08 0.595 50.22 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 66.15 0.8 66.45 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 37.59 0.8 37.89 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 74.22 0.595 74.36 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 41.58 0.595 41.72 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 60.62 0.595 60.76 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 52.46 0.595 52.6 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 69.46 0.595 69.6 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 64.36 0.595 64.5 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 49.83 0.8 50.13 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.98 0.595 45.12 ; + END + END chanx_left_in[19] + PIN chanx_left_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 55.18 0.595 55.32 ; + END + END chanx_left_in[20] + PIN chanx_left_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 68.78 0.595 68.92 ; + END + END chanx_left_in[21] + PIN chanx_left_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 67.51 0.8 67.81 ; + END + END chanx_left_in[22] + PIN chanx_left_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 50.76 0.595 50.9 ; + END + END chanx_left_in[23] + PIN chanx_left_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 52.55 0.8 52.85 ; + END + END chanx_left_in[24] + PIN chanx_left_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 38.86 0.595 39 ; + END + END chanx_left_in[25] + PIN chanx_left_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 45.75 0.8 46.05 ; + END + END chanx_left_in[26] + PIN chanx_left_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 47.02 0.595 47.16 ; + END + END chanx_left_in[27] + PIN chanx_left_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.31 0.8 40.61 ; + END + END chanx_left_in[28] + PIN chanx_left_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 58.92 0.595 59.06 ; + END + END chanx_left_in[29] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 1.8 75.44 1.94 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 37.16 75.44 37.3 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 50.51 75.44 50.81 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 39.2 75.44 39.34 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 31.04 75.44 31.18 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 47.11 75.44 47.41 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 43.03 75.44 43.33 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 45.75 75.44 46.05 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 49.15 75.44 49.45 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 47.02 75.44 47.16 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 56.2 75.44 56.34 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 45.32 75.44 45.46 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 52.46 75.44 52.6 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 41.92 75.44 42.06 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 36.48 75.44 36.62 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 47.7 75.44 47.84 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 64.36 75.44 64.5 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 66.4 75.44 66.54 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 22.63 75.44 22.93 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 50.42 75.44 50.56 ; + END + END chanx_right_in[19] + PIN chanx_right_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 25.6 75.44 25.74 ; + END + END chanx_right_in[20] + PIN chanx_right_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 57.9 75.44 58.04 ; + END + END chanx_right_in[21] + PIN chanx_right_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 44.39 75.44 44.69 ; + END + END chanx_right_in[22] + PIN chanx_right_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 44.64 75.44 44.78 ; + END + END chanx_right_in[23] + PIN chanx_right_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 39.88 75.44 40.02 ; + END + END chanx_right_in[24] + PIN chanx_right_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 23.56 75.44 23.7 ; + END + END chanx_right_in[25] + PIN chanx_right_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 23.99 75.44 24.29 ; + END + END chanx_right_in[26] + PIN chanx_right_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 27.98 75.44 28.12 ; + END + END chanx_right_in[27] + PIN chanx_right_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 33.42 75.44 33.56 ; + END + END chanx_right_in[28] + PIN chanx_right_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 55.52 75.44 55.66 ; + END + END chanx_right_in[29] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 18.12 75.44 18.26 ; + END + END ccff_head[0] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 23.56 0.595 23.7 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 21.27 0.8 21.57 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.04 0.595 31.18 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.48 0.595 36.62 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 22.63 0.8 22.93 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 25.6 0.595 25.74 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 17.1 0.595 17.24 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 29 0.595 29.14 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 38.95 0.8 39.25 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 71.5 0.595 71.64 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 66.4 0.595 66.54 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 37.16 0.595 37.3 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 12.68 0.595 12.82 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 57.9 0.595 58.04 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 34.44 0.595 34.58 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.72 0.595 31.86 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 33.76 0.595 33.9 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 22.88 0.595 23.02 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 20.16 0.595 20.3 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 27.98 0.595 28.12 ; + END + END chanx_left_out[19] + PIN chanx_left_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 63.34 0.595 63.48 ; + END + END chanx_left_out[20] + PIN chanx_left_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.11 0.8 47.41 ; + END + END chanx_left_out[21] + PIN chanx_left_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 54.59 0.8 54.89 ; + END + END chanx_left_out[22] + PIN chanx_left_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 15.4 0.595 15.54 ; + END + END chanx_left_out[23] + PIN chanx_left_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 20.84 0.595 20.98 ; + END + END chanx_left_out[24] + PIN chanx_left_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 72.18 0.595 72.32 ; + END + END chanx_left_out[25] + PIN chanx_left_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 61.3 0.595 61.44 ; + END + END chanx_left_out[26] + PIN chanx_left_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 26.28 0.595 26.42 ; + END + END chanx_left_out[27] + PIN chanx_left_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.3 0.595 44.44 ; + END + END chanx_left_out[28] + PIN chanx_left_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 67.08 0.595 67.22 ; + END + END chanx_left_out[29] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 20.84 75.44 20.98 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 31.72 75.44 31.86 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 63.68 75.44 63.82 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 29 75.44 29.14 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 42.6 75.44 42.74 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 12 75.44 12.14 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 30.79 75.44 31.09 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 37.59 75.44 37.89 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 32.15 75.44 32.45 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 61.64 75.44 61.78 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 38.95 75.44 39.25 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 41.67 75.44 41.97 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 33.51 75.44 33.81 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 58.58 75.44 58.72 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 69.46 75.44 69.6 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 66.15 75.44 66.45 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 71.5 75.44 71.64 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 72.18 75.44 72.32 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 36.23 75.44 36.53 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 53.14 75.44 53.28 ; + END + END chanx_right_out[19] + PIN chanx_right_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 34.87 75.44 35.17 ; + END + END chanx_right_out[20] + PIN chanx_right_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 60.96 75.44 61.1 ; + END + END chanx_right_out[21] + PIN chanx_right_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 40.31 75.44 40.61 ; + END + END chanx_right_out[22] + PIN chanx_right_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 34.44 75.44 34.58 ; + END + END chanx_right_out[23] + PIN chanx_right_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 26.28 75.44 26.42 ; + END + END chanx_right_out[24] + PIN chanx_right_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 67.51 75.44 67.81 ; + END + END chanx_right_out[25] + PIN chanx_right_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 22.88 75.44 23.02 ; + END + END chanx_right_out[26] + PIN chanx_right_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 49.74 75.44 49.88 ; + END + END chanx_right_out[27] + PIN chanx_right_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 68.78 75.44 68.92 ; + END + END chanx_right_out[28] + PIN chanx_right_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 67.08 75.44 67.22 ; + END + END chanx_right_out[29] + PIN bottom_grid_pin_0_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.8 0 61.94 0.485 ; + END + END bottom_grid_pin_0_[0] + PIN bottom_grid_pin_2_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 25.35 0.8 25.65 ; + END + END bottom_grid_pin_2_[0] + PIN bottom_grid_pin_4_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 25.35 75.44 25.65 ; + END + END bottom_grid_pin_4_[0] + PIN bottom_grid_pin_6_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.88 0 61.02 0.485 ; + END + END bottom_grid_pin_6_[0] + PIN bottom_grid_pin_8_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 26.71 75.44 27.01 ; + END + END bottom_grid_pin_8_[0] + PIN bottom_grid_pin_10_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 53.23 75.44 53.53 ; + END + END bottom_grid_pin_10_[0] + PIN bottom_grid_pin_12_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 29.43 0.8 29.73 ; + END + END bottom_grid_pin_12_[0] + PIN bottom_grid_pin_14_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.72 0 16.86 0.485 ; + END + END bottom_grid_pin_14_[0] + PIN bottom_grid_pin_16_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 16.51 0.8 16.81 ; + END + END bottom_grid_pin_16_[0] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 11.66 0.595 11.8 ; + END + END ccff_tail[0] + PIN IO_ISOL_N[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 72.27 0.8 72.57 ; + END + END IO_ISOL_N[0] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.92 0 26.06 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 26.84 0 26.98 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.2 0 57.34 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.1 0 64.24 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.96 0 60.1 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.06 0 53.2 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.78 0 44.92 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 5.68 0 5.82 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 4.91 0 5.21 0.8 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.98 0 31.12 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.62 0 23.76 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.98 0 54.12 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.18 0 63.32 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.28 0 56.42 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.76 0 50.9 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.48 0 42.62 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.84 0 3.98 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.6 0 6.74 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.32 0 21.46 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.54 0 24.68 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.7 0 45.84 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.9 0 55.04 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.68 0 51.82 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.62 0 46.76 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.34 0 38.48 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.76 0 4.9 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.92 0 3.06 0.485 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] + PIN top_width_0_height_0__pin_0_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.04 0 59.18 0.485 ; + END + END top_width_0_height_0__pin_0_[0] + PIN top_width_0_height_0__pin_2_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 26.71 0.8 27.01 ; + END + END top_width_0_height_0__pin_2_[0] + PIN top_width_0_height_0__pin_4_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 28.07 75.44 28.37 ; + END + END top_width_0_height_0__pin_4_[0] + PIN top_width_0_height_0__pin_6_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 0 58.26 0.485 ; + END + END top_width_0_height_0__pin_6_[0] + PIN top_width_0_height_0__pin_8_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 29.43 75.44 29.73 ; + END + END top_width_0_height_0__pin_8_[0] + PIN top_width_0_height_0__pin_10_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 51.87 75.44 52.17 ; + END + END top_width_0_height_0__pin_10_[0] + PIN top_width_0_height_0__pin_12_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 28.07 0.8 28.37 ; + END + END top_width_0_height_0__pin_12_[0] + PIN top_width_0_height_0__pin_14_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.64 0 17.78 0.485 ; + END + END top_width_0_height_0__pin_14_[0] + PIN top_width_0_height_0__pin_16_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 17.87 0.8 18.17 ; + END + END top_width_0_height_0__pin_16_[0] + PIN top_width_0_height_0__pin_1_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 3.84 0.595 3.98 ; + END + END top_width_0_height_0__pin_1_upper[0] + PIN top_width_0_height_0__pin_1_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 4.52 75.44 4.66 ; + END + END top_width_0_height_0__pin_1_lower[0] + PIN top_width_0_height_0__pin_3_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 9.28 0.595 9.42 ; + END + END top_width_0_height_0__pin_3_upper[0] + PIN top_width_0_height_0__pin_3_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 15.4 75.44 15.54 ; + END + END top_width_0_height_0__pin_3_lower[0] + PIN top_width_0_height_0__pin_5_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 5.63 0.8 5.93 ; + END + END top_width_0_height_0__pin_5_upper[0] + PIN top_width_0_height_0__pin_5_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 3.84 75.44 3.98 ; + END + END top_width_0_height_0__pin_5_lower[0] + PIN top_width_0_height_0__pin_7_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 6.56 0.595 6.7 ; + END + END top_width_0_height_0__pin_7_upper[0] + PIN top_width_0_height_0__pin_7_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 6.56 75.44 6.7 ; + END + END top_width_0_height_0__pin_7_lower[0] + PIN top_width_0_height_0__pin_9_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 6.99 0.8 7.29 ; + END + END top_width_0_height_0__pin_9_upper[0] + PIN top_width_0_height_0__pin_9_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 8.94 75.44 9.08 ; + END + END top_width_0_height_0__pin_9_lower[0] + PIN top_width_0_height_0__pin_11_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 7.24 0.595 7.38 ; + END + END top_width_0_height_0__pin_11_upper[0] + PIN top_width_0_height_0__pin_11_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 17.44 75.44 17.58 ; + END + END top_width_0_height_0__pin_11_lower[0] + PIN top_width_0_height_0__pin_13_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 1.8 0.595 1.94 ; + END + END top_width_0_height_0__pin_13_upper[0] + PIN top_width_0_height_0__pin_13_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 7.24 75.44 7.38 ; + END + END top_width_0_height_0__pin_13_lower[0] + PIN top_width_0_height_0__pin_15_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 14.72 0.595 14.86 ; + END + END top_width_0_height_0__pin_15_upper[0] + PIN top_width_0_height_0__pin_15_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 14.72 75.44 14.86 ; + END + END top_width_0_height_0__pin_15_lower[0] + PIN top_width_0_height_0__pin_17_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 4.52 0.595 4.66 ; + END + END top_width_0_height_0__pin_17_upper[0] + PIN top_width_0_height_0__pin_17_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 12.68 75.44 12.82 ; + END + END top_width_0_height_0__pin_17_lower[0] + PIN SC_IN_TOP + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 74.22 75.44 74.36 ; + END + END SC_IN_TOP + PIN SC_OUT_BOT + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.94 75.675 66.08 76.16 ; + END + END SC_OUT_BOT + PIN SC_IN_BOT + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.46 75.675 2.6 76.16 ; + END + END SC_IN_BOT + PIN SC_OUT_TOP + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 26.84 75.675 26.98 76.16 ; + END + END SC_OUT_TOP + PIN pReset_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 9.62 75.44 9.76 ; + END + END pReset_E_in + PIN pReset_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 17.78 0.595 17.92 ; + END + END pReset_W_in + PIN pReset_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 9.96 0.595 10.1 ; + END + END pReset_W_out + PIN pReset_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 19.82 75.44 19.96 ; + END + END pReset_E_out + PIN prog_clk_0_N_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 23.62 75.675 23.76 76.16 ; + END + END prog_clk_0_N_in + PIN prog_clk_0_W_out + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met1 ; + RECT 0 56.2 0.595 56.34 ; + END + END prog_clk_0_W_out + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 16.08 3.2 19.28 ; + RECT 72.24 16.08 75.44 19.28 ; + RECT 0 56.88 3.2 60.08 ; + RECT 72.24 56.88 75.44 60.08 ; + LAYER met4 ; + RECT 7.98 0 8.58 0.6 ; + RECT 37.42 0 38.02 0.6 ; + RECT 66.86 0 67.46 0.6 ; + RECT 7.98 75.56 8.58 76.16 ; + RECT 37.42 75.56 38.02 76.16 ; + RECT 66.86 75.56 67.46 76.16 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 74.96 2.48 75.44 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 74.96 7.92 75.44 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 74.96 13.36 75.44 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 74.96 18.8 75.44 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 74.96 24.24 75.44 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 74.96 29.68 75.44 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 74.96 35.12 75.44 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 74.96 40.56 75.44 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 74.96 46 75.44 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 74.96 51.44 75.44 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 74.96 56.88 75.44 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 74.96 62.32 75.44 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 74.96 67.76 75.44 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 74.96 73.2 75.44 73.68 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 36.48 3.2 39.68 ; + RECT 72.24 36.48 75.44 39.68 ; + LAYER met4 ; + RECT 22.7 0 23.3 0.6 ; + RECT 52.14 0 52.74 0.6 ; + RECT 22.7 75.56 23.3 76.16 ; + RECT 52.14 75.56 52.74 76.16 ; + LAYER met1 ; + RECT 0 -0.24 0.48 0.24 ; + RECT 74.96 -0.24 75.44 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 74.96 5.2 75.44 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 74.96 10.64 75.44 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 74.96 16.08 75.44 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 74.96 21.52 75.44 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 74.96 26.96 75.44 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 74.96 32.4 75.44 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 74.96 37.84 75.44 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 74.96 43.28 75.44 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 74.96 48.72 75.44 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 74.96 54.16 75.44 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 74.96 59.6 75.44 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 74.96 65.04 75.44 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 74.96 70.48 75.44 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 74.96 75.92 75.44 76.4 ; + END + END VSS + OBS + LAYER met3 ; + POLYGON 52.605 76.205 52.605 76.2 52.82 76.2 52.82 75.88 52.605 75.88 52.605 75.875 52.275 75.875 52.275 75.88 52.06 75.88 52.06 76.2 52.275 76.2 52.275 76.205 ; + POLYGON 23.165 76.205 23.165 76.2 23.38 76.2 23.38 75.88 23.165 75.88 23.165 75.875 22.835 75.875 22.835 75.88 22.62 75.88 22.62 76.2 22.835 76.2 22.835 76.205 ; + POLYGON 52.605 0.285 52.605 0.28 52.82 0.28 52.82 -0.04 52.605 -0.04 52.605 -0.045 52.275 -0.045 52.275 -0.04 52.06 -0.04 52.06 0.28 52.275 0.28 52.275 0.285 ; + POLYGON 23.165 0.285 23.165 0.28 23.38 0.28 23.38 -0.04 23.165 -0.04 23.165 -0.045 22.835 -0.045 22.835 -0.04 22.62 -0.04 22.62 0.28 22.835 0.28 22.835 0.285 ; + POLYGON 75.04 75.76 75.04 68.21 74.24 68.21 74.24 67.11 75.04 67.11 75.04 66.85 74.24 66.85 74.24 65.75 75.04 65.75 75.04 53.93 74.24 53.93 74.24 52.83 75.04 52.83 75.04 52.57 74.24 52.57 74.24 51.47 75.04 51.47 75.04 51.21 74.24 51.21 74.24 50.11 75.04 50.11 75.04 49.85 74.24 49.85 74.24 48.75 75.04 48.75 75.04 47.81 74.24 47.81 74.24 46.71 75.04 46.71 75.04 46.45 74.24 46.45 74.24 45.35 75.04 45.35 75.04 45.09 74.24 45.09 74.24 43.99 75.04 43.99 75.04 43.73 74.24 43.73 74.24 42.63 75.04 42.63 75.04 42.37 74.24 42.37 74.24 41.27 75.04 41.27 75.04 41.01 74.24 41.01 74.24 39.91 75.04 39.91 75.04 39.65 74.24 39.65 74.24 38.55 75.04 38.55 75.04 38.29 74.24 38.29 74.24 37.19 75.04 37.19 75.04 36.93 74.24 36.93 74.24 35.83 75.04 35.83 75.04 35.57 74.24 35.57 74.24 34.47 75.04 34.47 75.04 34.21 74.24 34.21 74.24 33.11 75.04 33.11 75.04 32.85 74.24 32.85 74.24 31.75 75.04 31.75 75.04 31.49 74.24 31.49 74.24 30.39 75.04 30.39 75.04 30.13 74.24 30.13 74.24 29.03 75.04 29.03 75.04 28.77 74.24 28.77 74.24 27.67 75.04 27.67 75.04 27.41 74.24 27.41 74.24 26.31 75.04 26.31 75.04 26.05 74.24 26.05 74.24 24.95 75.04 24.95 75.04 24.69 74.24 24.69 74.24 23.59 75.04 23.59 75.04 23.33 74.24 23.33 74.24 22.23 75.04 22.23 75.04 0.4 0.4 0.4 0.4 5.23 1.2 5.23 1.2 6.33 0.4 6.33 0.4 6.59 1.2 6.59 1.2 7.69 0.4 7.69 0.4 16.11 1.2 16.11 1.2 17.21 0.4 17.21 0.4 17.47 1.2 17.47 1.2 18.57 0.4 18.57 0.4 20.87 1.2 20.87 1.2 21.97 0.4 21.97 0.4 22.23 1.2 22.23 1.2 23.33 0.4 23.33 0.4 23.59 1.2 23.59 1.2 24.69 0.4 24.69 0.4 24.95 1.2 24.95 1.2 26.05 0.4 26.05 0.4 26.31 1.2 26.31 1.2 27.41 0.4 27.41 0.4 27.67 1.2 27.67 1.2 28.77 0.4 28.77 0.4 29.03 1.2 29.03 1.2 30.13 0.4 30.13 0.4 35.83 1.2 35.83 1.2 36.93 0.4 36.93 0.4 37.19 1.2 37.19 1.2 38.29 0.4 38.29 0.4 38.55 1.2 38.55 1.2 39.65 0.4 39.65 0.4 39.91 1.2 39.91 1.2 41.01 0.4 41.01 0.4 41.27 1.2 41.27 1.2 42.37 0.4 42.37 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 48.07 1.2 48.07 1.2 49.17 0.4 49.17 0.4 49.43 1.2 49.43 1.2 50.53 0.4 50.53 0.4 52.15 1.2 52.15 1.2 53.25 0.4 53.25 0.4 54.19 1.2 54.19 1.2 55.29 0.4 55.29 0.4 65.75 1.2 65.75 1.2 66.85 0.4 66.85 0.4 67.11 1.2 67.11 1.2 68.21 0.4 68.21 0.4 71.87 1.2 71.87 1.2 72.97 0.4 72.97 0.4 75.76 ; + LAYER met1 ; + POLYGON 74.68 76.4 74.68 75.92 52.6 75.92 52.6 75.91 52.28 75.91 52.28 75.92 23.16 75.92 23.16 75.91 22.84 75.91 22.84 75.92 0.76 75.92 0.76 76.4 ; + POLYGON 4.44 70.28 4.44 70.14 0.665 70.14 0.665 69.88 0.525 69.88 0.525 70.28 ; + POLYGON 3.98 64.84 3.98 64.7 0.875 64.7 0.875 64.78 0.525 64.78 0.525 64.84 ; + POLYGON 74.915 41.64 74.915 41.24 63.18 41.24 63.18 41.38 74.775 41.38 74.775 41.64 ; + POLYGON 74.915 18.6 74.915 18.54 74.565 18.54 74.565 18.46 72.38 18.46 72.38 18.6 ; + POLYGON 52.6 0.25 52.6 0.24 74.68 0.24 74.68 -0.24 0.76 -0.24 0.76 0.24 22.84 0.24 22.84 0.25 23.16 0.25 23.16 0.24 52.28 0.24 52.28 0.25 ; + POLYGON 74.68 75.88 74.68 75.64 75.16 75.64 75.16 74.64 74.565 74.64 74.565 73.94 74.68 73.94 74.68 72.92 75.16 72.92 75.16 72.6 74.565 72.6 74.565 71.22 74.68 71.22 74.68 70.2 75.16 70.2 75.16 69.88 74.565 69.88 74.565 68.5 74.68 68.5 74.68 67.5 74.565 67.5 74.565 66.12 75.16 66.12 75.16 65.8 74.68 65.8 74.68 64.78 74.565 64.78 74.565 63.4 75.16 63.4 75.16 63.08 74.68 63.08 74.68 62.06 74.565 62.06 74.565 60.68 75.16 60.68 75.16 60.36 74.68 60.36 74.68 59.32 75.16 59.32 75.16 59 74.565 59 74.565 57.62 74.68 57.62 74.68 56.62 74.565 56.62 74.565 55.24 75.16 55.24 75.16 54.92 74.68 54.92 74.68 53.88 75.16 53.88 75.16 53.56 74.565 53.56 74.565 52.18 74.68 52.18 74.68 51.16 75.16 51.16 75.16 50.84 74.565 50.84 74.565 49.46 74.68 49.46 74.68 48.44 75.16 48.44 75.16 48.12 74.565 48.12 74.565 46.74 74.68 46.74 74.68 45.74 74.565 45.74 74.565 44.36 75.16 44.36 75.16 44.04 74.68 44.04 74.68 43.02 74.565 43.02 74.565 41.64 75.16 41.64 75.16 41.32 74.68 41.32 74.68 40.3 74.565 40.3 74.565 38.92 75.16 38.92 75.16 38.6 74.68 38.6 74.68 37.58 74.565 37.58 74.565 36.2 75.16 36.2 75.16 35.88 74.68 35.88 74.68 34.86 74.565 34.86 74.565 34.16 75.16 34.16 75.16 33.84 74.565 33.84 74.565 33.14 74.68 33.14 74.68 32.14 74.565 32.14 74.565 30.76 75.16 30.76 75.16 30.44 74.68 30.44 74.68 29.42 74.565 29.42 74.565 28.72 75.16 28.72 75.16 28.4 74.565 28.4 74.565 27.7 74.68 27.7 74.68 26.7 74.565 26.7 74.565 25.32 75.16 25.32 75.16 25 74.68 25 74.68 23.98 74.565 23.98 74.565 22.6 75.16 22.6 75.16 22.28 74.68 22.28 74.68 21.26 74.565 21.26 74.565 20.56 75.16 20.56 75.16 20.24 74.565 20.24 74.565 19.54 74.68 19.54 74.68 18.54 74.565 18.54 74.565 17.16 75.16 17.16 75.16 16.84 74.68 16.84 74.68 15.82 74.565 15.82 74.565 14.44 75.16 14.44 75.16 14.12 74.68 14.12 74.68 13.1 74.565 13.1 74.565 11.72 75.16 11.72 75.16 11.4 74.68 11.4 74.68 10.36 75.16 10.36 75.16 10.04 74.565 10.04 74.565 8.66 74.68 8.66 74.68 7.66 74.565 7.66 74.565 6.28 75.16 6.28 75.16 5.96 74.68 5.96 74.68 4.94 74.565 4.94 74.565 3.56 75.16 3.56 75.16 3.24 74.68 3.24 74.68 2.22 74.565 2.22 74.565 1.52 75.16 1.52 75.16 0.52 74.68 0.52 74.68 0.28 0.76 0.28 0.76 0.52 0.28 0.52 0.28 1.52 0.875 1.52 0.875 2.22 0.76 2.22 0.76 3.24 0.28 3.24 0.28 3.56 0.875 3.56 0.875 4.94 0.76 4.94 0.76 5.96 0.28 5.96 0.28 6.28 0.875 6.28 0.875 7.66 0.76 7.66 0.76 8.68 0.28 8.68 0.28 9 0.875 9 0.875 10.38 0.76 10.38 0.76 11.38 0.875 11.38 0.875 12.08 0.28 12.08 0.28 12.4 0.875 12.4 0.875 13.1 0.76 13.1 0.76 14.12 0.28 14.12 0.28 14.44 0.875 14.44 0.875 15.82 0.76 15.82 0.76 16.82 0.875 16.82 0.875 18.2 0.28 18.2 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 19.88 0.875 19.88 0.875 21.26 0.76 21.26 0.76 22.28 0.28 22.28 0.28 22.6 0.875 22.6 0.875 23.98 0.76 23.98 0.76 25 0.28 25 0.28 25.32 0.875 25.32 0.875 26.7 0.76 26.7 0.76 27.7 0.875 27.7 0.875 28.4 0.28 28.4 0.28 28.72 0.875 28.72 0.875 29.42 0.76 29.42 0.76 30.44 0.28 30.44 0.28 30.76 0.875 30.76 0.875 32.14 0.76 32.14 0.76 33.16 0.28 33.16 0.28 33.48 0.875 33.48 0.875 34.86 0.76 34.86 0.76 35.88 0.28 35.88 0.28 36.2 0.875 36.2 0.875 37.58 0.76 37.58 0.76 38.58 0.875 38.58 0.875 39.28 0.28 39.28 0.28 39.6 0.875 39.6 0.875 40.3 0.76 40.3 0.76 41.3 0.875 41.3 0.875 42.68 0.28 42.68 0.28 43 0.76 43 0.76 44.02 0.875 44.02 0.875 45.4 0.28 45.4 0.28 45.72 0.76 45.72 0.76 46.74 0.875 46.74 0.875 47.44 0.28 47.44 0.28 47.76 0.875 47.76 0.875 48.46 0.76 48.46 0.76 49.48 0.28 49.48 0.28 49.8 0.875 49.8 0.875 51.18 0.76 51.18 0.76 52.18 0.875 52.18 0.875 52.88 0.28 52.88 0.28 53.2 0.875 53.2 0.875 53.9 0.76 53.9 0.76 54.9 0.875 54.9 0.875 55.6 0.28 55.6 0.28 55.92 0.875 55.92 0.875 56.62 0.76 56.62 0.76 57.62 0.875 57.62 0.875 58.32 0.28 58.32 0.28 58.64 0.875 58.64 0.875 59.34 0.76 59.34 0.76 60.34 0.875 60.34 0.875 61.72 0.28 61.72 0.28 62.04 0.76 62.04 0.76 63.06 0.875 63.06 0.875 63.76 0.28 63.76 0.28 64.08 0.875 64.08 0.875 64.78 0.76 64.78 0.76 65.8 0.28 65.8 0.28 66.12 0.875 66.12 0.875 67.5 0.76 67.5 0.76 68.5 0.875 68.5 0.875 69.88 0.28 69.88 0.28 70.2 0.76 70.2 0.76 71.22 0.875 71.22 0.875 72.6 0.28 72.6 0.28 72.92 0.76 72.92 0.76 73.94 0.875 73.94 0.875 74.64 0.28 74.64 0.28 75.64 0.76 75.64 0.76 75.88 ; + LAYER met2 ; + RECT 52.3 75.855 52.58 76.225 ; + RECT 22.86 75.855 23.14 76.225 ; + RECT 61.28 0.69 61.54 1.01 ; + RECT 55.3 0.69 55.56 1.01 ; + RECT 27.24 0.69 27.5 1.01 ; + RECT 20.8 0.69 21.06 1.01 ; + RECT 52.3 -0.065 52.58 0.305 ; + RECT 22.86 -0.065 23.14 0.305 ; + POLYGON 75.16 75.88 75.16 0.28 64.52 0.28 64.52 0.765 63.82 0.765 63.82 0.28 63.6 0.28 63.6 0.765 62.9 0.765 62.9 0.28 62.22 0.28 62.22 0.765 61.52 0.765 61.52 0.28 61.3 0.28 61.3 0.765 60.6 0.765 60.6 0.28 60.38 0.28 60.38 0.765 59.68 0.765 59.68 0.28 59.46 0.28 59.46 0.765 58.76 0.765 58.76 0.28 58.54 0.28 58.54 0.765 57.84 0.765 57.84 0.28 57.62 0.28 57.62 0.765 56.92 0.765 56.92 0.28 56.7 0.28 56.7 0.765 56 0.765 56 0.28 55.32 0.28 55.32 0.765 54.62 0.765 54.62 0.28 54.4 0.28 54.4 0.765 53.7 0.765 53.7 0.28 53.48 0.28 53.48 0.765 52.78 0.765 52.78 0.28 52.1 0.28 52.1 0.765 51.4 0.765 51.4 0.28 51.18 0.28 51.18 0.765 50.48 0.765 50.48 0.28 47.04 0.28 47.04 0.765 46.34 0.765 46.34 0.28 46.12 0.28 46.12 0.765 45.42 0.765 45.42 0.28 45.2 0.28 45.2 0.765 44.5 0.765 44.5 0.28 42.9 0.28 42.9 0.765 42.2 0.765 42.2 0.28 38.76 0.28 38.76 0.765 38.06 0.765 38.06 0.28 31.4 0.28 31.4 0.765 30.7 0.765 30.7 0.28 27.26 0.28 27.26 0.765 26.56 0.765 26.56 0.28 26.34 0.28 26.34 0.765 25.64 0.765 25.64 0.28 24.96 0.28 24.96 0.765 24.26 0.765 24.26 0.28 24.04 0.28 24.04 0.765 23.34 0.765 23.34 0.28 21.74 0.28 21.74 0.765 21.04 0.765 21.04 0.28 18.06 0.28 18.06 0.765 17.36 0.765 17.36 0.28 17.14 0.28 17.14 0.765 16.44 0.765 16.44 0.28 7.02 0.28 7.02 0.765 6.32 0.765 6.32 0.28 6.1 0.28 6.1 0.765 5.4 0.765 5.4 0.28 5.18 0.28 5.18 0.765 4.48 0.765 4.48 0.28 4.26 0.28 4.26 0.765 3.56 0.765 3.56 0.28 3.34 0.28 3.34 0.765 2.64 0.765 2.64 0.28 0.28 0.28 0.28 75.88 2.18 75.88 2.18 75.395 2.88 75.395 2.88 75.88 23.34 75.88 23.34 75.395 24.04 75.395 24.04 75.88 26.56 75.88 26.56 75.395 27.26 75.395 27.26 75.88 65.66 75.88 65.66 75.395 66.36 75.395 66.36 75.88 ; + LAYER met4 ; + POLYGON 75.04 75.76 75.04 0.4 67.86 0.4 67.86 1 66.46 1 66.46 0.4 53.14 0.4 53.14 1 51.74 1 51.74 0.4 38.42 0.4 38.42 1 37.02 1 37.02 0.4 23.7 0.4 23.7 1 22.3 1 22.3 0.4 8.98 0.4 8.98 1 7.58 1 7.58 0.4 5.61 0.4 5.61 1.2 4.51 1.2 4.51 0.4 0.4 0.4 0.4 75.76 7.58 75.76 7.58 75.16 8.98 75.16 8.98 75.76 22.3 75.76 22.3 75.16 23.7 75.16 23.7 75.76 37.02 75.76 37.02 75.16 38.42 75.16 38.42 75.76 51.74 75.76 51.74 75.16 53.14 75.16 53.14 75.76 66.46 75.76 66.46 75.16 67.86 75.16 67.86 75.76 ; + LAYER met5 ; + POLYGON 73.84 74.56 73.84 61.68 70.64 61.68 70.64 55.28 73.84 55.28 73.84 41.28 70.64 41.28 70.64 34.88 73.84 34.88 73.84 20.88 70.64 20.88 70.64 14.48 73.84 14.48 73.84 1.6 1.6 1.6 1.6 14.48 4.8 14.48 4.8 20.88 1.6 20.88 1.6 34.88 4.8 34.88 4.8 41.28 1.6 41.28 1.6 55.28 4.8 55.28 4.8 61.68 1.6 61.68 1.6 74.56 ; + LAYER li1 ; + POLYGON 75.44 76.245 75.44 76.075 72.245 76.075 72.245 75.595 72.075 75.595 72.075 76.075 71.405 76.075 71.405 75.595 71.235 75.595 71.235 76.075 70.645 76.075 70.645 75.595 70.315 75.595 70.315 76.075 69.805 76.075 69.805 75.595 69.475 75.595 69.475 76.075 68.965 76.075 68.965 75.275 68.635 75.275 68.635 76.075 66.645 76.075 66.645 75.615 66.34 75.615 66.34 76.075 64.855 76.075 64.855 75.635 64.665 75.635 64.665 76.075 62.765 76.075 62.765 75.615 62.435 75.615 62.435 76.075 59.835 76.075 59.835 75.715 59.505 75.715 59.505 76.075 58.805 76.075 58.805 75.695 58.475 75.695 58.475 76.075 57.445 76.075 57.445 75.615 57.14 75.615 57.14 76.075 55.655 76.075 55.655 75.635 55.465 75.635 55.465 76.075 53.565 76.075 53.565 75.615 53.235 75.615 53.235 76.075 50.635 76.075 50.635 75.715 50.305 75.715 50.305 76.075 49.605 76.075 49.605 75.695 49.275 75.695 49.275 76.075 48.245 76.075 48.245 75.615 47.94 75.615 47.94 76.075 46.455 76.075 46.455 75.635 46.265 75.635 46.265 76.075 44.365 76.075 44.365 75.615 44.035 75.615 44.035 76.075 41.435 76.075 41.435 75.715 41.105 75.715 41.105 76.075 40.405 76.075 40.405 75.695 40.075 75.695 40.075 76.075 39.045 76.075 39.045 75.615 38.74 75.615 38.74 76.075 37.255 76.075 37.255 75.635 37.065 75.635 37.065 76.075 35.165 76.075 35.165 75.615 34.835 75.615 34.835 76.075 32.235 76.075 32.235 75.715 31.905 75.715 31.905 76.075 31.205 76.075 31.205 75.695 30.875 75.695 30.875 76.075 26.155 76.075 26.155 75.695 25.825 75.695 25.825 76.075 22.905 76.075 22.905 75.275 22.575 75.275 22.575 76.075 22.065 76.075 22.065 75.595 21.735 75.595 21.735 76.075 21.225 76.075 21.225 75.595 20.895 75.595 20.895 76.075 20.305 76.075 20.305 75.595 20.135 75.595 20.135 76.075 19.465 76.075 19.465 75.595 19.295 75.595 19.295 76.075 16.035 76.075 16.035 75.695 15.705 75.695 15.705 76.075 12.325 76.075 12.325 75.275 11.995 75.275 11.995 76.075 11.485 76.075 11.485 75.595 11.155 75.595 11.155 76.075 10.645 76.075 10.645 75.595 10.315 75.595 10.315 76.075 9.725 76.075 9.725 75.595 9.555 75.595 9.555 76.075 8.885 76.075 8.885 75.595 8.715 75.595 8.715 76.075 7.805 76.075 7.805 75.275 7.475 75.275 7.475 76.075 6.965 76.075 6.965 75.595 6.635 75.595 6.635 76.075 6.125 76.075 6.125 75.595 5.795 75.595 5.795 76.075 5.285 76.075 5.285 75.595 4.955 75.595 4.955 76.075 4.445 76.075 4.445 75.595 4.115 75.595 4.115 76.075 3.605 76.075 3.605 75.595 3.275 75.595 3.275 76.075 0 76.075 0 76.245 ; + RECT 74.52 73.355 75.44 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 71.76 70.635 75.44 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 71.76 67.915 75.44 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 74.52 65.195 75.44 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 74.52 62.475 75.44 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 74.52 59.755 75.44 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 74.52 57.035 75.44 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 74.52 54.315 75.44 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 74.52 51.595 75.44 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 74.52 48.875 75.44 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 73.6 46.155 75.44 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 73.6 43.435 75.44 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 74.52 40.715 75.44 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 73.6 37.995 75.44 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 73.6 35.275 75.44 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 74.52 32.555 75.44 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 74.52 29.835 75.44 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 74.52 27.115 75.44 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 74.52 24.395 75.44 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 74.52 21.675 75.44 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 74.52 18.955 75.44 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 74.52 16.235 75.44 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 74.52 13.515 75.44 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 74.52 10.795 75.44 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 74.52 8.075 75.44 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 74.52 5.355 75.44 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 74.52 2.635 75.44 2.805 ; + RECT 0 2.635 3.68 2.805 ; + POLYGON 4.565 0.885 4.565 0.085 5.075 0.085 5.075 0.565 5.405 0.565 5.405 0.085 5.915 0.085 5.915 0.565 6.245 0.565 6.245 0.085 6.835 0.085 6.835 0.565 7.005 0.565 7.005 0.085 7.675 0.085 7.675 0.565 7.845 0.565 7.845 0.085 8.795 0.085 8.795 0.595 9.21 0.595 9.21 0.085 10.625 0.085 10.625 0.485 10.955 0.485 10.955 0.085 11.465 0.085 11.465 0.485 11.795 0.485 11.795 0.085 16.725 0.085 16.725 0.485 17.055 0.485 17.055 0.085 17.565 0.085 17.565 0.485 17.895 0.485 17.895 0.085 19.31 0.085 19.31 0.595 19.725 0.595 19.725 0.085 20.755 0.085 20.755 0.595 21.17 0.595 21.17 0.085 22.585 0.085 22.585 0.485 22.915 0.485 22.915 0.085 23.425 0.085 23.425 0.485 23.755 0.485 23.755 0.085 26.735 0.085 26.735 0.595 27.15 0.595 27.15 0.085 28.565 0.085 28.565 0.485 28.895 0.485 28.895 0.085 29.405 0.085 29.405 0.485 29.735 0.485 29.735 0.085 34.665 0.085 34.665 0.485 34.995 0.485 34.995 0.085 35.505 0.085 35.505 0.485 35.835 0.485 35.835 0.085 37.25 0.085 37.25 0.595 37.665 0.595 37.665 0.085 40.645 0.085 40.645 0.485 40.975 0.485 40.975 0.085 41.485 0.085 41.485 0.485 41.815 0.485 41.815 0.085 43.23 0.085 43.23 0.595 43.645 0.595 43.645 0.085 46.625 0.085 46.625 0.485 46.955 0.485 46.955 0.085 47.465 0.085 47.465 0.485 47.795 0.485 47.795 0.085 49.21 0.085 49.21 0.595 49.625 0.595 49.625 0.085 50.395 0.085 50.395 0.545 50.65 0.545 50.65 0.085 51.32 0.085 51.32 0.545 51.49 0.545 51.49 0.085 52.16 0.085 52.16 0.545 52.33 0.545 52.33 0.085 53 0.085 53 0.545 53.17 0.545 53.17 0.085 53.84 0.085 53.84 0.545 54.145 0.545 54.145 0.085 54.795 0.085 54.795 0.595 55.21 0.595 55.21 0.085 56.625 0.085 56.625 0.485 56.955 0.485 56.955 0.085 57.465 0.085 57.465 0.485 57.795 0.485 57.795 0.085 60.775 0.085 60.775 0.595 61.19 0.595 61.19 0.085 62.605 0.085 62.605 0.485 62.935 0.485 62.935 0.085 63.445 0.085 63.445 0.485 63.775 0.485 63.775 0.085 67.215 0.085 67.215 0.595 67.63 0.595 67.63 0.085 69.045 0.085 69.045 0.485 69.375 0.485 69.375 0.085 69.885 0.085 69.885 0.485 70.215 0.485 70.215 0.085 75.44 0.085 75.44 -0.085 0 -0.085 0 0.085 4.235 0.085 4.235 0.885 ; + RECT 0.17 0.17 75.27 75.99 ; + LAYER via ; + RECT 52.365 75.965 52.515 76.115 ; + RECT 22.925 75.965 23.075 76.115 ; + RECT 58.115 0.435 58.265 0.585 ; + RECT 57.195 0.435 57.345 0.585 ; + RECT 53.055 0.435 53.205 0.585 ; + RECT 17.635 0.435 17.785 0.585 ; + RECT 3.835 0.435 3.985 0.585 ; + RECT 52.365 0.045 52.515 0.195 ; + RECT 22.925 0.045 23.075 0.195 ; + LAYER via2 ; + RECT 52.34 75.94 52.54 76.14 ; + RECT 22.9 75.94 23.1 76.14 ; + RECT 74.19 53.28 74.39 53.48 ; + RECT 52.34 0.02 52.54 0.22 ; + RECT 22.9 0.02 23.1 0.22 ; + LAYER via3 ; + RECT 52.34 75.94 52.54 76.14 ; + RECT 22.9 75.94 23.1 76.14 ; + RECT 4.96 0.92 5.16 1.12 ; + RECT 52.34 0.02 52.54 0.22 ; + RECT 22.9 0.02 23.1 0.22 ; + LAYER OVERLAP ; + POLYGON 0 0 0 76.16 75.44 76.16 75.44 0 ; + END +END cbx_1__0_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/cbx_1__1__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/cbx_1__1__icv_in_design.lef new file mode 100644 index 0000000..2c9b60e --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/cbx_1__1__icv_in_design.lef @@ -0,0 +1,1992 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO cbx_1__1_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 75.44 BY 76.16 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 52.55 0.8 52.85 ; + END + END pReset[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 45.32 0.595 45.46 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 25.94 0.595 26.08 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 17.1 0.595 17.24 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 27.98 0.595 28.12 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 66.06 0.595 66.2 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 20.16 0.595 20.3 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.64 0.595 44.78 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.39 0.8 44.69 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.11 0.8 47.41 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 45.75 0.8 46.05 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 26.71 0.8 27.01 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 48.47 0.8 48.77 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 20.84 0.595 20.98 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 66.74 0.595 66.88 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 21.27 0.8 21.57 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 22.63 0.8 22.93 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 63.34 0.595 63.48 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 61.3 0.595 61.44 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 28.66 0.595 28.8 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 14.47 0.8 14.77 ; + END + END chanx_left_in[19] + PIN chanx_left_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 17.19 0.8 17.49 ; + END + END chanx_left_in[20] + PIN chanx_left_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 23.99 0.8 24.29 ; + END + END chanx_left_in[21] + PIN chanx_left_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 15.06 0.595 15.2 ; + END + END chanx_left_in[22] + PIN chanx_left_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 11.66 0.595 11.8 ; + END + END chanx_left_in[23] + PIN chanx_left_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 19.91 0.8 20.21 ; + END + END chanx_left_in[24] + PIN chanx_left_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 12.34 0.595 12.48 ; + END + END chanx_left_in[25] + PIN chanx_left_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 28.07 0.8 28.37 ; + END + END chanx_left_in[26] + PIN chanx_left_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 25.35 0.8 25.65 ; + END + END chanx_left_in[27] + PIN chanx_left_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 14.38 0.595 14.52 ; + END + END chanx_left_in[28] + PIN chanx_left_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 22.88 0.595 23.02 ; + END + END chanx_left_in[29] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 20.16 75.44 20.3 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 17.19 75.44 17.49 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 28.66 75.44 28.8 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 25.94 75.44 26.08 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 15.06 75.44 15.2 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 21.27 75.44 21.57 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 27.98 75.44 28.12 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 15.83 75.44 16.13 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 23.56 75.44 23.7 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 33.42 75.44 33.56 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 22.63 75.44 22.93 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 18.55 75.44 18.85 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 20.84 75.44 20.98 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 66.06 75.44 66.2 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 14.47 75.44 14.77 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 30.7 75.44 30.84 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 45.75 75.44 46.05 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 31.38 75.44 31.52 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 17.44 75.44 17.58 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 72.18 75.44 72.32 ; + END + END chanx_right_in[19] + PIN chanx_right_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 25.26 75.44 25.4 ; + END + END chanx_right_in[20] + PIN chanx_right_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 26.71 75.44 27.01 ; + END + END chanx_right_in[21] + PIN chanx_right_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 14.38 75.44 14.52 ; + END + END chanx_right_in[22] + PIN chanx_right_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 63.34 75.44 63.48 ; + END + END chanx_right_in[23] + PIN chanx_right_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 57.9 75.44 58.04 ; + END + END chanx_right_in[24] + PIN chanx_right_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 44.39 75.44 44.69 ; + END + END chanx_right_in[25] + PIN chanx_right_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 28.07 75.44 28.37 ; + END + END chanx_right_in[26] + PIN chanx_right_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 23.99 75.44 24.29 ; + END + END chanx_right_in[27] + PIN chanx_right_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 22.88 75.44 23.02 ; + END + END chanx_right_in[28] + PIN chanx_right_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 11.66 75.44 11.8 ; + END + END chanx_right_in[29] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 45.32 75.44 45.46 ; + END + END ccff_head[0] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 57.9 0.595 58.04 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 58.58 0.595 58.72 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 32.15 0.8 32.45 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 30.79 0.8 31.09 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 15.83 0.8 16.13 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 41.67 0.8 41.97 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.31 0.8 40.61 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 38.86 0.595 39 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 34.87 0.8 35.17 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 29.43 0.8 29.73 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 41.58 0.595 41.72 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 33.42 0.595 33.56 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 18.55 0.8 18.85 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.23 0.8 36.53 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 42.26 0.595 42.4 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 68.78 0.595 68.92 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.51 0.8 33.81 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 30.7 0.595 30.84 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 49.83 0.8 50.13 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 25.26 0.595 25.4 ; + END + END chanx_left_out[19] + PIN chanx_left_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.82 0.595 36.96 ; + END + END chanx_left_out[20] + PIN chanx_left_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 64.02 0.595 64.16 ; + END + END chanx_left_out[21] + PIN chanx_left_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 39.54 0.595 39.68 ; + END + END chanx_left_out[22] + PIN chanx_left_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 23.56 0.595 23.7 ; + END + END chanx_left_out[23] + PIN chanx_left_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 38.95 0.8 39.25 ; + END + END chanx_left_out[24] + PIN chanx_left_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.38 0.595 31.52 ; + END + END chanx_left_out[25] + PIN chanx_left_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 51.19 0.8 51.49 ; + END + END chanx_left_out[26] + PIN chanx_left_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.03 0.8 43.33 ; + END + END chanx_left_out[27] + PIN chanx_left_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 18.12 0.595 18.26 ; + END + END chanx_left_out[28] + PIN chanx_left_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 37.59 0.8 37.89 ; + END + END chanx_left_out[29] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 38.95 75.44 39.25 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 39.54 75.44 39.68 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 58.58 75.44 58.72 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 68.78 75.44 68.92 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 19.91 75.44 20.21 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 36.82 75.44 36.96 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 41.67 75.44 41.97 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 34.87 75.44 35.17 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 40.31 75.44 40.61 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 42.26 75.44 42.4 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 29.43 75.44 29.73 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 33.51 75.44 33.81 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 32.15 75.44 32.45 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 34.1 75.44 34.24 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 64.02 75.44 64.16 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 18.12 75.44 18.26 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 66.74 75.44 66.88 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 71.5 75.44 71.64 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 41.58 75.44 41.72 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 61.3 75.44 61.44 ; + END + END chanx_right_out[19] + PIN chanx_right_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 36.23 75.44 36.53 ; + END + END chanx_right_out[20] + PIN chanx_right_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 60.62 75.44 60.76 ; + END + END chanx_right_out[21] + PIN chanx_right_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 37.59 75.44 37.89 ; + END + END chanx_right_out[22] + PIN chanx_right_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 44.64 75.44 44.78 ; + END + END chanx_right_out[23] + PIN chanx_right_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 43.03 75.44 43.33 ; + END + END chanx_right_out[24] + PIN chanx_right_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 36.14 75.44 36.28 ; + END + END chanx_right_out[25] + PIN chanx_right_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 38.86 75.44 39 ; + END + END chanx_right_out[26] + PIN chanx_right_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 30.79 75.44 31.09 ; + END + END chanx_right_out[27] + PIN chanx_right_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 69.46 75.44 69.6 ; + END + END chanx_right_out[28] + PIN chanx_right_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 25.35 75.44 25.65 ; + END + END chanx_right_out[29] + PIN bottom_grid_pin_0_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.38 0 3.52 0.485 ; + END + END bottom_grid_pin_0_[0] + PIN bottom_grid_pin_1_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 1.8 0.595 1.94 ; + END + END bottom_grid_pin_1_[0] + PIN bottom_grid_pin_2_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.46 0 2.6 0.485 ; + END + END bottom_grid_pin_2_[0] + PIN bottom_grid_pin_3_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.3 0 4.44 0.485 ; + END + END bottom_grid_pin_3_[0] + PIN bottom_grid_pin_4_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.34 0 15.48 0.485 ; + END + END bottom_grid_pin_4_[0] + PIN bottom_grid_pin_5_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.06 0 30.2 0.485 ; + END + END bottom_grid_pin_5_[0] + PIN bottom_grid_pin_6_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.76 0 27.9 0.485 ; + END + END bottom_grid_pin_6_[0] + PIN bottom_grid_pin_7_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 0 37.1 0.485 ; + END + END bottom_grid_pin_7_[0] + PIN bottom_grid_pin_8_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.9 0 9.04 0.485 ; + END + END bottom_grid_pin_8_[0] + PIN bottom_grid_pin_9_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.98 0 8.12 0.485 ; + END + END bottom_grid_pin_9_[0] + PIN bottom_grid_pin_10_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 5.22 0 5.36 0.485 ; + END + END bottom_grid_pin_10_[0] + PIN bottom_grid_pin_11_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.14 0 6.28 0.485 ; + END + END bottom_grid_pin_11_[0] + PIN bottom_grid_pin_12_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.24 0 22.38 0.485 ; + END + END bottom_grid_pin_12_[0] + PIN bottom_grid_pin_13_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.42 0 14.56 0.485 ; + END + END bottom_grid_pin_13_[0] + PIN bottom_grid_pin_14_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.36 0 32.5 0.485 ; + END + END bottom_grid_pin_14_[0] + PIN bottom_grid_pin_15_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.26 0 16.4 0.485 ; + END + END bottom_grid_pin_15_[0] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 60.62 0.595 60.76 ; + END + END ccff_tail[0] + PIN SC_IN_TOP + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 74.22 75.44 74.36 ; + END + END SC_IN_TOP + PIN SC_OUT_BOT + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.92 0 26.06 0.485 ; + END + END SC_OUT_BOT + PIN SC_IN_BOT + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 0 64.7 0.485 ; + END + END SC_IN_BOT + PIN SC_OUT_TOP + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 26.84 75.675 26.98 76.16 ; + END + END SC_OUT_TOP + PIN REGIN_FEEDTHROUGH + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 72.27 75.44 72.57 ; + END + END REGIN_FEEDTHROUGH + PIN REGOUT_FEEDTHROUGH + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.68 0 28.82 0.485 ; + END + END REGOUT_FEEDTHROUGH + PIN CIN_FEEDTHROUGH + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.74 75.675 10.88 76.16 ; + END + END CIN_FEEDTHROUGH + PIN COUT_FEEDTHROUGH + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.06 0 7.2 0.485 ; + END + END COUT_FEEDTHROUGH + PIN pReset_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 9.28 75.44 9.42 ; + END + END pReset_E_in + PIN pReset_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.14 0.595 36.28 ; + END + END pReset_W_in + PIN pReset_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 4.52 0.595 4.66 ; + END + END pReset_W_out + PIN pReset_S_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.72 0 62.86 0.485 ; + END + END pReset_S_out + PIN pReset_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 11.75 75.44 12.05 ; + END + END pReset_E_out + PIN prog_clk_0_N_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 23.62 75.675 23.76 76.16 ; + END + END prog_clk_0_N_in + PIN prog_clk_0_W_out + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met1 ; + RECT 0 34.44 0.595 34.58 ; + END + END prog_clk_0_W_out + PIN prog_clk_1_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 11.75 0.8 12.05 ; + END + END prog_clk_1_W_in + PIN prog_clk_1_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 13.11 75.44 13.41 ; + END + END prog_clk_1_E_in + PIN prog_clk_1_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.54 75.675 24.68 76.16 ; + END + END prog_clk_1_N_out + PIN prog_clk_1_S_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.62 0 23.76 0.485 ; + END + END prog_clk_1_S_out + PIN prog_clk_2_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 50.08 75.44 50.22 ; + END + END prog_clk_2_E_in + PIN prog_clk_2_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 47.36 0.595 47.5 ; + END + END prog_clk_2_W_in + PIN prog_clk_2_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 50.08 0.595 50.22 ; + END + END prog_clk_2_W_out + PIN prog_clk_2_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 47.36 75.44 47.5 ; + END + END prog_clk_2_E_out + PIN prog_clk_3_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 48.04 0.595 48.18 ; + END + END prog_clk_3_W_in + PIN prog_clk_3_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 50.76 75.44 50.9 ; + END + END prog_clk_3_E_in + PIN prog_clk_3_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 48.04 75.44 48.18 ; + END + END prog_clk_3_E_out + PIN prog_clk_3_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 50.76 0.595 50.9 ; + END + END prog_clk_3_W_out + PIN clk_1_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 13.11 0.8 13.41 ; + END + END clk_1_W_in + PIN clk_1_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 12.68 75.44 12.82 ; + END + END clk_1_E_in + PIN clk_1_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.12 75.675 12.26 76.16 ; + END + END clk_1_N_out + PIN clk_1_S_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.58 0 12.72 0.485 ; + END + END clk_1_S_out + PIN clk_2_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 52.8 75.44 52.94 ; + END + END clk_2_E_in + PIN clk_2_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 55.18 0.595 55.32 ; + END + END clk_2_W_in + PIN clk_2_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 52.8 0.595 52.94 ; + END + END clk_2_W_out + PIN clk_2_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 53.48 75.44 53.62 ; + END + END clk_2_E_out + PIN clk_3_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 53.48 0.595 53.62 ; + END + END clk_3_W_in + PIN clk_3_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 55.86 75.44 56 ; + END + END clk_3_E_in + PIN clk_3_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 55.18 75.44 55.32 ; + END + END clk_3_E_out + PIN clk_3_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 55.86 0.595 56 ; + END + END clk_3_W_out + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 16.08 3.2 19.28 ; + RECT 72.24 16.08 75.44 19.28 ; + RECT 0 56.88 3.2 60.08 ; + RECT 72.24 56.88 75.44 60.08 ; + LAYER met4 ; + RECT 7.98 0 8.58 0.6 ; + RECT 37.42 0 38.02 0.6 ; + RECT 66.86 0 67.46 0.6 ; + RECT 7.98 75.56 8.58 76.16 ; + RECT 37.42 75.56 38.02 76.16 ; + RECT 66.86 75.56 67.46 76.16 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 74.96 2.48 75.44 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 74.96 7.92 75.44 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 74.96 13.36 75.44 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 74.96 18.8 75.44 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 74.96 24.24 75.44 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 74.96 29.68 75.44 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 74.96 35.12 75.44 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 74.96 40.56 75.44 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 74.96 46 75.44 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 74.96 51.44 75.44 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 74.96 56.88 75.44 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 74.96 62.32 75.44 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 74.96 67.76 75.44 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 74.96 73.2 75.44 73.68 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 36.48 3.2 39.68 ; + RECT 72.24 36.48 75.44 39.68 ; + LAYER met4 ; + RECT 22.7 0 23.3 0.6 ; + RECT 52.14 0 52.74 0.6 ; + RECT 22.7 75.56 23.3 76.16 ; + RECT 52.14 75.56 52.74 76.16 ; + LAYER met1 ; + RECT 0 -0.24 0.48 0.24 ; + RECT 74.96 -0.24 75.44 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 74.96 5.2 75.44 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 74.96 10.64 75.44 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 74.96 16.08 75.44 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 74.96 21.52 75.44 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 74.96 26.96 75.44 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 74.96 32.4 75.44 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 74.96 37.84 75.44 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 74.96 43.28 75.44 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 74.96 48.72 75.44 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 74.96 54.16 75.44 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 74.96 59.6 75.44 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 74.96 65.04 75.44 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 74.96 70.48 75.44 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 74.96 75.92 75.44 76.4 ; + END + END VSS + OBS + LAYER met3 ; + POLYGON 52.605 76.205 52.605 76.2 52.82 76.2 52.82 75.88 52.605 75.88 52.605 75.875 52.275 75.875 52.275 75.88 52.06 75.88 52.06 76.2 52.275 76.2 52.275 76.205 ; + POLYGON 23.165 76.205 23.165 76.2 23.38 76.2 23.38 75.88 23.165 75.88 23.165 75.875 22.835 75.875 22.835 75.88 22.62 75.88 22.62 76.2 22.835 76.2 22.835 76.205 ; + POLYGON 50.995 75.985 50.995 75.655 50.665 75.655 50.665 75.67 28.25 75.67 28.25 75.66 27.87 75.66 27.87 75.98 28.25 75.98 28.25 75.97 50.665 75.97 50.665 75.985 ; + POLYGON 1.315 52.185 1.315 52.17 3.6 52.17 3.6 51.87 1.315 51.87 1.315 51.855 0.985 51.855 0.985 52.185 ; + RECT 1.19 43.7 1.57 44.02 ; + POLYGON 2.68 41.29 2.68 40.99 1.2 40.99 1.2 41.01 0.65 41.01 0.65 41.29 ; + POLYGON 52.605 0.285 52.605 0.28 52.82 0.28 52.82 -0.04 52.605 -0.04 52.605 -0.045 52.275 -0.045 52.275 -0.04 52.06 -0.04 52.06 0.28 52.275 0.28 52.275 0.285 ; + POLYGON 23.165 0.285 23.165 0.28 23.38 0.28 23.38 -0.04 23.165 -0.04 23.165 -0.045 22.835 -0.045 22.835 -0.04 22.62 -0.04 22.62 0.28 22.835 0.28 22.835 0.285 ; + POLYGON 75.04 75.76 75.04 72.97 74.24 72.97 74.24 71.87 75.04 71.87 75.04 46.45 74.24 46.45 74.24 45.35 75.04 45.35 75.04 45.09 74.24 45.09 74.24 43.99 75.04 43.99 75.04 43.73 74.24 43.73 74.24 42.63 75.04 42.63 75.04 42.37 74.24 42.37 74.24 41.27 75.04 41.27 75.04 41.01 74.24 41.01 74.24 39.91 75.04 39.91 75.04 39.65 74.24 39.65 74.24 38.55 75.04 38.55 75.04 38.29 74.24 38.29 74.24 37.19 75.04 37.19 75.04 36.93 74.24 36.93 74.24 35.83 75.04 35.83 75.04 35.57 74.24 35.57 74.24 34.47 75.04 34.47 75.04 34.21 74.24 34.21 74.24 33.11 75.04 33.11 75.04 32.85 74.24 32.85 74.24 31.75 75.04 31.75 75.04 31.49 74.24 31.49 74.24 30.39 75.04 30.39 75.04 30.13 74.24 30.13 74.24 29.03 75.04 29.03 75.04 28.77 74.24 28.77 74.24 27.67 75.04 27.67 75.04 27.41 74.24 27.41 74.24 26.31 75.04 26.31 75.04 26.05 74.24 26.05 74.24 24.95 75.04 24.95 75.04 24.69 74.24 24.69 74.24 23.59 75.04 23.59 75.04 23.33 74.24 23.33 74.24 22.23 75.04 22.23 75.04 21.97 74.24 21.97 74.24 20.87 75.04 20.87 75.04 20.61 74.24 20.61 74.24 19.51 75.04 19.51 75.04 19.25 74.24 19.25 74.24 18.15 75.04 18.15 75.04 17.89 74.24 17.89 74.24 16.79 75.04 16.79 75.04 16.53 74.24 16.53 74.24 15.43 75.04 15.43 75.04 15.17 74.24 15.17 74.24 14.07 75.04 14.07 75.04 13.81 74.24 13.81 74.24 12.71 75.04 12.71 75.04 12.45 74.24 12.45 74.24 11.35 75.04 11.35 75.04 0.4 0.4 0.4 0.4 11.35 1.2 11.35 1.2 12.45 0.4 12.45 0.4 12.71 1.2 12.71 1.2 13.81 0.4 13.81 0.4 14.07 1.2 14.07 1.2 15.17 0.4 15.17 0.4 15.43 1.2 15.43 1.2 16.53 0.4 16.53 0.4 16.79 1.2 16.79 1.2 17.89 0.4 17.89 0.4 18.15 1.2 18.15 1.2 19.25 0.4 19.25 0.4 19.51 1.2 19.51 1.2 20.61 0.4 20.61 0.4 20.87 1.2 20.87 1.2 21.97 0.4 21.97 0.4 22.23 1.2 22.23 1.2 23.33 0.4 23.33 0.4 23.59 1.2 23.59 1.2 24.69 0.4 24.69 0.4 24.95 1.2 24.95 1.2 26.05 0.4 26.05 0.4 26.31 1.2 26.31 1.2 27.41 0.4 27.41 0.4 27.67 1.2 27.67 1.2 28.77 0.4 28.77 0.4 29.03 1.2 29.03 1.2 30.13 0.4 30.13 0.4 30.39 1.2 30.39 1.2 31.49 0.4 31.49 0.4 31.75 1.2 31.75 1.2 32.85 0.4 32.85 0.4 33.11 1.2 33.11 1.2 34.21 0.4 34.21 0.4 34.47 1.2 34.47 1.2 35.57 0.4 35.57 0.4 35.83 1.2 35.83 1.2 36.93 0.4 36.93 0.4 37.19 1.2 37.19 1.2 38.29 0.4 38.29 0.4 38.55 1.2 38.55 1.2 39.65 0.4 39.65 0.4 39.91 1.2 39.91 1.2 41.01 0.4 41.01 0.4 41.27 1.2 41.27 1.2 42.37 0.4 42.37 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 48.07 1.2 48.07 1.2 49.17 0.4 49.17 0.4 49.43 1.2 49.43 1.2 50.53 0.4 50.53 0.4 50.79 1.2 50.79 1.2 51.89 0.4 51.89 0.4 52.15 1.2 52.15 1.2 53.25 0.4 53.25 0.4 75.76 ; + LAYER met1 ; + POLYGON 74.68 76.4 74.68 75.92 52.6 75.92 52.6 75.91 52.28 75.91 52.28 75.92 23.16 75.92 23.16 75.91 22.84 75.91 22.84 75.92 0.76 75.92 0.76 76.4 ; + POLYGON 6.28 56.68 6.28 56.54 0.665 56.54 0.665 56.28 0.525 56.28 0.525 56.68 ; + POLYGON 74.915 43.08 74.915 42.68 74.775 42.68 74.775 42.94 67.32 42.94 67.32 43.08 ; + POLYGON 12.26 32.2 12.26 32.06 0.665 32.06 0.665 31.8 0.525 31.8 0.525 32.2 ; + POLYGON 52.6 0.25 52.6 0.24 74.68 0.24 74.68 -0.24 0.76 -0.24 0.76 0.24 22.84 0.24 22.84 0.25 23.16 0.25 23.16 0.24 52.28 0.24 52.28 0.25 ; + POLYGON 74.68 75.88 74.68 75.64 75.16 75.64 75.16 74.64 74.565 74.64 74.565 73.94 74.68 73.94 74.68 72.92 75.16 72.92 75.16 72.6 74.565 72.6 74.565 71.22 74.68 71.22 74.68 70.2 75.16 70.2 75.16 69.88 74.565 69.88 74.565 68.5 74.68 68.5 74.68 67.48 75.16 67.48 75.16 67.16 74.565 67.16 74.565 65.78 74.68 65.78 74.68 64.76 75.16 64.76 75.16 64.44 74.565 64.44 74.565 63.06 74.68 63.06 74.68 62.04 75.16 62.04 75.16 61.72 74.565 61.72 74.565 60.34 74.68 60.34 74.68 59.32 75.16 59.32 75.16 59 74.565 59 74.565 57.62 74.68 57.62 74.68 56.6 75.16 56.6 75.16 56.28 74.565 56.28 74.565 54.9 74.68 54.9 74.68 53.9 74.565 53.9 74.565 52.52 75.16 52.52 75.16 52.2 74.68 52.2 74.68 51.18 74.565 51.18 74.565 49.8 75.16 49.8 75.16 49.48 74.68 49.48 74.68 48.46 74.565 48.46 74.565 47.08 75.16 47.08 75.16 46.76 74.68 46.76 74.68 45.74 74.565 45.74 74.565 44.36 75.16 44.36 75.16 44.04 74.68 44.04 74.68 43 75.16 43 75.16 42.68 74.565 42.68 74.565 41.3 74.68 41.3 74.68 40.28 75.16 40.28 75.16 39.96 74.565 39.96 74.565 38.58 74.68 38.58 74.68 37.56 75.16 37.56 75.16 37.24 74.565 37.24 74.565 35.86 74.68 35.86 74.68 34.84 75.16 34.84 75.16 34.52 74.565 34.52 74.565 33.14 74.68 33.14 74.68 32.12 75.16 32.12 75.16 31.8 74.565 31.8 74.565 30.42 74.68 30.42 74.68 29.4 75.16 29.4 75.16 29.08 74.565 29.08 74.565 27.7 74.68 27.7 74.68 26.68 75.16 26.68 75.16 26.36 74.565 26.36 74.565 24.98 74.68 24.98 74.68 23.98 74.565 23.98 74.565 22.6 75.16 22.6 75.16 22.28 74.68 22.28 74.68 21.26 74.565 21.26 74.565 19.88 75.16 19.88 75.16 19.56 74.68 19.56 74.68 18.54 74.565 18.54 74.565 17.16 75.16 17.16 75.16 16.84 74.68 16.84 74.68 15.8 75.16 15.8 75.16 15.48 74.565 15.48 74.565 14.1 74.68 14.1 74.68 13.1 74.565 13.1 74.565 12.4 75.16 12.4 75.16 12.08 74.565 12.08 74.565 11.38 74.68 11.38 74.68 10.36 75.16 10.36 75.16 9.7 74.565 9.7 74.565 9 75.16 9 75.16 8.68 74.68 8.68 74.68 7.64 75.16 7.64 75.16 5.96 74.68 5.96 74.68 4.92 75.16 4.92 75.16 3.24 74.68 3.24 74.68 2.2 75.16 2.2 75.16 0.52 74.68 0.52 74.68 0.28 0.76 0.28 0.76 0.52 0.28 0.52 0.28 1.52 0.875 1.52 0.875 2.22 0.76 2.22 0.76 3.24 0.28 3.24 0.28 4.24 0.875 4.24 0.875 4.94 0.76 4.94 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.38 0.875 11.38 0.875 12.76 0.28 12.76 0.28 13.08 0.76 13.08 0.76 14.1 0.875 14.1 0.875 15.48 0.28 15.48 0.28 15.8 0.76 15.8 0.76 16.82 0.875 16.82 0.875 17.52 0.28 17.52 0.28 17.84 0.875 17.84 0.875 18.54 0.76 18.54 0.76 19.56 0.28 19.56 0.28 19.88 0.875 19.88 0.875 21.26 0.76 21.26 0.76 22.28 0.28 22.28 0.28 22.6 0.875 22.6 0.875 23.98 0.76 23.98 0.76 24.98 0.875 24.98 0.875 26.36 0.28 26.36 0.28 26.68 0.76 26.68 0.76 27.7 0.875 27.7 0.875 29.08 0.28 29.08 0.28 29.4 0.76 29.4 0.76 30.42 0.875 30.42 0.875 31.8 0.28 31.8 0.28 32.12 0.76 32.12 0.76 33.14 0.875 33.14 0.875 33.84 0.28 33.84 0.28 34.16 0.875 34.16 0.875 34.86 0.76 34.86 0.76 35.86 0.875 35.86 0.875 37.24 0.28 37.24 0.28 37.56 0.76 37.56 0.76 38.58 0.875 38.58 0.875 39.96 0.28 39.96 0.28 40.28 0.76 40.28 0.76 41.3 0.875 41.3 0.875 42.68 0.28 42.68 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 44.36 0.875 44.36 0.875 45.74 0.76 45.74 0.76 46.76 0.28 46.76 0.28 47.08 0.875 47.08 0.875 48.46 0.76 48.46 0.76 49.48 0.28 49.48 0.28 49.8 0.875 49.8 0.875 51.18 0.76 51.18 0.76 52.2 0.28 52.2 0.28 52.52 0.875 52.52 0.875 53.9 0.76 53.9 0.76 54.9 0.875 54.9 0.875 56.28 0.28 56.28 0.28 56.6 0.76 56.6 0.76 57.62 0.875 57.62 0.875 59 0.28 59 0.28 59.32 0.76 59.32 0.76 60.34 0.875 60.34 0.875 61.72 0.28 61.72 0.28 62.04 0.76 62.04 0.76 63.06 0.875 63.06 0.875 64.44 0.28 64.44 0.28 64.76 0.76 64.76 0.76 65.78 0.875 65.78 0.875 67.16 0.28 67.16 0.28 67.48 0.76 67.48 0.76 68.5 0.875 68.5 0.875 69.2 0.28 69.2 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 75.88 ; + LAYER met2 ; + RECT 52.3 75.855 52.58 76.225 ; + RECT 22.86 75.855 23.14 76.225 ; + POLYGON 50.97 76.005 50.97 75.635 50.9 75.635 50.9 74.56 50.76 74.56 50.76 75.635 50.69 75.635 50.69 76.005 ; + RECT 24.94 75.15 25.2 75.47 ; + RECT 24.02 0.35 24.28 0.67 ; + RECT 16.66 0.35 16.92 0.67 ; + RECT 52.3 -0.065 52.58 0.305 ; + RECT 22.86 -0.065 23.14 0.305 ; + POLYGON 75.16 75.88 75.16 0.28 64.98 0.28 64.98 0.765 64.28 0.765 64.28 0.28 63.14 0.28 63.14 0.765 62.44 0.765 62.44 0.28 37.38 0.28 37.38 0.765 36.68 0.765 36.68 0.28 32.78 0.28 32.78 0.765 32.08 0.765 32.08 0.28 30.48 0.28 30.48 0.765 29.78 0.765 29.78 0.28 29.1 0.28 29.1 0.765 28.4 0.765 28.4 0.28 28.18 0.28 28.18 0.765 27.48 0.765 27.48 0.28 26.34 0.28 26.34 0.765 25.64 0.765 25.64 0.28 24.04 0.28 24.04 0.765 23.34 0.765 23.34 0.28 22.66 0.28 22.66 0.765 21.96 0.765 21.96 0.28 16.68 0.28 16.68 0.765 15.98 0.765 15.98 0.28 15.76 0.28 15.76 0.765 15.06 0.765 15.06 0.28 14.84 0.28 14.84 0.765 14.14 0.765 14.14 0.28 13 0.28 13 0.765 12.3 0.765 12.3 0.28 9.32 0.28 9.32 0.765 8.62 0.765 8.62 0.28 8.4 0.28 8.4 0.765 7.7 0.765 7.7 0.28 7.48 0.28 7.48 0.765 6.78 0.765 6.78 0.28 6.56 0.28 6.56 0.765 5.86 0.765 5.86 0.28 5.64 0.28 5.64 0.765 4.94 0.765 4.94 0.28 4.72 0.28 4.72 0.765 4.02 0.765 4.02 0.28 3.8 0.28 3.8 0.765 3.1 0.765 3.1 0.28 2.88 0.28 2.88 0.765 2.18 0.765 2.18 0.28 0.28 0.28 0.28 75.88 10.46 75.88 10.46 75.395 11.16 75.395 11.16 75.88 11.84 75.88 11.84 75.395 12.54 75.395 12.54 75.88 23.34 75.88 23.34 75.395 24.04 75.395 24.04 75.88 24.26 75.88 24.26 75.395 24.96 75.395 24.96 75.88 26.56 75.88 26.56 75.395 27.26 75.395 27.26 75.88 ; + LAYER met4 ; + POLYGON 28.225 75.985 28.225 75.655 28.21 75.655 28.21 2.91 27.91 2.91 27.91 75.655 27.895 75.655 27.895 75.985 ; + POLYGON 75.04 75.76 75.04 0.4 67.86 0.4 67.86 1 66.46 1 66.46 0.4 53.14 0.4 53.14 1 51.74 1 51.74 0.4 38.42 0.4 38.42 1 37.02 1 37.02 0.4 23.7 0.4 23.7 1 22.3 1 22.3 0.4 8.98 0.4 8.98 1 7.58 1 7.58 0.4 0.4 0.4 0.4 75.76 7.58 75.76 7.58 75.16 8.98 75.16 8.98 75.76 22.3 75.76 22.3 75.16 23.7 75.16 23.7 75.76 37.02 75.76 37.02 75.16 38.42 75.16 38.42 75.76 51.74 75.76 51.74 75.16 53.14 75.16 53.14 75.76 66.46 75.76 66.46 75.16 67.86 75.16 67.86 75.76 ; + LAYER met5 ; + POLYGON 73.84 74.56 73.84 61.68 70.64 61.68 70.64 55.28 73.84 55.28 73.84 41.28 70.64 41.28 70.64 34.88 73.84 34.88 73.84 20.88 70.64 20.88 70.64 14.48 73.84 14.48 73.84 1.6 1.6 1.6 1.6 14.48 4.8 14.48 4.8 20.88 1.6 20.88 1.6 34.88 4.8 34.88 4.8 41.28 1.6 41.28 1.6 55.28 4.8 55.28 4.8 61.68 1.6 61.68 1.6 74.56 ; + LAYER li1 ; + POLYGON 75.44 76.245 75.44 76.075 74.895 76.075 74.895 75.35 74.605 75.35 74.605 76.075 71.245 76.075 71.245 75.675 70.915 75.675 70.915 76.075 68.955 76.075 68.955 75.54 68.445 75.54 68.445 76.075 67.535 76.075 67.535 75.35 67.245 75.35 67.245 76.075 66.645 76.075 66.645 75.615 66.34 75.615 66.34 76.075 64.855 76.075 64.855 75.635 64.665 75.635 64.665 76.075 62.765 76.075 62.765 75.615 62.435 75.615 62.435 76.075 59.835 76.075 59.835 75.715 59.505 75.715 59.505 76.075 58.805 76.075 58.805 75.695 58.475 75.695 58.475 76.075 57.445 76.075 57.445 75.595 57.115 75.595 57.115 76.075 56.605 76.075 56.605 75.595 56.275 75.595 56.275 76.075 55.765 76.075 55.765 75.595 55.435 75.595 55.435 76.075 54.925 76.075 54.925 75.595 54.595 75.595 54.595 76.075 54.085 76.075 54.085 75.595 53.755 75.595 53.755 76.075 53.245 76.075 53.245 75.275 52.915 75.275 52.915 76.075 52.355 76.075 52.355 75.35 52.065 75.35 52.065 76.075 50.235 76.075 50.235 75.54 49.725 75.54 49.725 76.075 47.765 76.075 47.765 75.675 47.435 75.675 47.435 76.075 46.405 76.075 46.405 75.615 46.1 75.615 46.1 76.075 44.615 76.075 44.615 75.635 44.425 75.635 44.425 76.075 42.525 76.075 42.525 75.615 42.195 75.615 42.195 76.075 39.595 76.075 39.595 75.715 39.265 75.715 39.265 76.075 38.565 76.075 38.565 75.695 38.235 75.695 38.235 76.075 37.635 76.075 37.635 75.35 37.345 75.35 37.345 76.075 37.025 76.075 37.025 75.275 36.695 75.275 36.695 76.075 36.185 76.075 36.185 75.595 35.855 75.595 35.855 76.075 35.265 76.075 35.265 75.595 35.025 75.595 35.025 76.075 34.325 76.075 34.325 75.595 34.155 75.595 34.155 76.075 33.485 76.075 33.485 75.595 33.315 75.595 33.315 76.075 32.645 76.075 32.645 75.595 32.475 75.595 32.475 76.075 31.805 76.075 31.805 75.595 31.635 75.595 31.635 76.075 30.965 76.075 30.965 75.595 30.795 75.595 30.795 76.075 30.125 76.075 30.125 75.595 29.955 75.595 29.955 76.075 29.285 76.075 29.285 75.595 29.115 75.595 29.115 76.075 28.445 76.075 28.445 75.595 28.275 75.595 28.275 76.075 27.605 76.075 27.605 75.595 27.435 75.595 27.435 76.075 26.765 76.075 26.765 75.595 26.595 75.595 26.595 76.075 25.925 76.075 25.925 75.595 25.755 75.595 25.755 76.075 25.085 76.075 25.085 75.595 24.915 75.595 24.915 76.075 24.245 76.075 24.245 75.595 24.075 75.595 24.075 76.075 22.885 76.075 22.885 75.255 22.715 75.255 22.715 76.075 22.455 76.075 22.455 75.35 22.165 75.35 22.165 76.075 21.555 76.075 21.555 75.695 21.225 75.695 21.225 76.075 20.525 76.075 20.525 75.595 20.355 75.595 20.355 76.075 19.685 76.075 19.685 75.595 19.515 75.595 19.515 76.075 18.845 76.075 18.845 75.595 18.675 75.595 18.675 76.075 18.005 76.075 18.005 75.595 17.835 75.595 17.835 76.075 17.165 76.075 17.165 75.595 16.995 75.595 16.995 76.075 16.325 76.075 16.325 75.595 16.155 75.595 16.155 76.075 15.485 76.075 15.485 75.595 15.315 75.595 15.315 76.075 14.645 76.075 14.645 75.595 14.475 75.595 14.475 76.075 13.805 76.075 13.805 75.595 13.635 75.595 13.635 76.075 12.965 76.075 12.965 75.595 12.795 75.595 12.795 76.075 12.125 76.075 12.125 75.595 11.955 75.595 11.955 76.075 11.285 76.075 11.285 75.595 11.115 75.595 11.115 76.075 10.445 76.075 10.445 75.595 10.275 75.595 10.275 76.075 9.085 76.075 9.085 75.255 8.915 75.255 8.915 76.075 7.735 76.075 7.735 75.35 7.445 75.35 7.445 76.075 6.535 76.075 6.535 75.54 6.025 75.54 6.025 76.075 4.065 76.075 4.065 75.675 3.735 75.675 3.735 76.075 0 76.075 0 76.245 ; + RECT 74.98 73.355 75.44 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 74.98 70.635 75.44 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 71.76 67.915 75.44 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 71.76 65.195 75.44 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 74.52 62.475 75.44 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 74.52 59.755 75.44 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 74.52 57.035 75.44 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 74.52 54.315 75.44 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 71.76 51.595 75.44 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 71.76 48.875 75.44 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 74.52 46.155 75.44 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 74.52 43.435 75.44 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 71.76 40.715 75.44 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 71.76 37.995 75.44 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 71.76 35.275 75.44 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 71.76 32.555 75.44 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 71.76 29.835 75.44 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 71.76 27.115 75.44 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 71.76 24.395 75.44 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 71.76 21.675 75.44 21.845 ; + RECT 0 21.675 1.84 21.845 ; + RECT 71.76 18.955 75.44 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 71.76 16.235 75.44 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 71.76 13.515 75.44 13.685 ; + RECT 0 13.515 1.84 13.685 ; + RECT 71.76 10.795 75.44 10.965 ; + RECT 0 10.795 1.84 10.965 ; + RECT 71.76 8.075 75.44 8.245 ; + RECT 0 8.075 1.84 8.245 ; + RECT 71.76 5.355 75.44 5.525 ; + RECT 0 5.355 1.84 5.525 ; + RECT 74.98 2.635 75.44 2.805 ; + RECT 0 2.635 1.84 2.805 ; + POLYGON 53.5 0.905 53.5 0.085 53.915 0.085 53.915 0.885 54.245 0.885 54.245 0.085 54.755 0.085 54.755 0.565 55.085 0.565 55.085 0.085 55.595 0.085 55.595 0.565 55.925 0.565 55.925 0.085 56.515 0.085 56.515 0.565 56.685 0.565 56.685 0.085 57.355 0.085 57.355 0.565 57.525 0.565 57.525 0.085 58.475 0.085 58.475 0.465 58.805 0.465 58.805 0.085 59.505 0.085 59.505 0.445 59.835 0.445 59.835 0.085 62.435 0.085 62.435 0.545 62.765 0.545 62.765 0.085 64.665 0.085 64.665 0.525 64.855 0.525 64.855 0.085 66.34 0.085 66.34 0.545 66.645 0.545 66.645 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 68.135 0.085 68.135 0.485 68.465 0.485 68.465 0.085 70.425 0.085 70.425 0.62 70.935 0.62 70.935 0.085 74.605 0.085 74.605 0.81 74.895 0.81 74.895 0.085 75.44 0.085 75.44 -0.085 0 -0.085 0 0.085 3.315 0.085 3.315 0.885 3.645 0.885 3.645 0.085 4.155 0.085 4.155 0.565 4.485 0.565 4.485 0.085 4.995 0.085 4.995 0.565 5.325 0.565 5.325 0.085 5.915 0.085 5.915 0.565 6.085 0.565 6.085 0.085 6.755 0.085 6.755 0.565 6.925 0.565 6.925 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 8.715 0.085 8.715 0.565 8.885 0.565 8.885 0.085 9.555 0.085 9.555 0.565 9.725 0.565 9.725 0.085 10.315 0.085 10.315 0.565 10.645 0.565 10.645 0.085 11.155 0.085 11.155 0.565 11.485 0.565 11.485 0.085 11.995 0.085 11.995 0.885 12.325 0.885 12.325 0.085 12.935 0.085 12.935 0.485 13.265 0.485 13.265 0.085 15.225 0.085 15.225 0.62 15.735 0.62 15.735 0.085 16.655 0.085 16.655 0.885 16.985 0.885 16.985 0.085 17.495 0.085 17.495 0.565 17.825 0.565 17.825 0.085 18.335 0.085 18.335 0.565 18.665 0.565 18.665 0.085 19.255 0.085 19.255 0.565 19.425 0.565 19.425 0.085 20.095 0.085 20.095 0.565 20.265 0.565 20.265 0.085 21.225 0.085 21.225 0.465 21.555 0.465 21.555 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 22.635 0.085 22.635 0.885 22.965 0.885 22.965 0.085 23.475 0.085 23.475 0.565 23.805 0.565 23.805 0.085 24.315 0.085 24.315 0.565 24.645 0.565 24.645 0.085 25.235 0.085 25.235 0.565 25.405 0.565 25.405 0.085 26.075 0.085 26.075 0.565 26.245 0.565 26.245 0.085 27.205 0.085 27.205 0.465 27.535 0.465 27.535 0.085 28.575 0.085 28.575 0.465 28.905 0.465 28.905 0.085 29.605 0.085 29.605 0.445 29.935 0.445 29.935 0.085 32.535 0.085 32.535 0.545 32.865 0.545 32.865 0.085 34.765 0.085 34.765 0.525 34.955 0.525 34.955 0.085 36.44 0.085 36.44 0.545 36.745 0.545 36.745 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 39.155 0.085 39.155 0.465 39.485 0.465 39.485 0.085 40.185 0.085 40.185 0.445 40.515 0.445 40.515 0.085 43.115 0.085 43.115 0.545 43.445 0.545 43.445 0.085 45.345 0.085 45.345 0.525 45.535 0.525 45.535 0.085 47.02 0.085 47.02 0.545 47.325 0.545 47.325 0.085 48.095 0.085 48.095 0.545 48.35 0.545 48.35 0.085 49.02 0.085 49.02 0.545 49.19 0.545 49.19 0.085 49.86 0.085 49.86 0.545 50.03 0.545 50.03 0.085 50.7 0.085 50.7 0.545 50.87 0.545 50.87 0.085 51.54 0.085 51.54 0.545 51.845 0.545 51.845 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 53.27 0.085 53.27 0.905 ; + RECT 0.17 0.17 75.27 75.99 ; + LAYER via ; + RECT 52.365 75.965 52.515 76.115 ; + RECT 22.925 75.965 23.075 76.115 ; + RECT 64.555 0.435 64.705 0.585 ; + RECT 30.055 0.435 30.205 0.585 ; + RECT 52.365 0.045 52.515 0.195 ; + RECT 22.925 0.045 23.075 0.195 ; + LAYER via2 ; + RECT 52.34 75.94 52.54 76.14 ; + RECT 22.9 75.94 23.1 76.14 ; + RECT 50.73 75.72 50.93 75.92 ; + RECT 52.34 0.02 52.54 0.22 ; + RECT 22.9 0.02 23.1 0.22 ; + LAYER via3 ; + RECT 52.34 75.94 52.54 76.14 ; + RECT 22.9 75.94 23.1 76.14 ; + RECT 27.96 75.72 28.16 75.92 ; + RECT 52.34 0.02 52.54 0.22 ; + RECT 22.9 0.02 23.1 0.22 ; + LAYER OVERLAP ; + POLYGON 0 0 0 76.16 75.44 76.16 75.44 0 ; + END +END cbx_1__1_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/cbx_1__2__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/cbx_1__2__icv_in_design.lef new file mode 100644 index 0000000..a0bfa5c --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/cbx_1__2__icv_in_design.lef @@ -0,0 +1,1825 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO cbx_1__2_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 75.44 BY 76.16 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.11 0.8 47.41 ; + END + END pReset[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.23 0.8 36.53 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 34.1 0.595 34.24 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.82 0.595 36.96 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 37.59 0.8 37.89 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 13.11 0.8 13.41 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 28.07 0.8 28.37 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 14.47 0.8 14.77 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 5.63 0.8 5.93 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 19.82 0.595 19.96 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 27.98 0.595 28.12 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 15.83 0.8 16.13 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 15.06 0.595 15.2 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 18.12 0.595 18.26 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 11.75 0.8 12.05 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 30.79 0.8 31.09 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 29.43 0.8 29.73 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 6.99 0.8 7.29 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 17.44 0.595 17.58 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.51 0.8 33.81 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 9.71 0.8 10.01 ; + END + END chanx_left_in[19] + PIN chanx_left_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 17.19 0.8 17.49 ; + END + END chanx_left_in[20] + PIN chanx_left_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 26.71 0.8 27.01 ; + END + END chanx_left_in[21] + PIN chanx_left_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 33.42 0.595 33.56 ; + END + END chanx_left_in[22] + PIN chanx_left_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 19.91 0.8 20.21 ; + END + END chanx_left_in[23] + PIN chanx_left_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.31 0.8 40.61 ; + END + END chanx_left_in[24] + PIN chanx_left_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 38.95 0.8 39.25 ; + END + END chanx_left_in[25] + PIN chanx_left_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 47.7 0.595 47.84 ; + END + END chanx_left_in[26] + PIN chanx_left_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.3 0.595 44.44 ; + END + END chanx_left_in[27] + PIN chanx_left_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 8.35 0.8 8.65 ; + END + END chanx_left_in[28] + PIN chanx_left_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 18.55 0.8 18.85 ; + END + END chanx_left_in[29] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 42.6 75.44 42.74 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 37.16 75.44 37.3 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 45.32 75.44 45.46 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 36.91 75.44 37.21 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 39.63 75.44 39.93 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 38.27 75.44 38.57 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 26.03 75.44 26.33 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 7.24 75.44 7.38 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 19.23 75.44 19.53 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 17.87 75.44 18.17 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 27.39 75.44 27.69 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 21.95 75.44 22.25 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 14.72 75.44 14.86 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 4.52 75.44 4.66 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 35.55 75.44 35.85 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 34.19 75.44 34.49 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 3.84 75.44 3.98 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 15.4 75.44 15.54 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 53.14 75.44 53.28 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 7.67 75.44 7.97 ; + END + END chanx_right_in[19] + PIN chanx_right_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 30.7 75.44 30.84 ; + END + END chanx_right_in[20] + PIN chanx_right_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 28.66 75.44 28.8 ; + END + END chanx_right_in[21] + PIN chanx_right_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 12.43 75.44 12.73 ; + END + END chanx_right_in[22] + PIN chanx_right_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 20.16 75.44 20.3 ; + END + END chanx_right_in[23] + PIN chanx_right_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 31.47 75.44 31.77 ; + END + END chanx_right_in[24] + PIN chanx_right_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 34.1 75.44 34.24 ; + END + END chanx_right_in[25] + PIN chanx_right_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 28.75 75.44 29.05 ; + END + END chanx_right_in[26] + PIN chanx_right_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 38.86 75.44 39 ; + END + END chanx_right_in[27] + PIN chanx_right_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 6.31 75.44 6.61 ; + END + END chanx_right_in[28] + PIN chanx_right_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 18.12 75.44 18.26 ; + END + END chanx_right_in[29] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 11.07 75.44 11.37 ; + END + END ccff_head[0] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 32.15 0.8 32.45 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 66.4 0.595 66.54 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 50.42 0.595 50.56 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 39.54 0.595 39.68 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.39 0.8 44.69 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 42.6 0.595 42.74 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 45.75 0.8 46.05 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 7.24 0.595 7.38 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 25.35 0.8 25.65 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 41.58 0.595 41.72 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 21.27 0.8 21.57 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 23.99 0.8 24.29 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 25.26 0.595 25.4 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 38.86 0.595 39 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 49.74 0.595 49.88 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 22.63 0.8 22.93 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.03 0.8 43.33 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 12.68 0.595 12.82 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 20.84 0.595 20.98 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.98 0.595 45.12 ; + END + END chanx_left_out[19] + PIN chanx_left_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 57.9 0.595 58.04 ; + END + END chanx_left_out[20] + PIN chanx_left_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 26.28 0.595 26.42 ; + END + END chanx_left_out[21] + PIN chanx_left_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 41.67 0.8 41.97 ; + END + END chanx_left_out[22] + PIN chanx_left_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 22.88 0.595 23.02 ; + END + END chanx_left_out[23] + PIN chanx_left_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 47.02 0.595 47.16 ; + END + END chanx_left_out[24] + PIN chanx_left_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 34.87 0.8 35.17 ; + END + END chanx_left_out[25] + PIN chanx_left_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 23.56 0.595 23.7 ; + END + END chanx_left_out[26] + PIN chanx_left_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 60.62 0.595 60.76 ; + END + END chanx_left_out[27] + PIN chanx_left_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 30.7 0.595 30.84 ; + END + END chanx_left_out[28] + PIN chanx_left_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 58.58 0.595 58.72 ; + END + END chanx_left_out[29] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 27.98 75.44 28.12 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 13.79 75.44 14.09 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 32.83 75.44 33.13 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 9.96 75.44 10.1 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 16.51 75.44 16.81 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 12.68 75.44 12.82 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 23.56 75.44 23.7 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 15.15 75.44 15.45 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 12 75.44 12.14 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 52.46 75.44 52.6 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 47.02 75.44 47.16 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 33.42 75.44 33.56 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 24.67 75.44 24.97 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 31.38 75.44 31.52 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 44.3 75.44 44.44 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 39.54 75.44 39.68 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 50.42 75.44 50.56 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 20.84 75.44 20.98 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 36.14 75.44 36.28 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 20.59 75.44 20.89 ; + END + END chanx_right_out[19] + PIN chanx_right_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 30.11 75.44 30.41 ; + END + END chanx_right_out[20] + PIN chanx_right_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 23.31 75.44 23.61 ; + END + END chanx_right_out[21] + PIN chanx_right_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 17.44 75.44 17.58 ; + END + END chanx_right_out[22] + PIN chanx_right_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 25.94 75.44 26.08 ; + END + END chanx_right_out[23] + PIN chanx_right_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 22.88 75.44 23.02 ; + END + END chanx_right_out[24] + PIN chanx_right_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 41.58 75.44 41.72 ; + END + END chanx_right_out[25] + PIN chanx_right_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 47.7 75.44 47.84 ; + END + END chanx_right_out[26] + PIN chanx_right_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 49.74 75.44 49.88 ; + END + END chanx_right_out[27] + PIN chanx_right_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 42.35 75.44 42.65 ; + END + END chanx_right_out[28] + PIN chanx_right_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 25.26 75.44 25.4 ; + END + END chanx_right_out[29] + PIN top_grid_pin_0_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.8 0 38.94 0.485 ; + END + END top_grid_pin_0_[0] + PIN bottom_grid_pin_0_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.38 0 3.52 0.485 ; + END + END bottom_grid_pin_0_[0] + PIN bottom_grid_pin_1_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 1.8 0.595 1.94 ; + END + END bottom_grid_pin_1_[0] + PIN bottom_grid_pin_2_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.46 0 2.6 0.485 ; + END + END bottom_grid_pin_2_[0] + PIN bottom_grid_pin_3_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.3 0 4.44 0.485 ; + END + END bottom_grid_pin_3_[0] + PIN bottom_grid_pin_4_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.34 0 15.48 0.485 ; + END + END bottom_grid_pin_4_[0] + PIN bottom_grid_pin_5_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.06 0 30.2 0.485 ; + END + END bottom_grid_pin_5_[0] + PIN bottom_grid_pin_6_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.76 0 27.9 0.485 ; + END + END bottom_grid_pin_6_[0] + PIN bottom_grid_pin_7_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 0 37.1 0.485 ; + END + END bottom_grid_pin_7_[0] + PIN bottom_grid_pin_8_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.9 0 9.04 0.485 ; + END + END bottom_grid_pin_8_[0] + PIN bottom_grid_pin_9_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.98 0 8.12 0.485 ; + END + END bottom_grid_pin_9_[0] + PIN bottom_grid_pin_10_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 5.22 0 5.36 0.485 ; + END + END bottom_grid_pin_10_[0] + PIN bottom_grid_pin_11_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.14 0 6.28 0.485 ; + END + END bottom_grid_pin_11_[0] + PIN bottom_grid_pin_12_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.24 0 22.38 0.485 ; + END + END bottom_grid_pin_12_[0] + PIN bottom_grid_pin_13_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.42 0 14.56 0.485 ; + END + END bottom_grid_pin_13_[0] + PIN bottom_grid_pin_14_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.36 0 32.5 0.485 ; + END + END bottom_grid_pin_14_[0] + PIN bottom_grid_pin_15_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.26 0 16.4 0.485 ; + END + END bottom_grid_pin_15_[0] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 6.56 0.595 6.7 ; + END + END ccff_tail[0] + PIN IO_ISOL_N[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 3.5 0.595 3.64 ; + END + END IO_ISOL_N[0] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.06 75.675 7.2 76.16 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 5.68 75.675 5.82 76.16 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.92 75.675 3.06 76.16 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] + PIN bottom_width_0_height_0__pin_0_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.88 0 38.02 0.485 ; + END + END bottom_width_0_height_0__pin_0_[0] + PIN bottom_width_0_height_0__pin_1_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.38 0.595 31.52 ; + END + END bottom_width_0_height_0__pin_1_upper[0] + PIN bottom_width_0_height_0__pin_1_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 40.99 75.44 41.29 ; + END + END bottom_width_0_height_0__pin_1_lower[0] + PIN SC_IN_TOP + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 11.66 0.595 11.8 ; + END + END SC_IN_TOP + PIN SC_OUT_BOT + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.92 0 26.06 0.485 ; + END + END SC_OUT_BOT + PIN SC_IN_BOT + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 0 64.7 0.485 ; + END + END SC_IN_BOT + PIN SC_OUT_TOP + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 9.03 75.44 9.33 ; + END + END SC_OUT_TOP + PIN pReset_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 74.64 4.27 75.44 4.57 ; + END + END pReset_E_in + PIN pReset_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.14 0.595 36.28 ; + END + END pReset_W_in + PIN pReset_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 29 0.595 29.14 ; + END + END pReset_W_out + PIN pReset_S_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.72 0 62.86 0.485 ; + END + END pReset_S_out + PIN pReset_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 74.845 6.56 75.44 6.7 ; + END + END pReset_E_out + PIN prog_clk_0_S_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 26.84 0 26.98 0.485 ; + END + END prog_clk_0_S_in + PIN prog_clk_0_W_out + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met1 ; + RECT 0 14.38 0.595 14.52 ; + END + END prog_clk_0_W_out + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 16.08 3.2 19.28 ; + RECT 72.24 16.08 75.44 19.28 ; + RECT 0 56.88 3.2 60.08 ; + RECT 72.24 56.88 75.44 60.08 ; + LAYER met4 ; + RECT 7.98 0 8.58 0.6 ; + RECT 37.42 0 38.02 0.6 ; + RECT 66.86 0 67.46 0.6 ; + RECT 7.98 75.56 8.58 76.16 ; + RECT 37.42 75.56 38.02 76.16 ; + RECT 66.86 75.56 67.46 76.16 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 74.96 2.48 75.44 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 74.96 7.92 75.44 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 74.96 13.36 75.44 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 74.96 18.8 75.44 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 74.96 24.24 75.44 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 74.96 29.68 75.44 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 74.96 35.12 75.44 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 74.96 40.56 75.44 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 74.96 46 75.44 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 74.96 51.44 75.44 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 74.96 56.88 75.44 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 74.96 62.32 75.44 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 74.96 67.76 75.44 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 74.96 73.2 75.44 73.68 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 36.48 3.2 39.68 ; + RECT 72.24 36.48 75.44 39.68 ; + LAYER met4 ; + RECT 22.7 0 23.3 0.6 ; + RECT 52.14 0 52.74 0.6 ; + RECT 22.7 75.56 23.3 76.16 ; + RECT 52.14 75.56 52.74 76.16 ; + LAYER met1 ; + RECT 0 -0.24 0.48 0.24 ; + RECT 74.96 -0.24 75.44 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 74.96 5.2 75.44 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 74.96 10.64 75.44 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 74.96 16.08 75.44 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 74.96 21.52 75.44 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 74.96 26.96 75.44 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 74.96 32.4 75.44 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 74.96 37.84 75.44 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 74.96 43.28 75.44 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 74.96 48.72 75.44 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 74.96 54.16 75.44 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 74.96 59.6 75.44 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 74.96 65.04 75.44 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 74.96 70.48 75.44 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 74.96 75.92 75.44 76.4 ; + END + END VSS + OBS + LAYER met3 ; + POLYGON 52.605 76.205 52.605 76.2 52.82 76.2 52.82 75.88 52.605 75.88 52.605 75.875 52.275 75.875 52.275 75.88 52.06 75.88 52.06 76.2 52.275 76.2 52.275 76.205 ; + POLYGON 23.165 76.205 23.165 76.2 23.38 76.2 23.38 75.88 23.165 75.88 23.165 75.875 22.835 75.875 22.835 75.88 22.62 75.88 22.62 76.2 22.835 76.2 22.835 76.205 ; + POLYGON 4.98 41.29 4.98 40.99 0.65 40.99 0.65 41.27 1.2 41.27 1.2 41.29 ; + POLYGON 1.76 14.09 1.76 13.79 1.2 13.79 1.2 13.81 0 13.81 0 14.09 ; + POLYGON 52.605 0.285 52.605 0.28 52.82 0.28 52.82 -0.04 52.605 -0.04 52.605 -0.045 52.275 -0.045 52.275 -0.04 52.06 -0.04 52.06 0.28 52.275 0.28 52.275 0.285 ; + POLYGON 23.165 0.285 23.165 0.28 23.38 0.28 23.38 -0.04 23.165 -0.04 23.165 -0.045 22.835 -0.045 22.835 -0.04 22.62 -0.04 22.62 0.28 22.835 0.28 22.835 0.285 ; + POLYGON 75.04 75.76 75.04 43.05 74.24 43.05 74.24 41.95 75.04 41.95 75.04 41.69 74.24 41.69 74.24 40.59 75.04 40.59 75.04 40.33 74.24 40.33 74.24 39.23 75.04 39.23 75.04 38.97 74.24 38.97 74.24 37.87 75.04 37.87 75.04 37.61 74.24 37.61 74.24 36.51 75.04 36.51 75.04 36.25 74.24 36.25 74.24 35.15 75.04 35.15 75.04 34.89 74.24 34.89 74.24 33.79 75.04 33.79 75.04 33.53 74.24 33.53 74.24 32.43 75.04 32.43 75.04 32.17 74.24 32.17 74.24 31.07 75.04 31.07 75.04 30.81 74.24 30.81 74.24 29.71 75.04 29.71 75.04 29.45 74.24 29.45 74.24 28.35 75.04 28.35 75.04 28.09 74.24 28.09 74.24 26.99 75.04 26.99 75.04 26.73 74.24 26.73 74.24 25.63 75.04 25.63 75.04 25.37 74.24 25.37 74.24 24.27 75.04 24.27 75.04 24.01 74.24 24.01 74.24 22.91 75.04 22.91 75.04 22.65 74.24 22.65 74.24 21.55 75.04 21.55 75.04 21.29 74.24 21.29 74.24 20.19 75.04 20.19 75.04 19.93 74.24 19.93 74.24 18.83 75.04 18.83 75.04 18.57 74.24 18.57 74.24 17.47 75.04 17.47 75.04 17.21 74.24 17.21 74.24 16.11 75.04 16.11 75.04 15.85 74.24 15.85 74.24 14.75 75.04 14.75 75.04 14.49 74.24 14.49 74.24 13.39 75.04 13.39 75.04 13.13 74.24 13.13 74.24 12.03 75.04 12.03 75.04 11.77 74.24 11.77 74.24 10.67 75.04 10.67 75.04 9.73 74.24 9.73 74.24 8.63 75.04 8.63 75.04 8.37 74.24 8.37 74.24 7.27 75.04 7.27 75.04 7.01 74.24 7.01 74.24 5.91 75.04 5.91 75.04 4.97 74.24 4.97 74.24 3.87 75.04 3.87 75.04 0.4 0.4 0.4 0.4 5.23 1.2 5.23 1.2 6.33 0.4 6.33 0.4 6.59 1.2 6.59 1.2 7.69 0.4 7.69 0.4 7.95 1.2 7.95 1.2 9.05 0.4 9.05 0.4 9.31 1.2 9.31 1.2 10.41 0.4 10.41 0.4 11.35 1.2 11.35 1.2 12.45 0.4 12.45 0.4 12.71 1.2 12.71 1.2 13.81 0.4 13.81 0.4 14.07 1.2 14.07 1.2 15.17 0.4 15.17 0.4 15.43 1.2 15.43 1.2 16.53 0.4 16.53 0.4 16.79 1.2 16.79 1.2 17.89 0.4 17.89 0.4 18.15 1.2 18.15 1.2 19.25 0.4 19.25 0.4 19.51 1.2 19.51 1.2 20.61 0.4 20.61 0.4 20.87 1.2 20.87 1.2 21.97 0.4 21.97 0.4 22.23 1.2 22.23 1.2 23.33 0.4 23.33 0.4 23.59 1.2 23.59 1.2 24.69 0.4 24.69 0.4 24.95 1.2 24.95 1.2 26.05 0.4 26.05 0.4 26.31 1.2 26.31 1.2 27.41 0.4 27.41 0.4 27.67 1.2 27.67 1.2 28.77 0.4 28.77 0.4 29.03 1.2 29.03 1.2 30.13 0.4 30.13 0.4 30.39 1.2 30.39 1.2 31.49 0.4 31.49 0.4 31.75 1.2 31.75 1.2 32.85 0.4 32.85 0.4 33.11 1.2 33.11 1.2 34.21 0.4 34.21 0.4 34.47 1.2 34.47 1.2 35.57 0.4 35.57 0.4 35.83 1.2 35.83 1.2 36.93 0.4 36.93 0.4 37.19 1.2 37.19 1.2 38.29 0.4 38.29 0.4 38.55 1.2 38.55 1.2 39.65 0.4 39.65 0.4 39.91 1.2 39.91 1.2 41.01 0.4 41.01 0.4 41.27 1.2 41.27 1.2 42.37 0.4 42.37 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 75.76 ; + LAYER met1 ; + POLYGON 74.68 76.4 74.68 75.92 52.6 75.92 52.6 75.91 52.28 75.91 52.28 75.92 23.16 75.92 23.16 75.91 22.84 75.91 22.84 75.92 0.76 75.92 0.76 76.4 ; + POLYGON 74.82 32.2 74.82 31.8 74.68 31.8 74.68 32.06 68.24 32.06 68.24 32.2 ; + POLYGON 1.68 11.46 1.68 11.32 0.525 11.32 0.525 11.38 0.875 11.38 0.875 11.46 ; + POLYGON 52.6 0.25 52.6 0.24 74.68 0.24 74.68 -0.24 0.76 -0.24 0.76 0.24 22.84 0.24 22.84 0.25 23.16 0.25 23.16 0.24 52.28 0.24 52.28 0.25 ; + POLYGON 74.68 75.88 74.68 75.64 75.16 75.64 75.16 73.96 74.68 73.96 74.68 72.92 75.16 72.92 75.16 71.24 74.68 71.24 74.68 70.2 75.16 70.2 75.16 68.52 74.68 68.52 74.68 67.48 75.16 67.48 75.16 65.8 74.68 65.8 74.68 64.76 75.16 64.76 75.16 63.08 74.68 63.08 74.68 62.04 75.16 62.04 75.16 60.36 74.68 60.36 74.68 59.32 75.16 59.32 75.16 57.64 74.68 57.64 74.68 56.6 75.16 56.6 75.16 54.92 74.68 54.92 74.68 53.88 75.16 53.88 75.16 53.56 74.565 53.56 74.565 52.18 74.68 52.18 74.68 51.16 75.16 51.16 75.16 50.84 74.565 50.84 74.565 49.46 74.68 49.46 74.68 48.44 75.16 48.44 75.16 48.12 74.565 48.12 74.565 46.74 74.68 46.74 74.68 45.74 74.565 45.74 74.565 45.04 75.16 45.04 75.16 44.72 74.565 44.72 74.565 44.02 74.68 44.02 74.68 43.02 74.565 43.02 74.565 42.32 75.16 42.32 75.16 42 74.565 42 74.565 41.3 74.68 41.3 74.68 40.28 75.16 40.28 75.16 39.96 74.565 39.96 74.565 38.58 74.68 38.58 74.68 37.58 74.565 37.58 74.565 36.88 75.16 36.88 75.16 36.56 74.565 36.56 74.565 35.86 74.68 35.86 74.68 34.84 75.16 34.84 75.16 34.52 74.565 34.52 74.565 33.14 74.68 33.14 74.68 32.12 75.16 32.12 75.16 31.8 74.565 31.8 74.565 30.42 74.68 30.42 74.68 29.4 75.16 29.4 75.16 29.08 74.565 29.08 74.565 27.7 74.68 27.7 74.68 26.68 75.16 26.68 75.16 26.36 74.565 26.36 74.565 24.98 74.68 24.98 74.68 23.98 74.565 23.98 74.565 22.6 75.16 22.6 75.16 22.28 74.68 22.28 74.68 21.26 74.565 21.26 74.565 19.88 75.16 19.88 75.16 19.56 74.68 19.56 74.68 18.54 74.565 18.54 74.565 17.16 75.16 17.16 75.16 16.84 74.68 16.84 74.68 15.82 74.565 15.82 74.565 14.44 75.16 14.44 75.16 14.12 74.68 14.12 74.68 13.1 74.565 13.1 74.565 11.72 75.16 11.72 75.16 11.4 74.68 11.4 74.68 10.38 74.565 10.38 74.565 9.68 75.16 9.68 75.16 8.68 74.68 8.68 74.68 7.66 74.565 7.66 74.565 6.28 75.16 6.28 75.16 5.96 74.68 5.96 74.68 4.94 74.565 4.94 74.565 3.56 75.16 3.56 75.16 3.24 74.68 3.24 74.68 2.2 75.16 2.2 75.16 0.52 74.68 0.52 74.68 0.28 0.76 0.28 0.76 0.52 0.28 0.52 0.28 1.52 0.875 1.52 0.875 2.22 0.76 2.22 0.76 3.22 0.875 3.22 0.875 3.92 0.28 3.92 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 6.28 0.875 6.28 0.875 7.66 0.76 7.66 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.38 0.875 11.38 0.875 12.08 0.28 12.08 0.28 12.4 0.875 12.4 0.875 13.1 0.76 13.1 0.76 14.1 0.875 14.1 0.875 15.48 0.28 15.48 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 17.16 0.875 17.16 0.875 18.54 0.76 18.54 0.76 19.54 0.875 19.54 0.875 20.24 0.28 20.24 0.28 20.56 0.875 20.56 0.875 21.26 0.76 21.26 0.76 22.28 0.28 22.28 0.28 22.6 0.875 22.6 0.875 23.98 0.76 23.98 0.76 24.98 0.875 24.98 0.875 25.68 0.28 25.68 0.28 26 0.875 26 0.875 26.7 0.76 26.7 0.76 27.7 0.875 27.7 0.875 28.4 0.28 28.4 0.28 28.72 0.875 28.72 0.875 29.42 0.76 29.42 0.76 30.42 0.875 30.42 0.875 31.8 0.28 31.8 0.28 32.12 0.76 32.12 0.76 33.14 0.875 33.14 0.875 34.52 0.28 34.52 0.28 34.84 0.76 34.84 0.76 35.86 0.875 35.86 0.875 37.24 0.28 37.24 0.28 37.56 0.76 37.56 0.76 38.58 0.875 38.58 0.875 39.96 0.28 39.96 0.28 40.28 0.76 40.28 0.76 41.3 0.875 41.3 0.875 42 0.28 42 0.28 42.32 0.875 42.32 0.875 43.02 0.76 43.02 0.76 44.02 0.875 44.02 0.875 45.4 0.28 45.4 0.28 45.72 0.76 45.72 0.76 46.74 0.875 46.74 0.875 48.12 0.28 48.12 0.28 48.44 0.76 48.44 0.76 49.46 0.875 49.46 0.875 50.84 0.28 50.84 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.62 0.875 57.62 0.875 59 0.28 59 0.28 59.32 0.76 59.32 0.76 60.34 0.875 60.34 0.875 61.04 0.28 61.04 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 66.12 0.875 66.12 0.875 66.82 0.28 66.82 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 75.88 ; + LAYER met2 ; + RECT 52.3 75.855 52.58 76.225 ; + RECT 22.86 75.855 23.14 76.225 ; + RECT 4.7 0.69 4.96 1.01 ; + RECT 52.3 -0.065 52.58 0.305 ; + RECT 22.86 -0.065 23.14 0.305 ; + POLYGON 75.16 75.88 75.16 0.28 64.98 0.28 64.98 0.765 64.28 0.765 64.28 0.28 63.14 0.28 63.14 0.765 62.44 0.765 62.44 0.28 39.22 0.28 39.22 0.765 38.52 0.765 38.52 0.28 38.3 0.28 38.3 0.765 37.6 0.765 37.6 0.28 37.38 0.28 37.38 0.765 36.68 0.765 36.68 0.28 32.78 0.28 32.78 0.765 32.08 0.765 32.08 0.28 30.48 0.28 30.48 0.765 29.78 0.765 29.78 0.28 28.18 0.28 28.18 0.765 27.48 0.765 27.48 0.28 27.26 0.28 27.26 0.765 26.56 0.765 26.56 0.28 26.34 0.28 26.34 0.765 25.64 0.765 25.64 0.28 22.66 0.28 22.66 0.765 21.96 0.765 21.96 0.28 16.68 0.28 16.68 0.765 15.98 0.765 15.98 0.28 15.76 0.28 15.76 0.765 15.06 0.765 15.06 0.28 14.84 0.28 14.84 0.765 14.14 0.765 14.14 0.28 9.32 0.28 9.32 0.765 8.62 0.765 8.62 0.28 8.4 0.28 8.4 0.765 7.7 0.765 7.7 0.28 6.56 0.28 6.56 0.765 5.86 0.765 5.86 0.28 5.64 0.28 5.64 0.765 4.94 0.765 4.94 0.28 4.72 0.28 4.72 0.765 4.02 0.765 4.02 0.28 3.8 0.28 3.8 0.765 3.1 0.765 3.1 0.28 2.88 0.28 2.88 0.765 2.18 0.765 2.18 0.28 0.28 0.28 0.28 75.88 2.64 75.88 2.64 75.395 3.34 75.395 3.34 75.88 5.4 75.88 5.4 75.395 6.1 75.395 6.1 75.88 6.78 75.88 6.78 75.395 7.48 75.395 7.48 75.88 ; + LAYER met4 ; + POLYGON 75.04 75.76 75.04 0.4 67.86 0.4 67.86 1 66.46 1 66.46 0.4 53.14 0.4 53.14 1 51.74 1 51.74 0.4 38.42 0.4 38.42 1 37.02 1 37.02 0.4 23.7 0.4 23.7 1 22.3 1 22.3 0.4 8.98 0.4 8.98 1 7.58 1 7.58 0.4 0.4 0.4 0.4 75.76 7.58 75.76 7.58 75.16 8.98 75.16 8.98 75.76 22.3 75.76 22.3 75.16 23.7 75.16 23.7 75.76 37.02 75.76 37.02 75.16 38.42 75.16 38.42 75.76 51.74 75.76 51.74 75.16 53.14 75.16 53.14 75.76 66.46 75.76 66.46 75.16 67.86 75.16 67.86 75.76 ; + LAYER met5 ; + POLYGON 73.84 74.56 73.84 61.68 70.64 61.68 70.64 55.28 73.84 55.28 73.84 41.28 70.64 41.28 70.64 34.88 73.84 34.88 73.84 20.88 70.64 20.88 70.64 14.48 73.84 14.48 73.84 1.6 1.6 1.6 1.6 14.48 4.8 14.48 4.8 20.88 1.6 20.88 1.6 34.88 4.8 34.88 4.8 41.28 1.6 41.28 1.6 55.28 4.8 55.28 4.8 61.68 1.6 61.68 1.6 74.56 ; + LAYER li1 ; + POLYGON 75.44 76.245 75.44 76.075 71.855 76.075 71.855 75.54 71.345 75.54 71.345 76.075 69.385 76.075 69.385 75.675 69.055 75.675 69.055 76.075 68.025 76.075 68.025 75.615 67.72 75.615 67.72 76.075 66.235 76.075 66.235 75.635 66.045 75.635 66.045 76.075 64.145 76.075 64.145 75.615 63.815 75.615 63.815 76.075 61.215 76.075 61.215 75.715 60.885 75.715 60.885 76.075 60.185 76.075 60.185 75.695 59.855 75.695 59.855 76.075 58.825 76.075 58.825 75.615 58.52 75.615 58.52 76.075 57.035 76.075 57.035 75.635 56.845 75.635 56.845 76.075 54.945 76.075 54.945 75.615 54.615 75.615 54.615 76.075 52.015 76.075 52.015 75.715 51.685 75.715 51.685 76.075 50.985 76.075 50.985 75.695 50.655 75.695 50.655 76.075 49.625 76.075 49.625 75.615 49.32 75.615 49.32 76.075 47.835 76.075 47.835 75.635 47.645 75.635 47.645 76.075 45.745 76.075 45.745 75.615 45.415 75.615 45.415 76.075 42.815 76.075 42.815 75.715 42.485 75.715 42.485 76.075 41.785 76.075 41.785 75.695 41.455 75.695 41.455 76.075 40.425 76.075 40.425 75.615 40.12 75.615 40.12 76.075 38.635 76.075 38.635 75.635 38.445 75.635 38.445 76.075 36.545 76.075 36.545 75.615 36.215 75.615 36.215 76.075 33.615 76.075 33.615 75.715 33.285 75.715 33.285 76.075 32.585 76.075 32.585 75.695 32.255 75.695 32.255 76.075 31.225 76.075 31.225 75.615 30.92 75.615 30.92 76.075 29.435 76.075 29.435 75.635 29.245 75.635 29.245 76.075 27.345 76.075 27.345 75.615 27.015 75.615 27.015 76.075 24.415 76.075 24.415 75.715 24.085 75.715 24.085 76.075 23.385 76.075 23.385 75.695 23.055 75.695 23.055 76.075 22.025 76.075 22.025 75.615 21.72 75.615 21.72 76.075 20.235 76.075 20.235 75.635 20.045 75.635 20.045 76.075 18.145 76.075 18.145 75.615 17.815 75.615 17.815 76.075 15.215 76.075 15.215 75.715 14.885 75.715 14.885 76.075 14.185 76.075 14.185 75.695 13.855 75.695 13.855 76.075 10.875 76.075 10.875 75.675 10.545 75.675 10.545 76.075 10.035 76.075 10.035 75.675 9.705 75.675 9.705 76.075 8.29 76.075 8.29 75.565 7.875 75.565 7.875 76.075 6.765 76.075 6.765 75.615 6.46 75.615 6.46 76.075 5.79 76.075 5.79 75.615 5.62 75.615 5.62 76.075 4.95 76.075 4.95 75.615 4.78 75.615 4.78 76.075 4.11 76.075 4.11 75.615 3.94 75.615 3.94 76.075 3.27 76.075 3.27 75.615 3.015 75.615 3.015 76.075 0 76.075 0 76.245 ; + RECT 74.52 73.355 75.44 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 74.52 70.635 75.44 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 74.52 67.915 75.44 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 74.52 65.195 75.44 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 74.52 62.475 75.44 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 74.52 59.755 75.44 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 74.52 57.035 75.44 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 74.52 54.315 75.44 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 74.52 51.595 75.44 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 74.52 48.875 75.44 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 74.52 46.155 75.44 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 74.52 43.435 75.44 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 74.52 40.715 75.44 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 74.52 37.995 75.44 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 74.52 35.275 75.44 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 74.52 32.555 75.44 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 71.76 29.835 75.44 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 71.76 27.115 75.44 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 74.52 24.395 75.44 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 74.52 21.675 75.44 21.845 ; + RECT 0 21.675 1.84 21.845 ; + RECT 74.52 18.955 75.44 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 74.52 16.235 75.44 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 74.52 13.515 75.44 13.685 ; + RECT 0 13.515 1.84 13.685 ; + RECT 74.52 10.795 75.44 10.965 ; + RECT 0 10.795 1.84 10.965 ; + RECT 74.52 8.075 75.44 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 74.52 5.355 75.44 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 74.52 2.635 75.44 2.805 ; + RECT 0 2.635 1.84 2.805 ; + POLYGON 49.555 0.905 49.555 0.085 50.195 0.085 50.195 0.465 50.525 0.465 50.525 0.085 51.225 0.085 51.225 0.445 51.555 0.445 51.555 0.085 54.155 0.085 54.155 0.545 54.485 0.545 54.485 0.085 56.385 0.085 56.385 0.525 56.575 0.525 56.575 0.085 58.06 0.085 58.06 0.545 58.365 0.545 58.365 0.085 59.355 0.085 59.355 0.885 59.685 0.885 59.685 0.085 60.195 0.085 60.195 0.565 60.525 0.565 60.525 0.085 61.035 0.085 61.035 0.565 61.365 0.565 61.365 0.085 61.875 0.085 61.875 0.565 62.205 0.565 62.205 0.085 62.715 0.085 62.715 0.565 63.045 0.565 63.045 0.085 63.555 0.085 63.555 0.565 63.885 0.565 63.885 0.085 64.835 0.085 64.835 0.565 65.005 0.565 65.005 0.085 65.675 0.085 65.675 0.565 65.845 0.565 65.845 0.085 66.435 0.085 66.435 0.565 66.765 0.565 66.765 0.085 67.275 0.085 67.275 0.565 67.605 0.565 67.605 0.085 68.115 0.085 68.115 0.885 68.445 0.885 68.445 0.085 70.445 0.085 70.445 0.565 70.685 0.565 70.685 0.085 71.275 0.085 71.275 0.565 71.605 0.565 71.605 0.085 72.115 0.085 72.115 0.885 72.445 0.885 72.445 0.085 75.44 0.085 75.44 -0.085 0 -0.085 0 0.085 3.195 0.085 3.195 0.565 3.365 0.565 3.365 0.085 4.035 0.085 4.035 0.565 4.205 0.565 4.205 0.085 4.795 0.085 4.795 0.565 5.125 0.565 5.125 0.085 5.635 0.085 5.635 0.565 5.965 0.565 5.965 0.085 6.475 0.085 6.475 0.885 6.805 0.885 6.805 0.085 8.375 0.085 8.375 0.885 8.705 0.885 8.705 0.085 9.215 0.085 9.215 0.565 9.545 0.565 9.545 0.085 10.055 0.085 10.055 0.565 10.385 0.565 10.385 0.085 10.975 0.085 10.975 0.565 11.145 0.565 11.145 0.085 11.815 0.085 11.815 0.565 11.985 0.565 11.985 0.085 14.885 0.085 14.885 0.485 15.215 0.485 15.215 0.085 15.725 0.085 15.725 0.485 16.055 0.485 16.055 0.085 17.47 0.085 17.47 0.595 17.885 0.595 17.885 0.085 18.495 0.085 18.495 0.885 18.825 0.885 18.825 0.085 19.335 0.085 19.335 0.565 19.665 0.565 19.665 0.085 20.175 0.085 20.175 0.565 20.505 0.565 20.505 0.085 21.095 0.085 21.095 0.565 21.265 0.565 21.265 0.085 21.935 0.085 21.935 0.565 22.105 0.565 22.105 0.085 22.725 0.085 22.725 0.55 22.975 0.55 22.975 0.085 23.565 0.085 23.565 0.545 23.735 0.545 23.735 0.085 24.405 0.085 24.405 0.545 24.575 0.545 24.575 0.085 25.365 0.085 25.365 0.545 25.63 0.545 25.63 0.085 25.855 0.085 25.855 0.885 26.185 0.885 26.185 0.085 26.695 0.085 26.695 0.565 27.025 0.565 27.025 0.085 27.535 0.085 27.535 0.565 27.865 0.565 27.865 0.085 28.455 0.085 28.455 0.565 28.625 0.565 28.625 0.085 29.295 0.085 29.295 0.565 29.465 0.565 29.465 0.085 30.915 0.085 30.915 0.885 31.245 0.885 31.245 0.085 31.755 0.085 31.755 0.565 32.085 0.565 32.085 0.085 32.595 0.085 32.595 0.565 32.925 0.565 32.925 0.085 33.515 0.085 33.515 0.565 33.685 0.565 33.685 0.085 34.355 0.085 34.355 0.565 34.525 0.565 34.525 0.085 35.215 0.085 35.215 0.545 35.47 0.545 35.47 0.085 36.14 0.085 36.14 0.545 36.31 0.545 36.31 0.085 36.98 0.085 36.98 0.545 37.15 0.545 37.15 0.085 37.82 0.085 37.82 0.545 37.99 0.545 37.99 0.085 38.66 0.085 38.66 0.545 38.965 0.545 38.965 0.085 39.615 0.085 39.615 0.465 39.945 0.465 39.945 0.085 40.645 0.085 40.645 0.445 40.975 0.445 40.975 0.085 43.575 0.085 43.575 0.545 43.905 0.545 43.905 0.085 45.805 0.085 45.805 0.525 45.995 0.525 45.995 0.085 47.48 0.085 47.48 0.545 47.785 0.545 47.785 0.085 48.445 0.085 48.445 0.905 48.655 0.905 48.655 0.085 49.325 0.085 49.325 0.905 ; + RECT 0.17 0.17 75.27 75.99 ; + LAYER via ; + RECT 52.365 75.965 52.515 76.115 ; + RECT 22.925 75.965 23.075 76.115 ; + RECT 32.355 0.435 32.505 0.585 ; + RECT 16.255 0.435 16.405 0.585 ; + RECT 2.455 0.435 2.605 0.585 ; + RECT 52.365 0.045 52.515 0.195 ; + RECT 22.925 0.045 23.075 0.195 ; + LAYER via2 ; + RECT 52.34 75.94 52.54 76.14 ; + RECT 22.9 75.94 23.1 76.14 ; + RECT 74.19 13.84 74.39 14.04 ; + RECT 52.34 0.02 52.54 0.22 ; + RECT 22.9 0.02 23.1 0.22 ; + LAYER via3 ; + RECT 52.34 75.94 52.54 76.14 ; + RECT 22.9 75.94 23.1 76.14 ; + RECT 52.34 0.02 52.54 0.22 ; + RECT 22.9 0.02 23.1 0.22 ; + LAYER OVERLAP ; + POLYGON 0 0 0 76.16 75.44 76.16 75.44 0 ; + END +END cbx_1__2_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/cby_0__1__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/cby_0__1__icv_in_design.lef new file mode 100644 index 0000000..9347fb6 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/cby_0__1__icv_in_design.lef @@ -0,0 +1,1651 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO cby_0__1_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 73.6 BY 87.04 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.3 0.595 44.44 ; + END + END pReset[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 26.84 0 26.98 0.485 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.72 0 62.86 0.485 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 0 14.1 0.485 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.28 0 10.42 0.485 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.32 0 44.46 0.485 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.32 0 21.46 0.485 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.04 0 13.18 0.485 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.12 0 35.26 0.485 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.8 0 61.94 0.485 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.88 0 15.02 0.485 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.4 0 43.54 0.485 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 20.4 0 20.54 0.485 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25 0 25.14 0.485 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.8 0 15.94 0.485 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.16 0 46.3 0.485 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.04 0 36.18 0.485 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.48 0 42.62 0.485 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.48 0 19.62 0.485 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.28 0 33.42 0.485 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 0 37.1 0.485 ; + END + END chany_bottom_in[19] + PIN chany_bottom_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.56 0 41.7 0.485 ; + END + END chany_bottom_in[20] + PIN chany_bottom_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.72 0 16.86 0.485 ; + END + END chany_bottom_in[21] + PIN chany_bottom_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.2 0 11.34 0.485 ; + END + END chany_bottom_in[22] + PIN chany_bottom_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.88 0 38.02 0.485 ; + END + END chany_bottom_in[23] + PIN chany_bottom_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.08 0 47.22 0.485 ; + END + END chany_bottom_in[24] + PIN chany_bottom_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.64 0 40.78 0.485 ; + END + END chany_bottom_in[25] + PIN chany_bottom_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.8 0 38.94 0.485 ; + END + END chany_bottom_in[26] + PIN chany_bottom_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.56 0 18.7 0.485 ; + END + END chany_bottom_in[27] + PIN chany_bottom_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.64 0 17.78 0.485 ; + END + END chany_bottom_in[28] + PIN chany_bottom_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.72 0 39.86 0.485 ; + END + END chany_bottom_in[29] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.36 86.555 9.5 87.04 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.72 86.555 62.86 87.04 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.56 86.555 41.7 87.04 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.52 86.555 7.66 87.04 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.16 86.555 23.3 87.04 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.88 86.555 38.02 87.04 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.6 86.555 6.74 87.04 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.04 86.555 13.18 87.04 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.24 86.555 22.38 87.04 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.8 86.555 61.94 87.04 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.64 86.555 40.78 87.04 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.8 86.555 38.94 87.04 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.2 86.555 11.34 87.04 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 86.555 14.1 87.04 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.32 86.555 67.46 87.04 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.32 86.555 21.46 87.04 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.46 86.555 2.6 87.04 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.88 86.555 15.02 87.04 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.04 86.555 36.18 87.04 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 20.4 86.555 20.54 87.04 ; + END + END chany_top_in[19] + PIN chany_top_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.8 86.555 15.94 87.04 ; + END + END chany_top_in[20] + PIN chany_top_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.48 86.555 19.62 87.04 ; + END + END chany_top_in[21] + PIN chany_top_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.28 86.555 10.42 87.04 ; + END + END chany_top_in[22] + PIN chany_top_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.72 86.555 16.86 87.04 ; + END + END chany_top_in[23] + PIN chany_top_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25 86.555 25.14 87.04 ; + END + END chany_top_in[24] + PIN chany_top_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.56 86.555 18.7 87.04 ; + END + END chany_top_in[25] + PIN chany_top_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.72 86.555 39.86 87.04 ; + END + END chany_top_in[26] + PIN chany_top_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.64 86.555 17.78 87.04 ; + END + END chany_top_in[27] + PIN chany_top_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.3 86.555 4.44 87.04 ; + END + END chany_top_in[28] + PIN chany_top_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.38 86.555 3.52 87.04 ; + END + END chany_top_in[29] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.08 86.555 24.22 87.04 ; + END + END ccff_head[0] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.16 0 69.3 0.485 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.36 0 55.5 0.485 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.2 0 57.34 0.485 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.68 0 28.82 0.485 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.48 0 65.62 0.485 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 0 64.7 0.485 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.44 0 8.58 0.485 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.12 0 12.26 0.485 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.16 0 23.3 0.485 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.24 0 22.38 0.485 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.08 0 24.22 0.485 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 31.44 0 31.58 0.485 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.52 0 30.66 0.485 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.4 0 66.54 0.485 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.28 0 56.42 0.485 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.88 0 61.02 0.485 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.2 0 34.34 0.485 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.24 0 45.38 0.485 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.52 0 7.66 0.485 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.36 0 32.5 0.485 ; + END + END chany_bottom_out[19] + PIN chany_bottom_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.96 0 60.1 0.485 ; + END + END chany_bottom_out[20] + PIN chany_bottom_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.64 0 63.78 0.485 ; + END + END chany_bottom_out[21] + PIN chany_bottom_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.36 0 9.5 0.485 ; + END + END chany_bottom_out[22] + PIN chany_bottom_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.92 0 26.06 0.485 ; + END + END chany_bottom_out[23] + PIN chany_bottom_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.76 0 27.9 0.485 ; + END + END chany_bottom_out[24] + PIN chany_bottom_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.6 0 6.74 0.485 ; + END + END chany_bottom_out[25] + PIN chany_bottom_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48 0 48.14 0.485 ; + END + END chany_bottom_out[26] + PIN chany_bottom_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.24 0 68.38 0.485 ; + END + END chany_bottom_out[27] + PIN chany_bottom_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.32 0 67.46 0.485 ; + END + END chany_bottom_out[28] + PIN chany_bottom_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 0 58.26 0.485 ; + END + END chany_bottom_out[29] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.24 86.555 68.38 87.04 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.52 86.555 53.66 87.04 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.44 86.555 54.58 87.04 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 17.79 86.24 18.09 87.04 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.64 86.555 63.78 87.04 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.96 86.555 60.1 87.04 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.52 86.555 30.66 87.04 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.48 86.555 42.62 87.04 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 86.555 37.1 87.04 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.36 86.555 55.5 87.04 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 5.68 86.555 5.82 87.04 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.2 86.555 34.34 87.04 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.76 86.555 50.9 87.04 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 86.555 58.26 87.04 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 86.555 64.7 87.04 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.54 86.555 70.68 87.04 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.62 86.555 69.76 87.04 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 19.63 86.24 19.93 87.04 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.24 86.555 45.38 87.04 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.12 86.555 12.26 87.04 ; + END + END chany_top_out[19] + PIN chany_top_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.32 86.555 44.46 87.04 ; + END + END chany_top_out[20] + PIN chany_top_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.4 86.555 66.54 87.04 ; + END + END chany_top_out[21] + PIN chany_top_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.12 86.555 35.26 87.04 ; + END + END chany_top_out[22] + PIN chany_top_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.44 86.555 8.58 87.04 ; + END + END chany_top_out[23] + PIN chany_top_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 21.47 86.24 21.77 87.04 ; + END + END chany_top_out[24] + PIN chany_top_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.48 86.555 65.62 87.04 ; + END + END chany_top_out[25] + PIN chany_top_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.4 86.555 43.54 87.04 ; + END + END chany_top_out[26] + PIN chany_top_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.88 86.555 61.02 87.04 ; + END + END chany_top_out[27] + PIN chany_top_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.28 86.555 56.42 87.04 ; + END + END chany_top_out[28] + PIN chany_top_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.2 86.555 57.34 87.04 ; + END + END chany_top_out[29] + PIN left_grid_pin_0_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 34.1 73.6 34.24 ; + END + END left_grid_pin_0_[0] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 75.24 73.6 75.38 ; + END + END ccff_tail[0] + PIN IO_ISOL_N[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 1.8 73.6 1.94 ; + END + END IO_ISOL_N[0] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 9.28 0.595 9.42 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 29 0.595 29.14 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 20.84 0.595 20.98 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] + PIN right_width_0_height_0__pin_0_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 33.42 73.6 33.56 ; + END + END right_width_0_height_0__pin_0_[0] + PIN right_width_0_height_0__pin_1_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.6 86.555 52.74 87.04 ; + END + END right_width_0_height_0__pin_1_upper[0] + PIN right_width_0_height_0__pin_1_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.44 0 54.58 0.485 ; + END + END right_width_0_height_0__pin_1_lower[0] + PIN pReset_N_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.68 86.555 28.82 87.04 ; + END + END pReset_N_in + PIN prog_clk_0_E_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met1 ; + RECT 73.005 30.7 73.6 30.84 ; + END + END prog_clk_0_E_in + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 1.12 3.2 4.32 ; + RECT 70.4 1.12 73.6 4.32 ; + RECT 0 41.92 3.2 45.12 ; + RECT 70.4 41.92 73.6 45.12 ; + RECT 0 82.72 3.2 85.92 ; + RECT 70.4 82.72 73.6 85.92 ; + LAYER met4 ; + RECT 14.42 0 15.02 0.6 ; + RECT 43.86 0 44.46 0.6 ; + RECT 14.42 86.44 15.02 87.04 ; + RECT 43.86 86.44 44.46 87.04 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 73.12 2.48 73.6 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 73.12 7.92 73.6 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 73.12 13.36 73.6 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 73.12 18.8 73.6 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 73.12 24.24 73.6 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 73.12 29.68 73.6 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 73.12 35.12 73.6 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 73.12 40.56 73.6 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 73.12 46 73.6 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 73.12 51.44 73.6 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 73.12 56.88 73.6 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 73.12 62.32 73.6 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 73.12 67.76 73.6 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 73.12 73.2 73.6 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 73.12 78.64 73.6 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 73.12 84.08 73.6 84.56 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 21.52 3.2 24.72 ; + RECT 70.4 21.52 73.6 24.72 ; + RECT 0 62.32 3.2 65.52 ; + RECT 70.4 62.32 73.6 65.52 ; + LAYER met4 ; + RECT 29.14 0 29.74 0.6 ; + RECT 58.58 0 59.18 0.6 ; + RECT 29.14 86.44 29.74 87.04 ; + RECT 58.58 86.44 59.18 87.04 ; + LAYER met1 ; + RECT 0 -0.24 0.48 0.24 ; + RECT 73.12 -0.24 73.6 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 73.12 5.2 73.6 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 73.12 10.64 73.6 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 73.12 16.08 73.6 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 73.12 21.52 73.6 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 73.12 26.96 73.6 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 73.12 32.4 73.6 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 73.12 37.84 73.6 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 73.12 43.28 73.6 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 73.12 48.72 73.6 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 73.12 54.16 73.6 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 73.12 59.6 73.6 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 73.12 65.04 73.6 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 73.12 70.48 73.6 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 73.12 75.92 73.6 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 73.12 81.36 73.6 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 73.12 86.8 73.6 87.28 ; + END + END VSS + OBS + LAYER met1 ; + POLYGON 72.84 87.28 72.84 86.8 59.04 86.8 59.04 86.79 58.72 86.79 58.72 86.8 29.6 86.8 29.6 86.79 29.28 86.79 29.28 86.8 0.76 86.8 0.76 87.28 ; + POLYGON 59.04 0.25 59.04 0.24 72.84 0.24 72.84 -0.24 0.76 -0.24 0.76 0.24 29.28 0.24 29.28 0.25 29.6 0.25 29.6 0.24 58.72 0.24 58.72 0.25 ; + POLYGON 72.84 86.76 72.84 86.52 73.32 86.52 73.32 84.84 72.84 84.84 72.84 83.8 73.32 83.8 73.32 82.12 72.84 82.12 72.84 81.08 73.32 81.08 73.32 79.4 72.84 79.4 72.84 78.36 73.32 78.36 73.32 76.68 72.84 76.68 72.84 75.66 72.725 75.66 72.725 74.96 73.32 74.96 73.32 73.96 72.84 73.96 72.84 72.92 73.32 72.92 73.32 71.24 72.84 71.24 72.84 70.2 73.32 70.2 73.32 68.52 72.84 68.52 72.84 67.48 73.32 67.48 73.32 65.8 72.84 65.8 72.84 64.76 73.32 64.76 73.32 63.08 72.84 63.08 72.84 62.04 73.32 62.04 73.32 60.36 72.84 60.36 72.84 59.32 73.32 59.32 73.32 57.64 72.84 57.64 72.84 56.6 73.32 56.6 73.32 54.92 72.84 54.92 72.84 53.88 73.32 53.88 73.32 52.2 72.84 52.2 72.84 51.16 73.32 51.16 73.32 49.48 72.84 49.48 72.84 48.44 73.32 48.44 73.32 46.76 72.84 46.76 72.84 45.72 73.32 45.72 73.32 44.04 72.84 44.04 72.84 43 73.32 43 73.32 41.32 72.84 41.32 72.84 40.28 73.32 40.28 73.32 38.6 72.84 38.6 72.84 37.56 73.32 37.56 73.32 35.88 72.84 35.88 72.84 34.84 73.32 34.84 73.32 34.52 72.725 34.52 72.725 33.14 72.84 33.14 72.84 32.12 73.32 32.12 73.32 31.12 72.725 31.12 72.725 30.42 72.84 30.42 72.84 29.4 73.32 29.4 73.32 27.72 72.84 27.72 72.84 26.68 73.32 26.68 73.32 25 72.84 25 72.84 23.96 73.32 23.96 73.32 22.28 72.84 22.28 72.84 21.24 73.32 21.24 73.32 19.56 72.84 19.56 72.84 18.52 73.32 18.52 73.32 16.84 72.84 16.84 72.84 15.8 73.32 15.8 73.32 14.12 72.84 14.12 72.84 13.08 73.32 13.08 73.32 11.4 72.84 11.4 72.84 10.36 73.32 10.36 73.32 8.68 72.84 8.68 72.84 7.64 73.32 7.64 73.32 5.96 72.84 5.96 72.84 4.92 73.32 4.92 73.32 3.24 72.84 3.24 72.84 2.22 72.725 2.22 72.725 1.52 73.32 1.52 73.32 0.52 72.84 0.52 72.84 0.28 0.76 0.28 0.76 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 9 0.875 9 0.875 9.7 0.28 9.7 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 20.56 0.875 20.56 0.875 21.26 0.76 21.26 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 28.72 0.875 28.72 0.875 29.42 0.76 29.42 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.02 0.875 44.02 0.875 44.72 0.28 44.72 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 86.76 ; + LAYER met2 ; + RECT 58.74 86.735 59.02 87.105 ; + RECT 29.3 86.735 29.58 87.105 ; + RECT 16.2 86.03 16.46 86.35 ; + POLYGON 15.48 15.2 15.48 0.1 15.3 0.1 15.3 0.24 15.34 0.24 15.34 15.2 ; + POLYGON 44.92 14.18 44.92 0.1 44.74 0.1 44.74 0.24 44.78 0.24 44.78 14.18 ; + RECT 40.12 0.69 40.38 1.01 ; + RECT 56.68 0.35 56.94 0.67 ; + RECT 58.74 -0.065 59.02 0.305 ; + RECT 29.3 -0.065 29.58 0.305 ; + POLYGON 73.32 86.76 73.32 0.28 69.58 0.28 69.58 0.765 68.88 0.765 68.88 0.28 68.66 0.28 68.66 0.765 67.96 0.765 67.96 0.28 67.74 0.28 67.74 0.765 67.04 0.765 67.04 0.28 66.82 0.28 66.82 0.765 66.12 0.765 66.12 0.28 65.9 0.28 65.9 0.765 65.2 0.765 65.2 0.28 64.98 0.28 64.98 0.765 64.28 0.765 64.28 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 63.14 0.28 63.14 0.765 62.44 0.765 62.44 0.28 62.22 0.28 62.22 0.765 61.52 0.765 61.52 0.28 61.3 0.28 61.3 0.765 60.6 0.765 60.6 0.28 60.38 0.28 60.38 0.765 59.68 0.765 59.68 0.28 58.54 0.28 58.54 0.765 57.84 0.765 57.84 0.28 57.62 0.28 57.62 0.765 56.92 0.765 56.92 0.28 56.7 0.28 56.7 0.765 56 0.765 56 0.28 55.78 0.28 55.78 0.765 55.08 0.765 55.08 0.28 54.86 0.28 54.86 0.765 54.16 0.765 54.16 0.28 48.42 0.28 48.42 0.765 47.72 0.765 47.72 0.28 47.5 0.28 47.5 0.765 46.8 0.765 46.8 0.28 46.58 0.28 46.58 0.765 45.88 0.765 45.88 0.28 45.66 0.28 45.66 0.765 44.96 0.765 44.96 0.28 44.74 0.28 44.74 0.765 44.04 0.765 44.04 0.28 43.82 0.28 43.82 0.765 43.12 0.765 43.12 0.28 42.9 0.28 42.9 0.765 42.2 0.765 42.2 0.28 41.98 0.28 41.98 0.765 41.28 0.765 41.28 0.28 41.06 0.28 41.06 0.765 40.36 0.765 40.36 0.28 40.14 0.28 40.14 0.765 39.44 0.765 39.44 0.28 39.22 0.28 39.22 0.765 38.52 0.765 38.52 0.28 38.3 0.28 38.3 0.765 37.6 0.765 37.6 0.28 37.38 0.28 37.38 0.765 36.68 0.765 36.68 0.28 36.46 0.28 36.46 0.765 35.76 0.765 35.76 0.28 35.54 0.28 35.54 0.765 34.84 0.765 34.84 0.28 34.62 0.28 34.62 0.765 33.92 0.765 33.92 0.28 33.7 0.28 33.7 0.765 33 0.765 33 0.28 32.78 0.28 32.78 0.765 32.08 0.765 32.08 0.28 31.86 0.28 31.86 0.765 31.16 0.765 31.16 0.28 30.94 0.28 30.94 0.765 30.24 0.765 30.24 0.28 29.1 0.28 29.1 0.765 28.4 0.765 28.4 0.28 28.18 0.28 28.18 0.765 27.48 0.765 27.48 0.28 27.26 0.28 27.26 0.765 26.56 0.765 26.56 0.28 26.34 0.28 26.34 0.765 25.64 0.765 25.64 0.28 25.42 0.28 25.42 0.765 24.72 0.765 24.72 0.28 24.5 0.28 24.5 0.765 23.8 0.765 23.8 0.28 23.58 0.28 23.58 0.765 22.88 0.765 22.88 0.28 22.66 0.28 22.66 0.765 21.96 0.765 21.96 0.28 21.74 0.28 21.74 0.765 21.04 0.765 21.04 0.28 20.82 0.28 20.82 0.765 20.12 0.765 20.12 0.28 19.9 0.28 19.9 0.765 19.2 0.765 19.2 0.28 18.98 0.28 18.98 0.765 18.28 0.765 18.28 0.28 18.06 0.28 18.06 0.765 17.36 0.765 17.36 0.28 17.14 0.28 17.14 0.765 16.44 0.765 16.44 0.28 16.22 0.28 16.22 0.765 15.52 0.765 15.52 0.28 15.3 0.28 15.3 0.765 14.6 0.765 14.6 0.28 14.38 0.28 14.38 0.765 13.68 0.765 13.68 0.28 13.46 0.28 13.46 0.765 12.76 0.765 12.76 0.28 12.54 0.28 12.54 0.765 11.84 0.765 11.84 0.28 11.62 0.28 11.62 0.765 10.92 0.765 10.92 0.28 10.7 0.28 10.7 0.765 10 0.765 10 0.28 9.78 0.28 9.78 0.765 9.08 0.765 9.08 0.28 8.86 0.28 8.86 0.765 8.16 0.765 8.16 0.28 7.94 0.28 7.94 0.765 7.24 0.765 7.24 0.28 7.02 0.28 7.02 0.765 6.32 0.765 6.32 0.28 0.28 0.28 0.28 86.76 2.18 86.76 2.18 86.275 2.88 86.275 2.88 86.76 3.1 86.76 3.1 86.275 3.8 86.275 3.8 86.76 4.02 86.76 4.02 86.275 4.72 86.275 4.72 86.76 5.4 86.76 5.4 86.275 6.1 86.275 6.1 86.76 6.32 86.76 6.32 86.275 7.02 86.275 7.02 86.76 7.24 86.76 7.24 86.275 7.94 86.275 7.94 86.76 8.16 86.76 8.16 86.275 8.86 86.275 8.86 86.76 9.08 86.76 9.08 86.275 9.78 86.275 9.78 86.76 10 86.76 10 86.275 10.7 86.275 10.7 86.76 10.92 86.76 10.92 86.275 11.62 86.275 11.62 86.76 11.84 86.76 11.84 86.275 12.54 86.275 12.54 86.76 12.76 86.76 12.76 86.275 13.46 86.275 13.46 86.76 13.68 86.76 13.68 86.275 14.38 86.275 14.38 86.76 14.6 86.76 14.6 86.275 15.3 86.275 15.3 86.76 15.52 86.76 15.52 86.275 16.22 86.275 16.22 86.76 16.44 86.76 16.44 86.275 17.14 86.275 17.14 86.76 17.36 86.76 17.36 86.275 18.06 86.275 18.06 86.76 18.28 86.76 18.28 86.275 18.98 86.275 18.98 86.76 19.2 86.76 19.2 86.275 19.9 86.275 19.9 86.76 20.12 86.76 20.12 86.275 20.82 86.275 20.82 86.76 21.04 86.76 21.04 86.275 21.74 86.275 21.74 86.76 21.96 86.76 21.96 86.275 22.66 86.275 22.66 86.76 22.88 86.76 22.88 86.275 23.58 86.275 23.58 86.76 23.8 86.76 23.8 86.275 24.5 86.275 24.5 86.76 24.72 86.76 24.72 86.275 25.42 86.275 25.42 86.76 28.4 86.76 28.4 86.275 29.1 86.275 29.1 86.76 30.24 86.76 30.24 86.275 30.94 86.275 30.94 86.76 33.92 86.76 33.92 86.275 34.62 86.275 34.62 86.76 34.84 86.76 34.84 86.275 35.54 86.275 35.54 86.76 35.76 86.76 35.76 86.275 36.46 86.275 36.46 86.76 36.68 86.76 36.68 86.275 37.38 86.275 37.38 86.76 37.6 86.76 37.6 86.275 38.3 86.275 38.3 86.76 38.52 86.76 38.52 86.275 39.22 86.275 39.22 86.76 39.44 86.76 39.44 86.275 40.14 86.275 40.14 86.76 40.36 86.76 40.36 86.275 41.06 86.275 41.06 86.76 41.28 86.76 41.28 86.275 41.98 86.275 41.98 86.76 42.2 86.76 42.2 86.275 42.9 86.275 42.9 86.76 43.12 86.76 43.12 86.275 43.82 86.275 43.82 86.76 44.04 86.76 44.04 86.275 44.74 86.275 44.74 86.76 44.96 86.76 44.96 86.275 45.66 86.275 45.66 86.76 50.48 86.76 50.48 86.275 51.18 86.275 51.18 86.76 52.32 86.76 52.32 86.275 53.02 86.275 53.02 86.76 53.24 86.76 53.24 86.275 53.94 86.275 53.94 86.76 54.16 86.76 54.16 86.275 54.86 86.275 54.86 86.76 55.08 86.76 55.08 86.275 55.78 86.275 55.78 86.76 56 86.76 56 86.275 56.7 86.275 56.7 86.76 56.92 86.76 56.92 86.275 57.62 86.275 57.62 86.76 57.84 86.76 57.84 86.275 58.54 86.275 58.54 86.76 59.68 86.76 59.68 86.275 60.38 86.275 60.38 86.76 60.6 86.76 60.6 86.275 61.3 86.275 61.3 86.76 61.52 86.76 61.52 86.275 62.22 86.275 62.22 86.76 62.44 86.76 62.44 86.275 63.14 86.275 63.14 86.76 63.36 86.76 63.36 86.275 64.06 86.275 64.06 86.76 64.28 86.76 64.28 86.275 64.98 86.275 64.98 86.76 65.2 86.76 65.2 86.275 65.9 86.275 65.9 86.76 66.12 86.76 66.12 86.275 66.82 86.275 66.82 86.76 67.04 86.76 67.04 86.275 67.74 86.275 67.74 86.76 67.96 86.76 67.96 86.275 68.66 86.275 68.66 86.76 69.34 86.76 69.34 86.275 70.04 86.275 70.04 86.76 70.26 86.76 70.26 86.275 70.96 86.275 70.96 86.76 ; + LAYER met4 ; + POLYGON 30.985 86.865 30.985 86.535 30.97 86.535 30.97 26.03 30.67 26.03 30.67 86.535 30.655 86.535 30.655 86.865 ; + POLYGON 73.2 86.64 73.2 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 15.42 0.4 15.42 1 14.02 1 14.02 0.4 0.4 0.4 0.4 86.64 14.02 86.64 14.02 86.04 15.42 86.04 15.42 86.64 17.39 86.64 17.39 85.84 18.49 85.84 18.49 86.64 19.23 86.64 19.23 85.84 20.33 85.84 20.33 86.64 21.07 86.64 21.07 85.84 22.17 85.84 22.17 86.64 28.74 86.64 28.74 86.04 30.14 86.04 30.14 86.64 43.46 86.64 43.46 86.04 44.86 86.04 44.86 86.64 58.18 86.64 58.18 86.04 59.58 86.04 59.58 86.64 ; + LAYER met5 ; + RECT 4.8 82.72 68.8 85.92 ; + RECT 4.8 1.12 68.8 4.32 ; + POLYGON 68.8 85.44 68.8 81.12 72 81.12 72 67.12 68.8 67.12 68.8 60.72 72 60.72 72 46.72 68.8 46.72 68.8 40.32 72 40.32 72 26.32 68.8 26.32 68.8 19.92 72 19.92 72 5.92 68.8 5.92 68.8 1.6 4.8 1.6 4.8 5.92 1.6 5.92 1.6 19.92 4.8 19.92 4.8 26.32 1.6 26.32 1.6 40.32 4.8 40.32 4.8 46.72 1.6 46.72 1.6 60.72 4.8 60.72 4.8 67.12 1.6 67.12 1.6 81.12 4.8 81.12 4.8 85.44 ; + LAYER li1 ; + POLYGON 73.6 87.125 73.6 86.955 67.535 86.955 67.535 86.23 67.245 86.23 67.245 86.955 63.965 86.955 63.965 86.475 63.795 86.475 63.795 86.955 63.125 86.955 63.125 86.475 62.955 86.475 62.955 86.955 62.365 86.955 62.365 86.475 62.035 86.475 62.035 86.955 61.525 86.955 61.525 86.475 61.195 86.475 61.195 86.955 60.685 86.955 60.685 86.155 60.355 86.155 60.355 86.955 52.355 86.955 52.355 86.23 52.065 86.23 52.065 86.955 43.685 86.955 43.685 86.155 43.355 86.155 43.355 86.955 42.845 86.955 42.845 86.475 42.515 86.475 42.515 86.955 42.005 86.955 42.005 86.475 41.675 86.475 41.675 86.955 41.165 86.955 41.165 86.475 40.835 86.475 40.835 86.955 40.325 86.955 40.325 86.475 39.995 86.475 39.995 86.955 39.485 86.955 39.485 86.475 39.155 86.475 39.155 86.955 37.635 86.955 37.635 86.23 37.345 86.23 37.345 86.955 34.405 86.955 34.405 86.155 34.075 86.155 34.075 86.955 33.565 86.955 33.565 86.475 33.235 86.475 33.235 86.955 32.725 86.955 32.725 86.475 32.395 86.475 32.395 86.955 31.805 86.955 31.805 86.475 31.635 86.475 31.635 86.955 30.965 86.955 30.965 86.475 30.795 86.475 30.795 86.955 28.505 86.955 28.505 86.155 28.175 86.155 28.175 86.955 27.665 86.955 27.665 86.475 27.335 86.475 27.335 86.955 26.825 86.955 26.825 86.475 26.495 86.475 26.495 86.955 25.985 86.955 25.985 86.475 25.655 86.475 25.655 86.955 25.145 86.955 25.145 86.475 24.815 86.475 24.815 86.955 24.305 86.955 24.305 86.475 23.975 86.475 23.975 86.955 22.455 86.955 22.455 86.23 22.165 86.23 22.165 86.955 18.385 86.955 18.385 86.155 18.055 86.155 18.055 86.955 17.545 86.955 17.545 86.475 17.215 86.475 17.215 86.955 16.705 86.955 16.705 86.475 16.375 86.475 16.375 86.955 15.865 86.955 15.865 86.475 15.535 86.475 15.535 86.955 15.025 86.955 15.025 86.475 14.695 86.475 14.695 86.955 14.185 86.955 14.185 86.475 13.855 86.475 13.855 86.955 12.865 86.955 12.865 86.155 12.535 86.155 12.535 86.955 12.025 86.955 12.025 86.475 11.695 86.475 11.695 86.955 11.185 86.955 11.185 86.475 10.855 86.475 10.855 86.955 10.345 86.955 10.345 86.475 10.015 86.475 10.015 86.955 9.505 86.955 9.505 86.475 9.175 86.475 9.175 86.955 8.665 86.955 8.665 86.475 8.335 86.475 8.335 86.955 7.735 86.955 7.735 86.23 7.445 86.23 7.445 86.955 0 86.955 0 87.125 ; + RECT 73.14 84.235 73.6 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 72.68 81.515 73.6 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 72.68 78.795 73.6 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 73.14 76.075 73.6 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 73.14 73.355 73.6 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 72.68 70.635 73.6 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 72.68 67.915 73.6 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 72.68 65.195 73.6 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 72.68 62.475 73.6 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 72.68 59.755 73.6 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 72.68 57.035 73.6 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 72.68 54.315 73.6 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 72.68 51.595 73.6 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 72.68 48.875 73.6 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 72.68 46.155 73.6 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 72.68 43.435 73.6 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 72.68 40.715 73.6 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 72.68 37.995 73.6 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 72.68 35.275 73.6 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 73.14 32.555 73.6 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 73.14 29.835 73.6 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 73.14 27.115 73.6 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 73.14 24.395 73.6 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 72.68 21.675 73.6 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 72.68 18.955 73.6 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 73.14 16.235 73.6 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 73.14 13.515 73.6 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 71.76 10.795 73.6 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 71.76 8.075 73.6 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 73.14 5.355 73.6 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 73.14 2.635 73.6 2.805 ; + RECT 0 2.635 3.68 2.805 ; + POLYGON 62.545 0.885 62.545 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 73.6 0.085 73.6 -0.085 0 -0.085 0 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 16.655 0.085 16.655 0.885 16.985 0.885 16.985 0.085 17.495 0.085 17.495 0.565 17.825 0.565 17.825 0.085 18.335 0.085 18.335 0.565 18.665 0.565 18.665 0.085 19.255 0.085 19.255 0.565 19.425 0.565 19.425 0.085 20.095 0.085 20.095 0.565 20.265 0.565 20.265 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 28.575 0.085 28.575 0.565 28.905 0.565 28.905 0.085 29.415 0.085 29.415 0.565 29.745 0.565 29.745 0.085 30.255 0.085 30.255 0.565 30.585 0.565 30.585 0.085 31.095 0.085 31.095 0.565 31.425 0.565 31.425 0.085 31.935 0.085 31.935 0.565 32.265 0.565 32.265 0.085 32.775 0.085 32.775 0.885 33.105 0.885 33.105 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 38.615 0.085 38.615 0.565 38.785 0.565 38.785 0.085 39.455 0.085 39.455 0.565 39.625 0.565 39.625 0.085 40.215 0.085 40.215 0.565 40.545 0.565 40.545 0.085 41.055 0.085 41.055 0.565 41.385 0.565 41.385 0.085 41.895 0.085 41.895 0.885 42.225 0.885 42.225 0.085 45.055 0.085 45.055 0.565 45.225 0.565 45.225 0.085 45.895 0.085 45.895 0.565 46.065 0.565 46.065 0.085 46.655 0.085 46.655 0.565 46.985 0.565 46.985 0.085 47.495 0.085 47.495 0.565 47.825 0.565 47.825 0.085 48.335 0.085 48.335 0.885 48.665 0.885 48.665 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 53.455 0.085 53.455 0.885 53.785 0.885 53.785 0.085 54.295 0.085 54.295 0.565 54.625 0.565 54.625 0.085 55.135 0.085 55.135 0.565 55.465 0.565 55.465 0.085 56.055 0.085 56.055 0.565 56.225 0.565 56.225 0.085 56.895 0.085 56.895 0.565 57.065 0.565 57.065 0.085 58.015 0.085 58.015 0.565 58.345 0.565 58.345 0.085 58.855 0.085 58.855 0.565 59.185 0.565 59.185 0.085 59.695 0.085 59.695 0.565 60.025 0.565 60.025 0.085 60.535 0.085 60.535 0.565 60.865 0.565 60.865 0.085 61.375 0.085 61.375 0.565 61.705 0.565 61.705 0.085 62.215 0.085 62.215 0.885 ; + RECT 0.17 0.17 73.43 86.87 ; + LAYER met3 ; + POLYGON 59.045 87.085 59.045 87.08 59.26 87.08 59.26 86.76 59.045 86.76 59.045 86.755 58.715 86.755 58.715 86.76 58.5 86.76 58.5 87.08 58.715 87.08 58.715 87.085 ; + POLYGON 29.605 87.085 29.605 87.08 29.82 87.08 29.82 86.76 29.605 86.76 29.605 86.755 29.275 86.755 29.275 86.76 29.06 86.76 29.06 87.08 29.275 87.08 29.275 87.085 ; + POLYGON 30.755 86.865 30.755 86.86 31.165 86.86 31.165 86.54 30.755 86.54 30.755 86.535 30.425 86.535 30.425 86.865 ; + POLYGON 59.045 0.285 59.045 0.28 59.26 0.28 59.26 -0.04 59.045 -0.04 59.045 -0.045 58.715 -0.045 58.715 -0.04 58.5 -0.04 58.5 0.28 58.715 0.28 58.715 0.285 ; + POLYGON 29.605 0.285 29.605 0.28 29.82 0.28 29.82 -0.04 29.605 -0.04 29.605 -0.045 29.275 -0.045 29.275 -0.04 29.06 -0.04 29.06 0.28 29.275 0.28 29.275 0.285 ; + RECT 0.4 0.4 73.2 86.64 ; + LAYER via ; + RECT 58.805 86.845 58.955 86.995 ; + RECT 29.365 86.845 29.515 86.995 ; + RECT 61.795 0.435 61.945 0.585 ; + RECT 58.805 0.045 58.955 0.195 ; + RECT 29.365 0.045 29.515 0.195 ; + LAYER via2 ; + RECT 58.78 86.82 58.98 87.02 ; + RECT 29.34 86.82 29.54 87.02 ; + RECT 30.49 86.6 30.69 86.8 ; + RECT 58.78 0.02 58.98 0.22 ; + RECT 29.34 0.02 29.54 0.22 ; + LAYER via3 ; + RECT 58.78 86.82 58.98 87.02 ; + RECT 29.34 86.82 29.54 87.02 ; + RECT 30.72 86.6 30.92 86.8 ; + RECT 58.78 0.02 58.98 0.22 ; + RECT 29.34 0.02 29.54 0.22 ; + LAYER via4 ; + RECT 43.76 84.72 44.56 85.52 ; + RECT 14.32 84.72 15.12 85.52 ; + RECT 43.76 1.52 44.56 2.32 ; + RECT 14.32 1.52 15.12 2.32 ; + LAYER OVERLAP ; + POLYGON 0 0 0 87.04 73.6 87.04 73.6 0 ; + END +END cby_0__1_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/cby_1__1__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/cby_1__1__icv_in_design.lef new file mode 100644 index 0000000..17bb41e --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/cby_1__1__icv_in_design.lef @@ -0,0 +1,1969 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO cby_1__1_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 73.6 BY 87.04 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.3 0.595 44.44 ; + END + END pReset[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.76 0 50.9 0.485 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.84 0 49.98 0.485 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.12 0 12.26 0.485 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.28 0 56.42 0.485 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.56 0 41.7 0.485 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.74 0 10.88 0.485 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.52 0 53.66 0.485 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.94 0 43.08 0.485 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.24 0 45.38 0.485 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.82 0 32.96 0.485 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 31.44 0 31.58 0.485 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.56 0 18.7 0.485 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.34 0 38.48 0.485 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48 0 48.14 0.485 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 0 14.1 0.485 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71 0 71.14 0.485 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.92 0 49.06 0.485 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.26 0 16.4 0.485 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.5 0 36.64 0.485 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 41.71 0 42.01 0.8 ; + END + END chany_bottom_in[19] + PIN chany_bottom_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.64 0 17.78 0.485 ; + END + END chany_bottom_in[20] + PIN chany_bottom_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.72 0 62.86 0.485 ; + END + END chany_bottom_in[21] + PIN chany_bottom_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.52 0 30.66 0.485 ; + END + END chany_bottom_in[22] + PIN chany_bottom_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.52 0 7.66 0.485 ; + END + END chany_bottom_in[23] + PIN chany_bottom_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.16 0 46.3 0.485 ; + END + END chany_bottom_in[24] + PIN chany_bottom_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.42 0 37.56 0.485 ; + END + END chany_bottom_in[25] + PIN chany_bottom_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.6 0 6.74 0.485 ; + END + END chany_bottom_in[26] + PIN chany_bottom_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.66 0 34.8 0.485 ; + END + END chany_bottom_in[27] + PIN chany_bottom_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.26 0 39.4 0.485 ; + END + END chany_bottom_in[28] + PIN chany_bottom_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.74 0 33.88 0.485 ; + END + END chany_bottom_in[29] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.78 86.555 44.92 87.04 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.34 86.555 15.48 87.04 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.12 86.555 12.26 87.04 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.02 86.555 42.16 87.04 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 56.43 86.24 56.73 87.04 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.2 86.555 11.34 87.04 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.78 86.555 21.92 87.04 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71 86.555 71.14 87.04 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.28 86.555 10.42 87.04 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.86 86.555 44 87.04 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.62 86.555 46.76 87.04 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.28 86.555 56.42 87.04 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.36 86.555 32.5 87.04 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 65.63 86.24 65.93 87.04 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.2 86.555 34.34 87.04 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 26.84 86.555 26.98 87.04 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.8 86.555 61.94 87.04 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 30.67 86.24 30.97 87.04 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.28 86.555 33.42 87.04 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.04 86.555 36.18 87.04 ; + END + END chany_top_in[19] + PIN chany_top_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.7 86.555 45.84 87.04 ; + END + END chany_top_in[20] + PIN chany_top_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.94 86.555 43.08 87.04 ; + END + END chany_top_in[21] + PIN chany_top_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.44 86.555 54.58 87.04 ; + END + END chany_top_in[22] + PIN chany_top_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 31.44 86.555 31.58 87.04 ; + END + END chany_top_in[23] + PIN chany_top_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.92 86.555 26.06 87.04 ; + END + END chany_top_in[24] + PIN chany_top_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 86.555 37.1 87.04 ; + END + END chany_top_in[25] + PIN chany_top_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 86.555 58.26 87.04 ; + END + END chany_top_in[26] + PIN chany_top_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.84 86.555 49.98 87.04 ; + END + END chany_top_in[27] + PIN chany_top_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.54 86.555 47.68 87.04 ; + END + END chany_top_in[28] + PIN chany_top_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.96 86.555 60.1 87.04 ; + END + END chany_top_in[29] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 75.24 0.595 75.38 ; + END + END ccff_head[0] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 68.39 0 68.69 0.8 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 57.35 0 57.65 0.8 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.32 0 21.46 0.485 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 65.63 0 65.93 0.8 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 39.87 0 40.17 0.8 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 30.67 0 30.97 0.8 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 53.67 0 53.97 0.8 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.2 0 57.34 0.485 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 61.95 0 62.25 0.8 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.44 0 54.58 0.485 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.36 0 55.5 0.485 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.68 0 51.82 0.485 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 36.19 0 36.49 0.8 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 51.83 0 52.13 0.8 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 60.11 0 60.41 0.8 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 49.99 0 50.29 0.8 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.16 0 69.3 0.485 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.58 0 35.72 0.485 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 0 64.7 0.485 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 48.15 0 48.45 0.8 ; + END + END chany_bottom_out[19] + PIN chany_bottom_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 38.03 0 38.33 0.8 ; + END + END chany_bottom_out[20] + PIN chany_bottom_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 32.51 0 32.81 0.8 ; + END + END chany_bottom_out[21] + PIN chany_bottom_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.08 0 70.22 0.485 ; + END + END chany_bottom_out[22] + PIN chany_bottom_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.08 0 47.22 0.485 ; + END + END chany_bottom_out[23] + PIN chany_bottom_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 46.31 0 46.61 0.8 ; + END + END chany_bottom_out[24] + PIN chany_bottom_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 34.35 0 34.65 0.8 ; + END + END chany_bottom_out[25] + PIN chany_bottom_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 63.79 0 64.09 0.8 ; + END + END chany_bottom_out[26] + PIN chany_bottom_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.64 0 63.78 0.485 ; + END + END chany_bottom_out[27] + PIN chany_bottom_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 55.51 0 55.81 0.8 ; + END + END chany_bottom_out[28] + PIN chany_bottom_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.5 0 59.64 0.485 ; + END + END chany_bottom_out[29] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 51.83 86.24 52.13 87.04 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25 86.555 25.14 87.04 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 38.03 86.24 38.33 87.04 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.64 86.555 63.78 87.04 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 49.99 86.24 50.29 87.04 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 68.39 86.24 68.69 87.04 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.46 86.555 48.6 87.04 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 36.19 86.24 36.49 87.04 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 46.31 86.24 46.61 87.04 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 54.59 86.24 54.89 87.04 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 61.95 86.24 62.25 87.04 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.76 86.555 27.9 87.04 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.72 86.555 62.86 87.04 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 40.79 86.24 41.09 87.04 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.52 86.555 53.66 87.04 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.16 86.555 69.3 87.04 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.08 86.555 70.22 87.04 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 34.35 86.24 34.65 87.04 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.88 86.555 38.02 87.04 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.36 86.555 55.5 87.04 ; + END + END chany_top_out[19] + PIN chany_top_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.42 86.555 14.56 87.04 ; + END + END chany_top_out[20] + PIN chany_top_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 32.51 86.24 32.81 87.04 ; + END + END chany_top_out[21] + PIN chany_top_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.68 86.555 28.82 87.04 ; + END + END chany_top_out[22] + PIN chany_top_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.12 86.555 35.26 87.04 ; + END + END chany_top_out[23] + PIN chany_top_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 60.11 86.24 60.41 87.04 ; + END + END chany_top_out[24] + PIN chany_top_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.2 86.555 57.34 87.04 ; + END + END chany_top_out[25] + PIN chany_top_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 63.79 86.24 64.09 87.04 ; + END + END chany_top_out[26] + PIN chany_top_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.88 86.555 61.02 87.04 ; + END + END chany_top_out[27] + PIN chany_top_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 48.15 86.24 48.45 87.04 ; + END + END chany_top_out[28] + PIN chany_top_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.8 86.555 38.94 87.04 ; + END + END chany_top_out[29] + PIN left_grid_pin_16_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 22.54 0.595 22.68 ; + END + END left_grid_pin_16_[0] + PIN left_grid_pin_17_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 14.72 0.595 14.86 ; + END + END left_grid_pin_17_[0] + PIN left_grid_pin_18_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 15.4 0.595 15.54 ; + END + END left_grid_pin_18_[0] + PIN left_grid_pin_19_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 23.22 0.595 23.36 ; + END + END left_grid_pin_19_[0] + PIN left_grid_pin_20_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 6.22 0.595 6.36 ; + END + END left_grid_pin_20_[0] + PIN left_grid_pin_21_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 6.9 0.595 7.04 ; + END + END left_grid_pin_21_[0] + PIN left_grid_pin_22_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 1.8 0.595 1.94 ; + END + END left_grid_pin_22_[0] + PIN left_grid_pin_23_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 4.52 0.595 4.66 ; + END + END left_grid_pin_23_[0] + PIN left_grid_pin_24_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 18.12 0.595 18.26 ; + END + END left_grid_pin_24_[0] + PIN left_grid_pin_25_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 17.44 0.595 17.58 ; + END + END left_grid_pin_25_[0] + PIN left_grid_pin_26_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 20.5 0.595 20.64 ; + END + END left_grid_pin_26_[0] + PIN left_grid_pin_27_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 19.82 0.595 19.96 ; + END + END left_grid_pin_27_[0] + PIN left_grid_pin_28_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 60.96 0.595 61.1 ; + END + END left_grid_pin_28_[0] + PIN left_grid_pin_29_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 64.02 0.595 64.16 ; + END + END left_grid_pin_29_[0] + PIN left_grid_pin_30_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 61.64 0.595 61.78 ; + END + END left_grid_pin_30_[0] + PIN left_grid_pin_31_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 63.34 0.595 63.48 ; + END + END left_grid_pin_31_[0] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 75.24 73.6 75.38 ; + END + END ccff_tail[0] + PIN Test_en_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.6 0 52.74 0.485 ; + END + END Test_en_S_in + PIN Test_en_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 28.32 73.6 28.46 ; + END + END Test_en_E_in + PIN Test_en_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 28.32 0.595 28.46 ; + END + END Test_en_W_in + PIN Test_en_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.76 86.555 50.9 87.04 ; + END + END Test_en_N_out + PIN Test_en_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 52.46 0.595 52.6 ; + END + END Test_en_W_out + PIN Test_en_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 53.14 73.6 53.28 ; + END + END Test_en_E_out + PIN pReset_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.3 0 4.44 0.485 ; + END + END pReset_S_in + PIN pReset_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.52 86.555 30.66 87.04 ; + END + END pReset_N_out + PIN Reset_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.32 0 44.46 0.485 ; + END + END Reset_S_in + PIN Reset_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 29 73.6 29.14 ; + END + END Reset_E_in + PIN Reset_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 50.76 0.595 50.9 ; + END + END Reset_W_in + PIN Reset_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.68 86.555 51.82 87.04 ; + END + END Reset_N_out + PIN Reset_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 29 0.595 29.14 ; + END + END Reset_W_out + PIN Reset_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 52.46 73.6 52.6 ; + END + END Reset_E_out + PIN prog_clk_0_W_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met1 ; + RECT 0 3.84 0.595 3.98 ; + END + END prog_clk_0_W_in + PIN prog_clk_0_S_out + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 3.38 0 3.52 0.485 ; + END + END prog_clk_0_S_out + PIN prog_clk_0_N_out + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 13.04 86.555 13.18 87.04 ; + END + END prog_clk_0_N_out + PIN prog_clk_2_N_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 86.555 64.7 87.04 ; + END + END prog_clk_2_N_in + PIN prog_clk_2_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.48 0 65.62 0.485 ; + END + END prog_clk_2_S_in + PIN prog_clk_2_S_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.64 0 40.78 0.485 ; + END + END prog_clk_2_S_out + PIN prog_clk_2_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.1 86.555 41.24 87.04 ; + END + END prog_clk_2_N_out + PIN prog_clk_3_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.42 0 60.56 0.485 ; + END + END prog_clk_3_S_in + PIN prog_clk_3_N_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.48 86.555 65.62 87.04 ; + END + END prog_clk_3_N_in + PIN prog_clk_3_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.4 86.555 66.54 87.04 ; + END + END prog_clk_3_N_out + PIN prog_clk_3_S_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.4 0 66.54 0.485 ; + END + END prog_clk_3_S_out + PIN clk_2_N_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.32 86.555 67.46 87.04 ; + END + END clk_2_N_in + PIN clk_2_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.32 0 67.46 0.485 ; + END + END clk_2_S_in + PIN clk_2_S_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.8 0 61.94 0.485 ; + END + END clk_2_S_out + PIN clk_2_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.18 86.555 40.32 87.04 ; + END + END clk_2_N_out + PIN clk_3_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.24 0 68.38 0.485 ; + END + END clk_3_S_in + PIN clk_3_N_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.24 86.555 68.38 87.04 ; + END + END clk_3_N_in + PIN clk_3_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.6 86.555 52.74 87.04 ; + END + END clk_3_N_out + PIN clk_3_S_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 0 58.26 0.485 ; + END + END clk_3_S_out + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 1.12 3.2 4.32 ; + RECT 70.4 1.12 73.6 4.32 ; + RECT 0 41.92 3.2 45.12 ; + RECT 70.4 41.92 73.6 45.12 ; + RECT 0 82.72 3.2 85.92 ; + RECT 70.4 82.72 73.6 85.92 ; + LAYER met4 ; + RECT 14.42 0 15.02 0.6 ; + RECT 43.86 0 44.46 0.6 ; + RECT 14.42 86.44 15.02 87.04 ; + RECT 43.86 86.44 44.46 87.04 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 73.12 2.48 73.6 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 73.12 7.92 73.6 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 73.12 13.36 73.6 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 73.12 18.8 73.6 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 73.12 24.24 73.6 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 73.12 29.68 73.6 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 73.12 35.12 73.6 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 73.12 40.56 73.6 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 73.12 46 73.6 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 73.12 51.44 73.6 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 73.12 56.88 73.6 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 73.12 62.32 73.6 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 73.12 67.76 73.6 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 73.12 73.2 73.6 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 73.12 78.64 73.6 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 73.12 84.08 73.6 84.56 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 21.52 3.2 24.72 ; + RECT 70.4 21.52 73.6 24.72 ; + RECT 0 62.32 3.2 65.52 ; + RECT 70.4 62.32 73.6 65.52 ; + LAYER met4 ; + RECT 29.14 0 29.74 0.6 ; + RECT 58.58 0 59.18 0.6 ; + RECT 29.14 86.44 29.74 87.04 ; + RECT 58.58 86.44 59.18 87.04 ; + LAYER met1 ; + RECT 0 -0.24 0.48 0.24 ; + RECT 73.12 -0.24 73.6 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 73.12 5.2 73.6 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 73.12 10.64 73.6 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 73.12 16.08 73.6 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 73.12 21.52 73.6 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 73.12 26.96 73.6 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 73.12 32.4 73.6 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 73.12 37.84 73.6 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 73.12 43.28 73.6 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 73.12 48.72 73.6 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 73.12 54.16 73.6 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 73.12 59.6 73.6 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 73.12 65.04 73.6 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 73.12 70.48 73.6 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 73.12 75.92 73.6 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 73.12 81.36 73.6 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 73.12 86.8 73.6 87.28 ; + END + END VSS + OBS + LAYER met1 ; + POLYGON 72.84 87.28 72.84 86.8 59.04 86.8 59.04 86.79 58.72 86.79 58.72 86.8 29.6 86.8 29.6 86.79 29.28 86.79 29.28 86.8 0.76 86.8 0.76 87.28 ; + POLYGON 59.04 0.25 59.04 0.24 72.84 0.24 72.84 -0.24 0.76 -0.24 0.76 0.24 29.28 0.24 29.28 0.25 29.6 0.25 29.6 0.24 58.72 0.24 58.72 0.25 ; + POLYGON 72.84 86.76 72.84 86.52 73.32 86.52 73.32 84.84 72.84 84.84 72.84 83.8 73.32 83.8 73.32 82.12 72.84 82.12 72.84 81.08 73.32 81.08 73.32 79.4 72.84 79.4 72.84 78.36 73.32 78.36 73.32 76.68 72.84 76.68 72.84 75.66 72.725 75.66 72.725 74.96 73.32 74.96 73.32 73.96 72.84 73.96 72.84 72.92 73.32 72.92 73.32 71.24 72.84 71.24 72.84 70.2 73.32 70.2 73.32 68.52 72.84 68.52 72.84 67.48 73.32 67.48 73.32 65.8 72.84 65.8 72.84 64.76 73.32 64.76 73.32 63.08 72.84 63.08 72.84 62.04 73.32 62.04 73.32 60.36 72.84 60.36 72.84 59.32 73.32 59.32 73.32 57.64 72.84 57.64 72.84 56.6 73.32 56.6 73.32 54.92 72.84 54.92 72.84 53.88 73.32 53.88 73.32 53.56 72.725 53.56 72.725 52.18 72.84 52.18 72.84 51.16 73.32 51.16 73.32 49.48 72.84 49.48 72.84 48.44 73.32 48.44 73.32 46.76 72.84 46.76 72.84 45.72 73.32 45.72 73.32 44.04 72.84 44.04 72.84 43 73.32 43 73.32 41.32 72.84 41.32 72.84 40.28 73.32 40.28 73.32 38.6 72.84 38.6 72.84 37.56 73.32 37.56 73.32 35.88 72.84 35.88 72.84 34.84 73.32 34.84 73.32 33.16 72.84 33.16 72.84 32.12 73.32 32.12 73.32 30.44 72.84 30.44 72.84 29.42 72.725 29.42 72.725 28.04 73.32 28.04 73.32 27.72 72.84 27.72 72.84 26.68 73.32 26.68 73.32 25 72.84 25 72.84 23.96 73.32 23.96 73.32 22.28 72.84 22.28 72.84 21.24 73.32 21.24 73.32 19.56 72.84 19.56 72.84 18.52 73.32 18.52 73.32 16.84 72.84 16.84 72.84 15.8 73.32 15.8 73.32 14.12 72.84 14.12 72.84 13.08 73.32 13.08 73.32 11.4 72.84 11.4 72.84 10.36 73.32 10.36 73.32 8.68 72.84 8.68 72.84 7.64 73.32 7.64 73.32 5.96 72.84 5.96 72.84 4.92 73.32 4.92 73.32 3.24 72.84 3.24 72.84 2.2 73.32 2.2 73.32 0.52 72.84 0.52 72.84 0.28 0.76 0.28 0.76 0.52 0.28 0.52 0.28 1.52 0.875 1.52 0.875 2.22 0.76 2.22 0.76 3.24 0.28 3.24 0.28 3.56 0.875 3.56 0.875 4.94 0.76 4.94 0.76 5.94 0.875 5.94 0.875 7.32 0.28 7.32 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 14.44 0.875 14.44 0.875 15.82 0.76 15.82 0.76 16.84 0.28 16.84 0.28 17.16 0.875 17.16 0.875 18.54 0.76 18.54 0.76 19.54 0.875 19.54 0.875 20.92 0.28 20.92 0.28 21.24 0.76 21.24 0.76 22.26 0.875 22.26 0.875 23.64 0.28 23.64 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 28.04 0.875 28.04 0.875 29.42 0.76 29.42 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.02 0.875 44.02 0.875 44.72 0.28 44.72 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 50.48 0.875 50.48 0.875 51.18 0.76 51.18 0.76 52.18 0.875 52.18 0.875 52.88 0.28 52.88 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 60.68 0.875 60.68 0.875 62.06 0.76 62.06 0.76 63.06 0.875 63.06 0.875 64.44 0.28 64.44 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 74.96 0.875 74.96 0.875 75.66 0.76 75.66 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 86.76 ; + LAYER met2 ; + RECT 58.74 86.735 59.02 87.105 ; + RECT 29.3 86.735 29.58 87.105 ; + POLYGON 53.24 86.94 53.24 86.8 53.2 86.8 53.2 79.83 53.06 79.83 53.06 86.94 ; + POLYGON 14.14 86.94 14.14 86.8 14.1 86.8 14.1 83.74 13.96 83.74 13.96 86.94 ; + RECT 66.82 86.37 67.06 86.69 ; + POLYGON 44.92 11.97 44.92 0.1 44.74 0.1 44.74 0.24 44.78 0.24 44.78 11.97 ; + RECT 58.74 -0.065 59.02 0.305 ; + RECT 29.3 -0.065 29.58 0.305 ; + POLYGON 73.32 86.76 73.32 0.28 71.42 0.28 71.42 0.765 70.72 0.765 70.72 0.28 70.5 0.28 70.5 0.765 69.8 0.765 69.8 0.28 69.58 0.28 69.58 0.765 68.88 0.765 68.88 0.28 68.66 0.28 68.66 0.765 67.96 0.765 67.96 0.28 67.74 0.28 67.74 0.765 67.04 0.765 67.04 0.28 66.82 0.28 66.82 0.765 66.12 0.765 66.12 0.28 65.9 0.28 65.9 0.765 65.2 0.765 65.2 0.28 64.98 0.28 64.98 0.765 64.28 0.765 64.28 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 63.14 0.28 63.14 0.765 62.44 0.765 62.44 0.28 62.22 0.28 62.22 0.765 61.52 0.765 61.52 0.28 60.84 0.28 60.84 0.765 60.14 0.765 60.14 0.28 59.92 0.28 59.92 0.765 59.22 0.765 59.22 0.28 58.54 0.28 58.54 0.765 57.84 0.765 57.84 0.28 57.62 0.28 57.62 0.765 56.92 0.765 56.92 0.28 56.7 0.28 56.7 0.765 56 0.765 56 0.28 55.78 0.28 55.78 0.765 55.08 0.765 55.08 0.28 54.86 0.28 54.86 0.765 54.16 0.765 54.16 0.28 53.94 0.28 53.94 0.765 53.24 0.765 53.24 0.28 53.02 0.28 53.02 0.765 52.32 0.765 52.32 0.28 52.1 0.28 52.1 0.765 51.4 0.765 51.4 0.28 51.18 0.28 51.18 0.765 50.48 0.765 50.48 0.28 50.26 0.28 50.26 0.765 49.56 0.765 49.56 0.28 49.34 0.28 49.34 0.765 48.64 0.765 48.64 0.28 48.42 0.28 48.42 0.765 47.72 0.765 47.72 0.28 47.5 0.28 47.5 0.765 46.8 0.765 46.8 0.28 46.58 0.28 46.58 0.765 45.88 0.765 45.88 0.28 45.66 0.28 45.66 0.765 44.96 0.765 44.96 0.28 44.74 0.28 44.74 0.765 44.04 0.765 44.04 0.28 43.36 0.28 43.36 0.765 42.66 0.765 42.66 0.28 41.98 0.28 41.98 0.765 41.28 0.765 41.28 0.28 41.06 0.28 41.06 0.765 40.36 0.765 40.36 0.28 39.68 0.28 39.68 0.765 38.98 0.765 38.98 0.28 38.76 0.28 38.76 0.765 38.06 0.765 38.06 0.28 37.84 0.28 37.84 0.765 37.14 0.765 37.14 0.28 36.92 0.28 36.92 0.765 36.22 0.765 36.22 0.28 36 0.28 36 0.765 35.3 0.765 35.3 0.28 35.08 0.28 35.08 0.765 34.38 0.765 34.38 0.28 34.16 0.28 34.16 0.765 33.46 0.765 33.46 0.28 33.24 0.28 33.24 0.765 32.54 0.765 32.54 0.28 31.86 0.28 31.86 0.765 31.16 0.765 31.16 0.28 30.94 0.28 30.94 0.765 30.24 0.765 30.24 0.28 21.74 0.28 21.74 0.765 21.04 0.765 21.04 0.28 18.98 0.28 18.98 0.765 18.28 0.765 18.28 0.28 18.06 0.28 18.06 0.765 17.36 0.765 17.36 0.28 16.68 0.28 16.68 0.765 15.98 0.765 15.98 0.28 14.38 0.28 14.38 0.765 13.68 0.765 13.68 0.28 12.54 0.28 12.54 0.765 11.84 0.765 11.84 0.28 11.16 0.28 11.16 0.765 10.46 0.765 10.46 0.28 7.94 0.28 7.94 0.765 7.24 0.765 7.24 0.28 7.02 0.28 7.02 0.765 6.32 0.765 6.32 0.28 4.72 0.28 4.72 0.765 4.02 0.765 4.02 0.28 3.8 0.28 3.8 0.765 3.1 0.765 3.1 0.28 0.28 0.28 0.28 86.76 10 86.76 10 86.275 10.7 86.275 10.7 86.76 10.92 86.76 10.92 86.275 11.62 86.275 11.62 86.76 11.84 86.76 11.84 86.275 12.54 86.275 12.54 86.76 12.76 86.76 12.76 86.275 13.46 86.275 13.46 86.76 14.14 86.76 14.14 86.275 14.84 86.275 14.84 86.76 15.06 86.76 15.06 86.275 15.76 86.275 15.76 86.76 21.5 86.76 21.5 86.275 22.2 86.275 22.2 86.76 24.72 86.76 24.72 86.275 25.42 86.275 25.42 86.76 25.64 86.76 25.64 86.275 26.34 86.275 26.34 86.76 26.56 86.76 26.56 86.275 27.26 86.275 27.26 86.76 27.48 86.76 27.48 86.275 28.18 86.275 28.18 86.76 28.4 86.76 28.4 86.275 29.1 86.275 29.1 86.76 30.24 86.76 30.24 86.275 30.94 86.275 30.94 86.76 31.16 86.76 31.16 86.275 31.86 86.275 31.86 86.76 32.08 86.76 32.08 86.275 32.78 86.275 32.78 86.76 33 86.76 33 86.275 33.7 86.275 33.7 86.76 33.92 86.76 33.92 86.275 34.62 86.275 34.62 86.76 34.84 86.76 34.84 86.275 35.54 86.275 35.54 86.76 35.76 86.76 35.76 86.275 36.46 86.275 36.46 86.76 36.68 86.76 36.68 86.275 37.38 86.275 37.38 86.76 37.6 86.76 37.6 86.275 38.3 86.275 38.3 86.76 38.52 86.76 38.52 86.275 39.22 86.275 39.22 86.76 39.9 86.76 39.9 86.275 40.6 86.275 40.6 86.76 40.82 86.76 40.82 86.275 41.52 86.275 41.52 86.76 41.74 86.76 41.74 86.275 42.44 86.275 42.44 86.76 42.66 86.76 42.66 86.275 43.36 86.275 43.36 86.76 43.58 86.76 43.58 86.275 44.28 86.275 44.28 86.76 44.5 86.76 44.5 86.275 45.2 86.275 45.2 86.76 45.42 86.76 45.42 86.275 46.12 86.275 46.12 86.76 46.34 86.76 46.34 86.275 47.04 86.275 47.04 86.76 47.26 86.76 47.26 86.275 47.96 86.275 47.96 86.76 48.18 86.76 48.18 86.275 48.88 86.275 48.88 86.76 49.56 86.76 49.56 86.275 50.26 86.275 50.26 86.76 50.48 86.76 50.48 86.275 51.18 86.275 51.18 86.76 51.4 86.76 51.4 86.275 52.1 86.275 52.1 86.76 52.32 86.76 52.32 86.275 53.02 86.275 53.02 86.76 53.24 86.76 53.24 86.275 53.94 86.275 53.94 86.76 54.16 86.76 54.16 86.275 54.86 86.275 54.86 86.76 55.08 86.76 55.08 86.275 55.78 86.275 55.78 86.76 56 86.76 56 86.275 56.7 86.275 56.7 86.76 56.92 86.76 56.92 86.275 57.62 86.275 57.62 86.76 57.84 86.76 57.84 86.275 58.54 86.275 58.54 86.76 59.68 86.76 59.68 86.275 60.38 86.275 60.38 86.76 60.6 86.76 60.6 86.275 61.3 86.275 61.3 86.76 61.52 86.76 61.52 86.275 62.22 86.275 62.22 86.76 62.44 86.76 62.44 86.275 63.14 86.275 63.14 86.76 63.36 86.76 63.36 86.275 64.06 86.275 64.06 86.76 64.28 86.76 64.28 86.275 64.98 86.275 64.98 86.76 65.2 86.76 65.2 86.275 65.9 86.275 65.9 86.76 66.12 86.76 66.12 86.275 66.82 86.275 66.82 86.76 67.04 86.76 67.04 86.275 67.74 86.275 67.74 86.76 67.96 86.76 67.96 86.275 68.66 86.275 68.66 86.76 68.88 86.76 68.88 86.275 69.58 86.275 69.58 86.76 69.8 86.76 69.8 86.275 70.5 86.275 70.5 86.76 70.72 86.76 70.72 86.275 71.42 86.275 71.42 86.76 ; + LAYER met4 ; + POLYGON 53.05 86.85 53.05 66.32 52.75 66.32 52.75 86.55 52.53 86.55 52.53 86.85 ; + POLYGON 5.21 27.01 5.21 0.505 5.225 0.505 5.225 0.175 4.895 0.175 4.895 0.505 4.91 0.505 4.91 27.01 ; + POLYGON 73.2 86.64 73.2 0.4 69.09 0.4 69.09 1.2 67.99 1.2 67.99 0.4 66.33 0.4 66.33 1.2 65.23 1.2 65.23 0.4 64.49 0.4 64.49 1.2 63.39 1.2 63.39 0.4 62.65 0.4 62.65 1.2 61.55 1.2 61.55 0.4 60.81 0.4 60.81 1.2 59.71 1.2 59.71 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 58.05 0.4 58.05 1.2 56.95 1.2 56.95 0.4 56.21 0.4 56.21 1.2 55.11 1.2 55.11 0.4 54.37 0.4 54.37 1.2 53.27 1.2 53.27 0.4 52.53 0.4 52.53 1.2 51.43 1.2 51.43 0.4 50.69 0.4 50.69 1.2 49.59 1.2 49.59 0.4 48.85 0.4 48.85 1.2 47.75 1.2 47.75 0.4 47.01 0.4 47.01 1.2 45.91 1.2 45.91 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 42.41 0.4 42.41 1.2 41.31 1.2 41.31 0.4 40.57 0.4 40.57 1.2 39.47 1.2 39.47 0.4 38.73 0.4 38.73 1.2 37.63 1.2 37.63 0.4 36.89 0.4 36.89 1.2 35.79 1.2 35.79 0.4 35.05 0.4 35.05 1.2 33.95 1.2 33.95 0.4 33.21 0.4 33.21 1.2 32.11 1.2 32.11 0.4 31.37 0.4 31.37 1.2 30.27 1.2 30.27 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 15.42 0.4 15.42 1 14.02 1 14.02 0.4 0.4 0.4 0.4 86.64 14.02 86.64 14.02 86.04 15.42 86.04 15.42 86.64 28.74 86.64 28.74 86.04 30.14 86.04 30.14 86.64 30.27 86.64 30.27 85.84 31.37 85.84 31.37 86.64 32.11 86.64 32.11 85.84 33.21 85.84 33.21 86.64 33.95 86.64 33.95 85.84 35.05 85.84 35.05 86.64 35.79 86.64 35.79 85.84 36.89 85.84 36.89 86.64 37.63 86.64 37.63 85.84 38.73 85.84 38.73 86.64 40.39 86.64 40.39 85.84 41.49 85.84 41.49 86.64 43.46 86.64 43.46 86.04 44.86 86.04 44.86 86.64 45.91 86.64 45.91 85.84 47.01 85.84 47.01 86.64 47.75 86.64 47.75 85.84 48.85 85.84 48.85 86.64 49.59 86.64 49.59 85.84 50.69 85.84 50.69 86.64 51.43 86.64 51.43 85.84 52.53 85.84 52.53 86.64 54.19 86.64 54.19 85.84 55.29 85.84 55.29 86.64 56.03 86.64 56.03 85.84 57.13 85.84 57.13 86.64 58.18 86.64 58.18 86.04 59.58 86.04 59.58 86.64 59.71 86.64 59.71 85.84 60.81 85.84 60.81 86.64 61.55 86.64 61.55 85.84 62.65 85.84 62.65 86.64 63.39 86.64 63.39 85.84 64.49 85.84 64.49 86.64 65.23 86.64 65.23 85.84 66.33 85.84 66.33 86.64 67.99 86.64 67.99 85.84 69.09 85.84 69.09 86.64 ; + LAYER met5 ; + RECT 4.8 82.72 68.8 85.92 ; + RECT 4.8 1.12 68.8 4.32 ; + POLYGON 68.8 85.44 68.8 81.12 72 81.12 72 67.12 68.8 67.12 68.8 60.72 72 60.72 72 46.72 68.8 46.72 68.8 40.32 72 40.32 72 26.32 68.8 26.32 68.8 19.92 72 19.92 72 5.92 68.8 5.92 68.8 1.6 4.8 1.6 4.8 5.92 1.6 5.92 1.6 19.92 4.8 19.92 4.8 26.32 1.6 26.32 1.6 40.32 4.8 40.32 4.8 46.72 1.6 46.72 1.6 60.72 4.8 60.72 4.8 67.12 1.6 67.12 1.6 81.12 4.8 81.12 4.8 85.44 ; + LAYER li1 ; + POLYGON 73.6 87.125 73.6 86.955 70.71 86.955 70.71 86.495 70.445 86.495 70.445 86.955 69.655 86.955 69.655 86.495 69.485 86.495 69.485 86.955 68.815 86.955 68.815 86.495 68.645 86.495 68.645 86.955 68.055 86.955 68.055 86.49 67.805 86.49 67.805 86.955 67.095 86.955 67.095 86.575 66.765 86.575 66.765 86.955 65.92 86.955 65.92 86.135 65.69 86.135 65.69 86.955 63.81 86.955 63.81 86.495 63.545 86.495 63.545 86.955 62.755 86.955 62.755 86.495 62.585 86.495 62.585 86.955 61.915 86.955 61.915 86.495 61.745 86.495 61.745 86.955 61.155 86.955 61.155 86.49 60.905 86.49 60.905 86.955 60.245 86.955 60.245 86.155 59.915 86.155 59.915 86.955 59.405 86.955 59.405 86.475 59.075 86.475 59.075 86.955 58.565 86.955 58.565 86.475 58.235 86.475 58.235 86.955 57.725 86.955 57.725 86.475 57.395 86.475 57.395 86.955 56.885 86.955 56.885 86.475 56.555 86.475 56.555 86.955 56.045 86.955 56.045 86.475 55.715 86.475 55.715 86.955 54.765 86.955 54.765 86.475 54.595 86.475 54.595 86.955 53.925 86.955 53.925 86.475 53.755 86.475 53.755 86.955 53.165 86.955 53.165 86.475 52.835 86.475 52.835 86.955 52.325 86.955 52.325 86.475 51.995 86.475 51.995 86.955 51.485 86.955 51.485 86.155 51.155 86.155 51.155 86.955 50.585 86.955 50.585 86.155 50.255 86.155 50.255 86.955 49.745 86.955 49.745 86.475 49.415 86.475 49.415 86.955 48.905 86.955 48.905 86.475 48.575 86.475 48.575 86.955 48.065 86.955 48.065 86.475 47.735 86.475 47.735 86.955 47.225 86.955 47.225 86.475 46.895 86.475 46.895 86.955 46.385 86.955 46.385 86.475 46.055 86.475 46.055 86.955 45.065 86.955 45.065 86.155 44.735 86.155 44.735 86.955 44.225 86.955 44.225 86.475 43.895 86.475 43.895 86.955 43.385 86.955 43.385 86.475 43.055 86.475 43.055 86.955 42.545 86.955 42.545 86.475 42.215 86.475 42.215 86.955 41.705 86.955 41.705 86.475 41.375 86.475 41.375 86.955 40.865 86.955 40.865 86.475 40.535 86.475 40.535 86.955 39.925 86.955 39.925 86.155 39.595 86.155 39.595 86.955 39.085 86.955 39.085 86.475 38.755 86.475 38.755 86.955 38.245 86.955 38.245 86.475 37.915 86.475 37.915 86.955 37.325 86.955 37.325 86.475 37.155 86.475 37.155 86.955 36.485 86.955 36.485 86.475 36.315 86.475 36.315 86.955 35.405 86.955 35.405 86.155 35.075 86.155 35.075 86.955 34.565 86.955 34.565 86.475 34.235 86.475 34.235 86.955 33.725 86.955 33.725 86.475 33.395 86.475 33.395 86.955 32.885 86.955 32.885 86.475 32.555 86.475 32.555 86.955 32.045 86.955 32.045 86.475 31.715 86.475 31.715 86.955 31.205 86.955 31.205 86.475 30.875 86.475 30.875 86.955 29.885 86.955 29.885 86.155 29.555 86.155 29.555 86.955 29.045 86.955 29.045 86.475 28.715 86.475 28.715 86.955 28.205 86.955 28.205 86.475 27.875 86.475 27.875 86.955 27.365 86.955 27.365 86.475 27.035 86.475 27.035 86.955 26.525 86.955 26.525 86.475 26.195 86.475 26.195 86.955 25.685 86.955 25.685 86.475 25.355 86.475 25.355 86.955 24.365 86.955 24.365 86.155 24.035 86.155 24.035 86.955 23.525 86.955 23.525 86.475 23.195 86.475 23.195 86.955 22.685 86.955 22.685 86.475 22.355 86.475 22.355 86.955 21.845 86.955 21.845 86.475 21.515 86.475 21.515 86.955 21.005 86.955 21.005 86.475 20.675 86.475 20.675 86.955 20.165 86.955 20.165 86.475 19.835 86.475 19.835 86.955 18.845 86.955 18.845 86.155 18.515 86.155 18.515 86.955 18.005 86.955 18.005 86.475 17.675 86.475 17.675 86.955 17.165 86.955 17.165 86.475 16.835 86.475 16.835 86.955 16.325 86.955 16.325 86.475 15.995 86.475 15.995 86.955 15.485 86.955 15.485 86.475 15.155 86.475 15.155 86.955 14.645 86.955 14.645 86.475 14.315 86.475 14.315 86.955 13.325 86.955 13.325 86.155 12.995 86.155 12.995 86.955 12.485 86.955 12.485 86.475 12.155 86.475 12.155 86.955 11.645 86.955 11.645 86.475 11.315 86.475 11.315 86.955 10.805 86.955 10.805 86.475 10.475 86.475 10.475 86.955 9.965 86.955 9.965 86.475 9.635 86.475 9.635 86.955 9.125 86.955 9.125 86.475 8.795 86.475 8.795 86.955 7.765 86.955 7.765 86.475 7.435 86.475 7.435 86.955 6.925 86.955 6.925 86.475 6.595 86.475 6.595 86.955 6.085 86.955 6.085 86.475 5.755 86.475 5.755 86.955 5.245 86.955 5.245 86.475 4.915 86.475 4.915 86.955 4.405 86.955 4.405 86.475 4.075 86.475 4.075 86.955 3.565 86.955 3.565 86.155 3.235 86.155 3.235 86.955 0 86.955 0 87.125 ; + RECT 72.68 84.235 73.6 84.405 ; + RECT 0 84.235 1.84 84.405 ; + RECT 72.68 81.515 73.6 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 72.68 78.795 73.6 78.965 ; + RECT 0 78.795 1.84 78.965 ; + RECT 72.68 76.075 73.6 76.245 ; + RECT 0 76.075 1.84 76.245 ; + RECT 72.68 73.355 73.6 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 72.68 70.635 73.6 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 69.92 67.915 73.6 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 69.92 65.195 73.6 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 72.68 62.475 73.6 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 72.68 59.755 73.6 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 69.92 57.035 73.6 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 69.92 54.315 73.6 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 72.68 51.595 73.6 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 72.68 48.875 73.6 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 72.68 46.155 73.6 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 72.68 43.435 73.6 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 72.68 40.715 73.6 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 72.68 37.995 73.6 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 69.92 35.275 73.6 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 69.92 32.555 73.6 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 72.68 29.835 73.6 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 72.68 27.115 73.6 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 72.68 24.395 73.6 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 72.68 21.675 73.6 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 72.68 18.955 73.6 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 72.68 16.235 73.6 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 72.68 13.515 73.6 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 73.14 10.795 73.6 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 72.68 8.075 73.6 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 72.68 5.355 73.6 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 69.92 2.635 73.6 2.805 ; + RECT 0 2.635 3.68 2.805 ; + POLYGON 58.305 0.905 58.305 0.085 59.495 0.085 59.495 0.565 59.665 0.565 59.665 0.085 60.335 0.085 60.335 0.565 60.505 0.565 60.505 0.085 61.175 0.085 61.175 0.565 61.345 0.565 61.345 0.085 62.015 0.085 62.015 0.565 62.185 0.565 62.185 0.085 62.855 0.085 62.855 0.565 63.025 0.565 63.025 0.085 63.695 0.085 63.695 0.565 63.865 0.565 63.865 0.085 64.535 0.085 64.535 0.565 64.705 0.565 64.705 0.085 65.375 0.085 65.375 0.565 65.545 0.565 65.545 0.085 66.215 0.085 66.215 0.565 66.385 0.565 66.385 0.085 67.055 0.085 67.055 0.565 67.225 0.565 67.225 0.085 67.895 0.085 67.895 0.565 68.065 0.565 68.065 0.085 68.735 0.085 68.735 0.565 68.905 0.565 68.905 0.085 69.575 0.085 69.575 0.565 69.745 0.565 69.745 0.085 73.6 0.085 73.6 -0.085 0 -0.085 0 0.085 4.115 0.085 4.115 0.565 4.285 0.565 4.285 0.085 4.955 0.085 4.955 0.565 5.125 0.565 5.125 0.085 5.715 0.085 5.715 0.565 6.045 0.565 6.045 0.085 6.555 0.085 6.555 0.565 6.885 0.565 6.885 0.085 7.395 0.085 7.395 0.885 7.725 0.885 7.725 0.085 8.795 0.085 8.795 0.565 9.125 0.565 9.125 0.085 9.635 0.085 9.635 0.565 9.965 0.565 9.965 0.085 10.475 0.085 10.475 0.565 10.805 0.565 10.805 0.085 11.315 0.085 11.315 0.565 11.645 0.565 11.645 0.085 12.155 0.085 12.155 0.565 12.485 0.565 12.485 0.085 12.995 0.085 12.995 0.885 13.325 0.885 13.325 0.085 15.235 0.085 15.235 0.565 15.565 0.565 15.565 0.085 16.075 0.085 16.075 0.565 16.405 0.565 16.405 0.085 16.915 0.085 16.915 0.565 17.245 0.565 17.245 0.085 17.755 0.085 17.755 0.565 18.085 0.565 18.085 0.085 18.595 0.085 18.595 0.565 18.925 0.565 18.925 0.085 19.435 0.085 19.435 0.885 19.765 0.885 19.765 0.085 21.215 0.085 21.215 0.565 21.545 0.565 21.545 0.085 22.055 0.085 22.055 0.565 22.385 0.565 22.385 0.085 22.895 0.085 22.895 0.565 23.225 0.565 23.225 0.085 23.735 0.085 23.735 0.565 24.065 0.565 24.065 0.085 24.575 0.085 24.575 0.565 24.905 0.565 24.905 0.085 25.415 0.085 25.415 0.885 25.745 0.885 25.745 0.085 27.615 0.085 27.615 0.885 27.945 0.885 27.945 0.085 28.455 0.085 28.455 0.565 28.785 0.565 28.785 0.085 29.295 0.085 29.295 0.565 29.625 0.565 29.625 0.085 30.135 0.085 30.135 0.565 30.465 0.565 30.465 0.085 30.975 0.085 30.975 0.565 31.305 0.565 31.305 0.085 31.815 0.085 31.815 0.565 32.145 0.565 32.145 0.085 33.595 0.085 33.595 0.885 33.925 0.885 33.925 0.085 34.435 0.085 34.435 0.565 34.765 0.565 34.765 0.085 35.275 0.085 35.275 0.565 35.605 0.565 35.605 0.085 36.115 0.085 36.115 0.565 36.445 0.565 36.445 0.085 36.955 0.085 36.955 0.565 37.285 0.565 37.285 0.085 37.795 0.085 37.795 0.565 38.125 0.565 38.125 0.085 40.115 0.085 40.115 0.885 40.445 0.885 40.445 0.085 40.955 0.085 40.955 0.565 41.285 0.565 41.285 0.085 41.795 0.085 41.795 0.565 42.125 0.565 42.125 0.085 42.715 0.085 42.715 0.565 42.885 0.565 42.885 0.085 43.555 0.085 43.555 0.565 43.725 0.565 43.725 0.085 45.145 0.085 45.145 0.465 45.475 0.465 45.475 0.085 46.515 0.085 46.515 0.565 46.845 0.565 46.845 0.085 47.355 0.085 47.355 0.565 47.685 0.565 47.685 0.085 48.195 0.085 48.195 0.565 48.525 0.565 48.525 0.085 49.035 0.085 49.035 0.565 49.365 0.565 49.365 0.085 49.875 0.085 49.875 0.565 50.205 0.565 50.205 0.085 50.715 0.085 50.715 0.885 51.045 0.885 51.045 0.085 52.035 0.085 52.035 0.565 52.365 0.565 52.365 0.085 52.875 0.085 52.875 0.565 53.205 0.565 53.205 0.085 53.715 0.085 53.715 0.565 54.045 0.565 54.045 0.085 54.555 0.085 54.555 0.565 54.885 0.565 54.885 0.085 55.395 0.085 55.395 0.565 55.725 0.565 55.725 0.085 56.235 0.085 56.235 0.885 56.565 0.885 56.565 0.085 58.135 0.085 58.135 0.905 ; + RECT 0.17 0.17 73.43 86.87 ; + LAYER met3 ; + POLYGON 59.045 87.085 59.045 87.08 59.26 87.08 59.26 86.76 59.045 86.76 59.045 86.755 58.715 86.755 58.715 86.76 58.5 86.76 58.5 87.08 58.715 87.08 58.715 87.085 ; + POLYGON 29.605 87.085 29.605 87.08 29.82 87.08 29.82 86.76 29.605 86.76 29.605 86.755 29.275 86.755 29.275 86.76 29.06 86.76 29.06 87.08 29.275 87.08 29.275 87.085 ; + POLYGON 57.65 2.53 57.65 0.5 57.69 0.5 57.69 0.18 57.31 0.18 57.31 0.5 57.35 0.5 57.35 2.53 ; + POLYGON 4.535 0.505 4.535 0.49 4.87 0.49 4.87 0.5 5.25 0.5 5.25 0.18 4.87 0.18 4.87 0.19 4.535 0.19 4.535 0.175 4.205 0.175 4.205 0.505 ; + POLYGON 59.045 0.285 59.045 0.28 59.26 0.28 59.26 -0.04 59.045 -0.04 59.045 -0.045 58.715 -0.045 58.715 -0.04 58.5 -0.04 58.5 0.28 58.715 0.28 58.715 0.285 ; + POLYGON 29.605 0.285 29.605 0.28 29.82 0.28 29.82 -0.04 29.605 -0.04 29.605 -0.045 29.275 -0.045 29.275 -0.04 29.06 -0.04 29.06 0.28 29.275 0.28 29.275 0.285 ; + RECT 0.4 0.4 73.2 86.64 ; + LAYER via ; + RECT 58.805 86.845 58.955 86.995 ; + RECT 29.365 86.845 29.515 86.995 ; + RECT 44.775 86.455 44.925 86.605 ; + RECT 41.095 86.455 41.245 86.605 ; + RECT 36.035 86.455 36.185 86.605 ; + RECT 32.355 86.455 32.505 86.605 ; + RECT 65.475 0.435 65.625 0.585 ; + RECT 58.805 0.045 58.955 0.195 ; + RECT 29.365 0.045 29.515 0.195 ; + LAYER via2 ; + RECT 58.78 86.82 58.98 87.02 ; + RECT 29.34 86.82 29.54 87.02 ; + RECT 4.27 0.24 4.47 0.44 ; + RECT 58.78 0.02 58.98 0.22 ; + RECT 29.34 0.02 29.54 0.22 ; + LAYER via3 ; + RECT 58.78 86.82 58.98 87.02 ; + RECT 29.34 86.82 29.54 87.02 ; + RECT 57.4 0.24 57.6 0.44 ; + RECT 4.96 0.24 5.16 0.44 ; + RECT 58.78 0.02 58.98 0.22 ; + RECT 29.34 0.02 29.54 0.22 ; + LAYER via4 ; + RECT 43.76 84.72 44.56 85.52 ; + RECT 14.32 84.72 15.12 85.52 ; + RECT 43.76 1.52 44.56 2.32 ; + RECT 14.32 1.52 15.12 2.32 ; + LAYER OVERLAP ; + POLYGON 0 0 0 87.04 73.6 87.04 73.6 0 ; + END +END cby_1__1_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/cby_2__1__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/cby_2__1__icv_in_design.lef new file mode 100644 index 0000000..f61e794 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/cby_2__1__icv_in_design.lef @@ -0,0 +1,1804 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO cby_2__1_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 73.6 BY 87.04 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.3 0.595 44.44 ; + END + END pReset[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.5 0 59.64 0.485 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.98 0 54.12 0.485 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.14 0 52.28 0.485 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.66 0 57.8 0.485 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 20.4 0 20.54 0.485 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.98 0 31.12 0.485 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.74 0 56.88 0.485 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.46 0 25.6 0.485 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.54 0 24.68 0.485 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.76 0 27.9 0.485 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.16 0 23.3 0.485 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.94 0 43.08 0.485 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.66 0 34.8 0.485 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.4 0 66.54 0.485 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.38 0 49.52 0.485 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.62 0 46.76 0.485 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.24 0 22.38 0.485 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.86 0 44 0.485 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 31.9 0 32.04 0.485 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 0 37.1 0.485 ; + END + END chany_bottom_in[19] + PIN chany_bottom_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.72 0 39.86 0.485 ; + END + END chany_bottom_in[20] + PIN chany_bottom_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.68 0 28.82 0.485 ; + END + END chany_bottom_in[21] + PIN chany_bottom_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.5 0 13.64 0.485 ; + END + END chany_bottom_in[22] + PIN chany_bottom_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.02 0 42.16 0.485 ; + END + END chany_bottom_in[23] + PIN chany_bottom_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.64 0 40.78 0.485 ; + END + END chany_bottom_in[24] + PIN chany_bottom_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.06 0 30.2 0.485 ; + END + END chany_bottom_in[25] + PIN chany_bottom_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.7 0 45.84 0.485 ; + END + END chany_bottom_in[26] + PIN chany_bottom_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.32 0 21.46 0.485 ; + END + END chany_bottom_in[27] + PIN chany_bottom_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.78 0 44.92 0.485 ; + END + END chany_bottom_in[28] + PIN chany_bottom_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.64 0 63.78 0.485 ; + END + END chany_bottom_in[29] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.6 86.555 6.74 87.04 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 5.68 86.555 5.82 87.04 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.76 86.555 4.9 87.04 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.74 86.555 10.88 87.04 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.32 86.555 21.46 87.04 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.82 86.555 9.96 87.04 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.98 86.555 54.12 87.04 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 20.4 86.555 20.54 87.04 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.9 86.555 55.04 87.04 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.42 86.555 37.56 87.04 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.46 86.555 48.6 87.04 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.62 86.555 46.76 87.04 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.48 86.555 19.62 87.04 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.3 86.555 50.44 87.04 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.14 86.555 52.28 87.04 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.86 86.555 44 87.04 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.24 86.555 22.38 87.04 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.7 86.555 45.84 87.04 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.16 86.555 23.3 87.04 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.06 86.555 53.2 87.04 ; + END + END chany_top_in[19] + PIN chany_top_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.58 86.555 35.72 87.04 ; + END + END chany_top_in[20] + PIN chany_top_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.5 86.555 59.64 87.04 ; + END + END chany_top_in[21] + PIN chany_top_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.5 86.555 36.64 87.04 ; + END + END chany_top_in[22] + PIN chany_top_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.2 86.555 34.34 87.04 ; + END + END chany_top_in[23] + PIN chany_top_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.28 86.555 33.42 87.04 ; + END + END chany_top_in[24] + PIN chany_top_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.64 86.555 17.78 87.04 ; + END + END chany_top_in[25] + PIN chany_top_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.38 86.555 49.52 87.04 ; + END + END chany_top_in[26] + PIN chany_top_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.08 86.555 24.22 87.04 ; + END + END chany_top_in[27] + PIN chany_top_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.78 86.555 44.92 87.04 ; + END + END chany_top_in[28] + PIN chany_top_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.1 86.555 64.24 87.04 ; + END + END chany_top_in[29] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 75.24 0.595 75.38 ; + END + END ccff_head[0] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 0 64.7 0.485 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 30.67 0 30.97 0.8 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.28 0 10.42 0.485 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.48 0 65.62 0.485 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.56 0 18.7 0.485 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 32.51 0 32.81 0.8 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.24 0 68.38 0.485 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.74 0 33.88 0.485 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.8 0 38.94 0.485 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.26 0 62.4 0.485 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.48 0 19.62 0.485 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.82 0 32.96 0.485 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.46 0 48.6 0.485 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.06 0 53.2 0.485 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.88 0 38.02 0.485 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.54 0 47.68 0.485 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.3 0 50.44 0.485 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.16 0 69.3 0.485 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.9 0 55.04 0.485 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.04 0 36.18 0.485 ; + END + END chany_bottom_out[19] + PIN chany_bottom_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.64 0 17.78 0.485 ; + END + END chany_bottom_out[20] + PIN chany_bottom_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 26.38 0 26.52 0.485 ; + END + END chany_bottom_out[21] + PIN chany_bottom_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.52 0 7.66 0.485 ; + END + END chany_bottom_out[22] + PIN chany_bottom_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.2 0 11.34 0.485 ; + END + END chany_bottom_out[23] + PIN chany_bottom_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.32 0 67.46 0.485 ; + END + END chany_bottom_out[24] + PIN chany_bottom_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.22 0 51.36 0.485 ; + END + END chany_bottom_out[25] + PIN chany_bottom_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71 0 71.14 0.485 ; + END + END chany_bottom_out[26] + PIN chany_bottom_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 41.71 0 42.01 0.8 ; + END + END chany_bottom_out[27] + PIN chany_bottom_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.34 0 61.48 0.485 ; + END + END chany_bottom_out[28] + PIN chany_bottom_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.08 0 70.22 0.485 ; + END + END chany_bottom_out[29] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 32.51 86.24 32.81 87.04 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 30.67 86.24 30.97 87.04 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 34.35 86.24 34.65 87.04 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.88 86.555 15.02 87.04 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.26 86.555 39.4 87.04 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.94 86.555 66.08 87.04 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.56 86.555 18.7 87.04 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.66 86.555 57.8 87.04 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.1 86.555 41.24 87.04 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.02 86.555 42.16 87.04 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.3 86.555 27.44 87.04 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.8 86.555 15.94 87.04 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.92 86.555 26.06 87.04 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.54 86.555 47.68 87.04 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.22 86.555 28.36 87.04 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.26 86.555 62.4 87.04 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.34 86.555 61.48 87.04 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.02 86.555 65.16 87.04 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.06 86.555 30.2 87.04 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.72 86.555 16.86 87.04 ; + END + END chany_top_out[19] + PIN chany_top_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.94 86.555 43.08 87.04 ; + END + END chany_top_out[20] + PIN chany_top_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.22 86.555 51.36 87.04 ; + END + END chany_top_out[21] + PIN chany_top_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.82 86.555 55.96 87.04 ; + END + END chany_top_out[22] + PIN chany_top_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.18 86.555 40.32 87.04 ; + END + END chany_top_out[23] + PIN chany_top_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.36 86.555 32.5 87.04 ; + END + END chany_top_out[24] + PIN chany_top_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.18 86.555 63.32 87.04 ; + END + END chany_top_out[25] + PIN chany_top_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.98 86.555 31.12 87.04 ; + END + END chany_top_out[26] + PIN chany_top_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25 86.555 25.14 87.04 ; + END + END chany_top_out[27] + PIN chany_top_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.42 86.555 60.56 87.04 ; + END + END chany_top_out[28] + PIN chany_top_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.74 86.555 56.88 87.04 ; + END + END chany_top_out[29] + PIN right_grid_pin_0_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 57.35 86.24 57.65 87.04 ; + END + END right_grid_pin_0_[0] + PIN left_grid_pin_16_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 22.54 0.595 22.68 ; + END + END left_grid_pin_16_[0] + PIN left_grid_pin_17_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 14.72 0.595 14.86 ; + END + END left_grid_pin_17_[0] + PIN left_grid_pin_18_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 15.4 0.595 15.54 ; + END + END left_grid_pin_18_[0] + PIN left_grid_pin_19_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 23.22 0.595 23.36 ; + END + END left_grid_pin_19_[0] + PIN left_grid_pin_20_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 6.22 0.595 6.36 ; + END + END left_grid_pin_20_[0] + PIN left_grid_pin_21_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 6.9 0.595 7.04 ; + END + END left_grid_pin_21_[0] + PIN left_grid_pin_22_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 1.8 0.595 1.94 ; + END + END left_grid_pin_22_[0] + PIN left_grid_pin_23_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 4.52 0.595 4.66 ; + END + END left_grid_pin_23_[0] + PIN left_grid_pin_24_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 18.12 0.595 18.26 ; + END + END left_grid_pin_24_[0] + PIN left_grid_pin_25_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 17.44 0.595 17.58 ; + END + END left_grid_pin_25_[0] + PIN left_grid_pin_26_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 20.5 0.595 20.64 ; + END + END left_grid_pin_26_[0] + PIN left_grid_pin_27_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 19.82 0.595 19.96 ; + END + END left_grid_pin_27_[0] + PIN left_grid_pin_28_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 60.96 0.595 61.1 ; + END + END left_grid_pin_28_[0] + PIN left_grid_pin_29_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 64.02 0.595 64.16 ; + END + END left_grid_pin_29_[0] + PIN left_grid_pin_30_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 61.64 0.595 61.78 ; + END + END left_grid_pin_30_[0] + PIN left_grid_pin_31_[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 63.34 0.595 63.48 ; + END + END left_grid_pin_31_[0] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.82 0 55.96 0.485 ; + END + END ccff_tail[0] + PIN IO_ISOL_N[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 8.94 0.595 9.08 ; + END + END IO_ISOL_N[0] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 82.72 73.6 82.86 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 83.4 73.6 83.54 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] + PIN gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 85.1 73.6 85.24 ; + END + END gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] + PIN left_width_0_height_0__pin_0_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 60.11 86.24 60.41 87.04 ; + END + END left_width_0_height_0__pin_0_[0] + PIN left_width_0_height_0__pin_1_upper[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.34 86.555 38.48 87.04 ; + END + END left_width_0_height_0__pin_1_upper[0] + PIN left_width_0_height_0__pin_1_lower[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.42 0 60.56 0.485 ; + END + END left_width_0_height_0__pin_1_lower[0] + PIN pReset_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.6 0 6.74 0.485 ; + END + END pReset_S_in + PIN prog_clk_0_W_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met1 ; + RECT 0 3.84 0.595 3.98 ; + END + END prog_clk_0_W_in + PIN prog_clk_0_S_out + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 2.46 0 2.6 0.485 ; + END + END prog_clk_0_S_out + PIN prog_clk_0_N_out + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 11.66 86.555 11.8 87.04 ; + END + END prog_clk_0_N_out + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 1.12 3.2 4.32 ; + RECT 70.4 1.12 73.6 4.32 ; + RECT 0 41.92 3.2 45.12 ; + RECT 70.4 41.92 73.6 45.12 ; + RECT 0 82.72 3.2 85.92 ; + RECT 70.4 82.72 73.6 85.92 ; + LAYER met4 ; + RECT 14.42 0 15.02 0.6 ; + RECT 43.86 0 44.46 0.6 ; + RECT 14.42 86.44 15.02 87.04 ; + RECT 43.86 86.44 44.46 87.04 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 73.12 2.48 73.6 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 73.12 7.92 73.6 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 73.12 13.36 73.6 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 73.12 18.8 73.6 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 73.12 24.24 73.6 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 73.12 29.68 73.6 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 73.12 35.12 73.6 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 73.12 40.56 73.6 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 73.12 46 73.6 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 73.12 51.44 73.6 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 73.12 56.88 73.6 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 73.12 62.32 73.6 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 73.12 67.76 73.6 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 73.12 73.2 73.6 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 73.12 78.64 73.6 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 73.12 84.08 73.6 84.56 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 21.52 3.2 24.72 ; + RECT 70.4 21.52 73.6 24.72 ; + RECT 0 62.32 3.2 65.52 ; + RECT 70.4 62.32 73.6 65.52 ; + LAYER met4 ; + RECT 29.14 0 29.74 0.6 ; + RECT 58.58 0 59.18 0.6 ; + RECT 29.14 86.44 29.74 87.04 ; + RECT 58.58 86.44 59.18 87.04 ; + LAYER met1 ; + RECT 0 -0.24 0.48 0.24 ; + RECT 73.12 -0.24 73.6 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 73.12 5.2 73.6 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 73.12 10.64 73.6 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 73.12 16.08 73.6 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 73.12 21.52 73.6 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 73.12 26.96 73.6 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 73.12 32.4 73.6 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 73.12 37.84 73.6 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 73.12 43.28 73.6 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 73.12 48.72 73.6 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 73.12 54.16 73.6 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 73.12 59.6 73.6 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 73.12 65.04 73.6 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 73.12 70.48 73.6 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 73.12 75.92 73.6 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 73.12 81.36 73.6 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 73.12 86.8 73.6 87.28 ; + END + END VSS + OBS + LAYER met1 ; + POLYGON 72.84 87.28 72.84 86.8 59.04 86.8 59.04 86.79 58.72 86.79 58.72 86.8 29.6 86.8 29.6 86.79 29.28 86.79 29.28 86.8 0.76 86.8 0.76 87.28 ; + POLYGON 59.04 0.25 59.04 0.24 72.84 0.24 72.84 -0.24 0.76 -0.24 0.76 0.24 29.28 0.24 29.28 0.25 29.6 0.25 29.6 0.24 58.72 0.24 58.72 0.25 ; + POLYGON 72.84 86.76 72.84 86.52 73.32 86.52 73.32 85.52 72.725 85.52 72.725 84.82 72.84 84.82 72.84 83.82 72.725 83.82 72.725 82.44 73.32 82.44 73.32 82.12 72.84 82.12 72.84 81.08 73.32 81.08 73.32 79.4 72.84 79.4 72.84 78.36 73.32 78.36 73.32 76.68 72.84 76.68 72.84 75.64 73.32 75.64 73.32 73.96 72.84 73.96 72.84 72.92 73.32 72.92 73.32 71.24 72.84 71.24 72.84 70.2 73.32 70.2 73.32 68.52 72.84 68.52 72.84 67.48 73.32 67.48 73.32 65.8 72.84 65.8 72.84 64.76 73.32 64.76 73.32 63.08 72.84 63.08 72.84 62.04 73.32 62.04 73.32 60.36 72.84 60.36 72.84 59.32 73.32 59.32 73.32 57.64 72.84 57.64 72.84 56.6 73.32 56.6 73.32 54.92 72.84 54.92 72.84 53.88 73.32 53.88 73.32 52.2 72.84 52.2 72.84 51.16 73.32 51.16 73.32 49.48 72.84 49.48 72.84 48.44 73.32 48.44 73.32 46.76 72.84 46.76 72.84 45.72 73.32 45.72 73.32 44.04 72.84 44.04 72.84 43 73.32 43 73.32 41.32 72.84 41.32 72.84 40.28 73.32 40.28 73.32 38.6 72.84 38.6 72.84 37.56 73.32 37.56 73.32 35.88 72.84 35.88 72.84 34.84 73.32 34.84 73.32 33.16 72.84 33.16 72.84 32.12 73.32 32.12 73.32 30.44 72.84 30.44 72.84 29.4 73.32 29.4 73.32 27.72 72.84 27.72 72.84 26.68 73.32 26.68 73.32 25 72.84 25 72.84 23.96 73.32 23.96 73.32 22.28 72.84 22.28 72.84 21.24 73.32 21.24 73.32 19.56 72.84 19.56 72.84 18.52 73.32 18.52 73.32 16.84 72.84 16.84 72.84 15.8 73.32 15.8 73.32 14.12 72.84 14.12 72.84 13.08 73.32 13.08 73.32 11.4 72.84 11.4 72.84 10.36 73.32 10.36 73.32 8.68 72.84 8.68 72.84 7.64 73.32 7.64 73.32 5.96 72.84 5.96 72.84 4.92 73.32 4.92 73.32 3.24 72.84 3.24 72.84 2.2 73.32 2.2 73.32 0.52 72.84 0.52 72.84 0.28 0.76 0.28 0.76 0.52 0.28 0.52 0.28 1.52 0.875 1.52 0.875 2.22 0.76 2.22 0.76 3.24 0.28 3.24 0.28 3.56 0.875 3.56 0.875 4.94 0.76 4.94 0.76 5.94 0.875 5.94 0.875 7.32 0.28 7.32 0.28 7.64 0.76 7.64 0.76 8.66 0.875 8.66 0.875 9.36 0.28 9.36 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 14.44 0.875 14.44 0.875 15.82 0.76 15.82 0.76 16.84 0.28 16.84 0.28 17.16 0.875 17.16 0.875 18.54 0.76 18.54 0.76 19.54 0.875 19.54 0.875 20.92 0.28 20.92 0.28 21.24 0.76 21.24 0.76 22.26 0.875 22.26 0.875 23.64 0.28 23.64 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.02 0.875 44.02 0.875 44.72 0.28 44.72 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 60.68 0.875 60.68 0.875 62.06 0.76 62.06 0.76 63.06 0.875 63.06 0.875 64.44 0.28 64.44 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 74.96 0.875 74.96 0.875 75.66 0.76 75.66 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 86.76 ; + LAYER met2 ; + RECT 58.74 86.735 59.02 87.105 ; + RECT 29.3 86.735 29.58 87.105 ; + POLYGON 31.58 86.94 31.58 82.04 31.44 82.04 31.44 86.8 31.4 86.8 31.4 86.94 ; + RECT 18.96 86.37 19.22 86.69 ; + RECT 57.14 86.03 57.4 86.35 ; + POLYGON 9.5 5.85 9.5 0.24 10 0.24 10 0.1 9.36 0.1 9.36 5.85 ; + RECT 30.46 0.69 30.72 1.01 ; + RECT 40.12 0.35 40.38 0.67 ; + RECT 26.78 0.35 27.04 0.67 ; + RECT 20.8 0.35 21.06 0.67 ; + RECT 17.12 0.35 17.38 0.67 ; + RECT 58.74 -0.065 59.02 0.305 ; + RECT 29.3 -0.065 29.58 0.305 ; + POLYGON 73.32 86.76 73.32 0.28 71.42 0.28 71.42 0.765 70.72 0.765 70.72 0.28 70.5 0.28 70.5 0.765 69.8 0.765 69.8 0.28 69.58 0.28 69.58 0.765 68.88 0.765 68.88 0.28 68.66 0.28 68.66 0.765 67.96 0.765 67.96 0.28 67.74 0.28 67.74 0.765 67.04 0.765 67.04 0.28 66.82 0.28 66.82 0.765 66.12 0.765 66.12 0.28 65.9 0.28 65.9 0.765 65.2 0.765 65.2 0.28 64.98 0.28 64.98 0.765 64.28 0.765 64.28 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 62.68 0.28 62.68 0.765 61.98 0.765 61.98 0.28 61.76 0.28 61.76 0.765 61.06 0.765 61.06 0.28 60.84 0.28 60.84 0.765 60.14 0.765 60.14 0.28 59.92 0.28 59.92 0.765 59.22 0.765 59.22 0.28 58.08 0.28 58.08 0.765 57.38 0.765 57.38 0.28 57.16 0.28 57.16 0.765 56.46 0.765 56.46 0.28 56.24 0.28 56.24 0.765 55.54 0.765 55.54 0.28 55.32 0.28 55.32 0.765 54.62 0.765 54.62 0.28 54.4 0.28 54.4 0.765 53.7 0.765 53.7 0.28 53.48 0.28 53.48 0.765 52.78 0.765 52.78 0.28 52.56 0.28 52.56 0.765 51.86 0.765 51.86 0.28 51.64 0.28 51.64 0.765 50.94 0.765 50.94 0.28 50.72 0.28 50.72 0.765 50.02 0.765 50.02 0.28 49.8 0.28 49.8 0.765 49.1 0.765 49.1 0.28 48.88 0.28 48.88 0.765 48.18 0.765 48.18 0.28 47.96 0.28 47.96 0.765 47.26 0.765 47.26 0.28 47.04 0.28 47.04 0.765 46.34 0.765 46.34 0.28 46.12 0.28 46.12 0.765 45.42 0.765 45.42 0.28 45.2 0.28 45.2 0.765 44.5 0.765 44.5 0.28 44.28 0.28 44.28 0.765 43.58 0.765 43.58 0.28 43.36 0.28 43.36 0.765 42.66 0.765 42.66 0.28 42.44 0.28 42.44 0.765 41.74 0.765 41.74 0.28 41.06 0.28 41.06 0.765 40.36 0.765 40.36 0.28 40.14 0.28 40.14 0.765 39.44 0.765 39.44 0.28 39.22 0.28 39.22 0.765 38.52 0.765 38.52 0.28 38.3 0.28 38.3 0.765 37.6 0.765 37.6 0.28 37.38 0.28 37.38 0.765 36.68 0.765 36.68 0.28 36.46 0.28 36.46 0.765 35.76 0.765 35.76 0.28 35.08 0.28 35.08 0.765 34.38 0.765 34.38 0.28 34.16 0.28 34.16 0.765 33.46 0.765 33.46 0.28 33.24 0.28 33.24 0.765 32.54 0.765 32.54 0.28 32.32 0.28 32.32 0.765 31.62 0.765 31.62 0.28 31.4 0.28 31.4 0.765 30.7 0.765 30.7 0.28 30.48 0.28 30.48 0.765 29.78 0.765 29.78 0.28 29.1 0.28 29.1 0.765 28.4 0.765 28.4 0.28 28.18 0.28 28.18 0.765 27.48 0.765 27.48 0.28 26.8 0.28 26.8 0.765 26.1 0.765 26.1 0.28 25.88 0.28 25.88 0.765 25.18 0.765 25.18 0.28 24.96 0.28 24.96 0.765 24.26 0.765 24.26 0.28 23.58 0.28 23.58 0.765 22.88 0.765 22.88 0.28 22.66 0.28 22.66 0.765 21.96 0.765 21.96 0.28 21.74 0.28 21.74 0.765 21.04 0.765 21.04 0.28 20.82 0.28 20.82 0.765 20.12 0.765 20.12 0.28 19.9 0.28 19.9 0.765 19.2 0.765 19.2 0.28 18.98 0.28 18.98 0.765 18.28 0.765 18.28 0.28 18.06 0.28 18.06 0.765 17.36 0.765 17.36 0.28 13.92 0.28 13.92 0.765 13.22 0.765 13.22 0.28 11.62 0.28 11.62 0.765 10.92 0.765 10.92 0.28 10.7 0.28 10.7 0.765 10 0.765 10 0.28 7.94 0.28 7.94 0.765 7.24 0.765 7.24 0.28 7.02 0.28 7.02 0.765 6.32 0.765 6.32 0.28 2.88 0.28 2.88 0.765 2.18 0.765 2.18 0.28 0.28 0.28 0.28 86.76 4.48 86.76 4.48 86.275 5.18 86.275 5.18 86.76 5.4 86.76 5.4 86.275 6.1 86.275 6.1 86.76 6.32 86.76 6.32 86.275 7.02 86.275 7.02 86.76 9.54 86.76 9.54 86.275 10.24 86.275 10.24 86.76 10.46 86.76 10.46 86.275 11.16 86.275 11.16 86.76 11.38 86.76 11.38 86.275 12.08 86.275 12.08 86.76 14.6 86.76 14.6 86.275 15.3 86.275 15.3 86.76 15.52 86.76 15.52 86.275 16.22 86.275 16.22 86.76 16.44 86.76 16.44 86.275 17.14 86.275 17.14 86.76 17.36 86.76 17.36 86.275 18.06 86.275 18.06 86.76 18.28 86.76 18.28 86.275 18.98 86.275 18.98 86.76 19.2 86.76 19.2 86.275 19.9 86.275 19.9 86.76 20.12 86.76 20.12 86.275 20.82 86.275 20.82 86.76 21.04 86.76 21.04 86.275 21.74 86.275 21.74 86.76 21.96 86.76 21.96 86.275 22.66 86.275 22.66 86.76 22.88 86.76 22.88 86.275 23.58 86.275 23.58 86.76 23.8 86.76 23.8 86.275 24.5 86.275 24.5 86.76 24.72 86.76 24.72 86.275 25.42 86.275 25.42 86.76 25.64 86.76 25.64 86.275 26.34 86.275 26.34 86.76 27.02 86.76 27.02 86.275 27.72 86.275 27.72 86.76 27.94 86.76 27.94 86.275 28.64 86.275 28.64 86.76 29.78 86.76 29.78 86.275 30.48 86.275 30.48 86.76 30.7 86.76 30.7 86.275 31.4 86.275 31.4 86.76 32.08 86.76 32.08 86.275 32.78 86.275 32.78 86.76 33 86.76 33 86.275 33.7 86.275 33.7 86.76 33.92 86.76 33.92 86.275 34.62 86.275 34.62 86.76 35.3 86.76 35.3 86.275 36 86.275 36 86.76 36.22 86.76 36.22 86.275 36.92 86.275 36.92 86.76 37.14 86.76 37.14 86.275 37.84 86.275 37.84 86.76 38.06 86.76 38.06 86.275 38.76 86.275 38.76 86.76 38.98 86.76 38.98 86.275 39.68 86.275 39.68 86.76 39.9 86.76 39.9 86.275 40.6 86.275 40.6 86.76 40.82 86.76 40.82 86.275 41.52 86.275 41.52 86.76 41.74 86.76 41.74 86.275 42.44 86.275 42.44 86.76 42.66 86.76 42.66 86.275 43.36 86.275 43.36 86.76 43.58 86.76 43.58 86.275 44.28 86.275 44.28 86.76 44.5 86.76 44.5 86.275 45.2 86.275 45.2 86.76 45.42 86.76 45.42 86.275 46.12 86.275 46.12 86.76 46.34 86.76 46.34 86.275 47.04 86.275 47.04 86.76 47.26 86.76 47.26 86.275 47.96 86.275 47.96 86.76 48.18 86.76 48.18 86.275 48.88 86.275 48.88 86.76 49.1 86.76 49.1 86.275 49.8 86.275 49.8 86.76 50.02 86.76 50.02 86.275 50.72 86.275 50.72 86.76 50.94 86.76 50.94 86.275 51.64 86.275 51.64 86.76 51.86 86.76 51.86 86.275 52.56 86.275 52.56 86.76 52.78 86.76 52.78 86.275 53.48 86.275 53.48 86.76 53.7 86.76 53.7 86.275 54.4 86.275 54.4 86.76 54.62 86.76 54.62 86.275 55.32 86.275 55.32 86.76 55.54 86.76 55.54 86.275 56.24 86.275 56.24 86.76 56.46 86.76 56.46 86.275 57.16 86.275 57.16 86.76 57.38 86.76 57.38 86.275 58.08 86.275 58.08 86.76 59.22 86.76 59.22 86.275 59.92 86.275 59.92 86.76 60.14 86.76 60.14 86.275 60.84 86.275 60.84 86.76 61.06 86.76 61.06 86.275 61.76 86.275 61.76 86.76 61.98 86.76 61.98 86.275 62.68 86.275 62.68 86.76 62.9 86.76 62.9 86.275 63.6 86.275 63.6 86.76 63.82 86.76 63.82 86.275 64.52 86.275 64.52 86.76 64.74 86.76 64.74 86.275 65.44 86.275 65.44 86.76 65.66 86.76 65.66 86.275 66.36 86.275 66.36 86.76 ; + LAYER met4 ; + POLYGON 26.385 86.865 26.385 86.535 26.37 86.535 26.37 41.67 26.07 41.67 26.07 86.535 26.055 86.535 26.055 86.865 ; + POLYGON 73.2 86.64 73.2 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 42.41 0.4 42.41 1.2 41.31 1.2 41.31 0.4 33.21 0.4 33.21 1.2 32.11 1.2 32.11 0.4 31.37 0.4 31.37 1.2 30.27 1.2 30.27 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 15.42 0.4 15.42 1 14.02 1 14.02 0.4 0.4 0.4 0.4 86.64 14.02 86.64 14.02 86.04 15.42 86.04 15.42 86.64 28.74 86.64 28.74 86.04 30.14 86.04 30.14 86.64 30.27 86.64 30.27 85.84 31.37 85.84 31.37 86.64 32.11 86.64 32.11 85.84 33.21 85.84 33.21 86.64 33.95 86.64 33.95 85.84 35.05 85.84 35.05 86.64 43.46 86.64 43.46 86.04 44.86 86.04 44.86 86.64 56.95 86.64 56.95 85.84 58.05 85.84 58.05 86.64 58.18 86.64 58.18 86.04 59.58 86.04 59.58 86.64 59.71 86.64 59.71 85.84 60.81 85.84 60.81 86.64 ; + LAYER met5 ; + RECT 4.8 82.72 68.8 85.92 ; + RECT 4.8 1.12 68.8 4.32 ; + POLYGON 68.8 85.44 68.8 81.12 72 81.12 72 67.12 68.8 67.12 68.8 60.72 72 60.72 72 46.72 68.8 46.72 68.8 40.32 72 40.32 72 26.32 68.8 26.32 68.8 19.92 72 19.92 72 5.92 68.8 5.92 68.8 1.6 4.8 1.6 4.8 5.92 1.6 5.92 1.6 19.92 4.8 19.92 4.8 26.32 1.6 26.32 1.6 40.32 4.8 40.32 4.8 46.72 1.6 46.72 1.6 60.72 4.8 60.72 4.8 67.12 1.6 67.12 1.6 81.12 4.8 81.12 4.8 85.44 ; + LAYER li1 ; + POLYGON 73.6 87.125 73.6 86.955 67.535 86.955 67.535 86.23 67.245 86.23 67.245 86.955 64.695 86.955 64.695 86.555 64.365 86.555 64.365 86.955 63.855 86.955 63.855 86.555 63.525 86.555 63.525 86.955 62.11 86.955 62.11 86.445 61.695 86.445 61.695 86.955 57.485 86.955 57.485 86.155 57.155 86.155 57.155 86.955 56.645 86.955 56.645 86.475 56.315 86.475 56.315 86.955 55.805 86.955 55.805 86.475 55.475 86.475 55.475 86.955 54.965 86.955 54.965 86.475 54.635 86.475 54.635 86.955 54.125 86.955 54.125 86.475 53.795 86.475 53.795 86.955 53.285 86.955 53.285 86.475 52.955 86.475 52.955 86.955 52.355 86.955 52.355 86.23 52.065 86.23 52.065 86.955 49.205 86.955 49.205 86.155 48.875 86.155 48.875 86.955 48.365 86.955 48.365 86.475 48.035 86.475 48.035 86.955 47.525 86.955 47.525 86.475 47.195 86.475 47.195 86.955 46.685 86.955 46.685 86.475 46.355 86.475 46.355 86.955 45.845 86.955 45.845 86.475 45.515 86.475 45.515 86.955 45.005 86.955 45.005 86.475 44.675 86.475 44.675 86.955 43.645 86.955 43.645 86.475 43.315 86.475 43.315 86.955 42.805 86.955 42.805 86.475 42.475 86.475 42.475 86.955 41.965 86.955 41.965 86.475 41.635 86.475 41.635 86.955 41.125 86.955 41.125 86.475 40.795 86.475 40.795 86.955 40.285 86.955 40.285 86.475 39.955 86.475 39.955 86.955 39.445 86.955 39.445 86.155 39.115 86.155 39.115 86.955 37.635 86.955 37.635 86.23 37.345 86.23 37.345 86.955 36.785 86.955 36.785 86.155 36.455 86.155 36.455 86.955 35.945 86.955 35.945 86.475 35.615 86.475 35.615 86.955 35.105 86.955 35.105 86.475 34.775 86.475 34.775 86.955 34.265 86.955 34.265 86.475 33.935 86.475 33.935 86.955 33.425 86.955 33.425 86.475 33.095 86.475 33.095 86.955 32.585 86.955 32.585 86.475 32.255 86.475 32.255 86.955 31.1 86.955 31.1 86.495 30.775 86.495 30.775 86.955 28.985 86.955 28.985 86.495 28.715 86.495 28.715 86.955 27.545 86.955 27.545 86.475 27.215 86.475 27.215 86.955 26.705 86.955 26.705 86.475 26.375 86.475 26.375 86.955 25.865 86.955 25.865 86.475 25.535 86.475 25.535 86.955 25.025 86.955 25.025 86.475 24.695 86.475 24.695 86.955 24.185 86.955 24.185 86.475 23.855 86.475 23.855 86.955 23.345 86.955 23.345 86.155 23.015 86.155 23.015 86.955 22.455 86.955 22.455 86.23 22.165 86.23 22.165 86.955 21.605 86.955 21.605 86.155 21.275 86.155 21.275 86.955 20.765 86.955 20.765 86.475 20.435 86.475 20.435 86.955 19.925 86.955 19.925 86.475 19.595 86.475 19.595 86.955 19.085 86.955 19.085 86.475 18.755 86.475 18.755 86.955 18.245 86.955 18.245 86.475 17.915 86.475 17.915 86.955 17.405 86.955 17.405 86.475 17.075 86.475 17.075 86.955 12.865 86.955 12.865 86.155 12.535 86.155 12.535 86.955 12.025 86.955 12.025 86.475 11.695 86.475 11.695 86.955 11.185 86.955 11.185 86.475 10.855 86.475 10.855 86.955 10.345 86.955 10.345 86.475 10.015 86.475 10.015 86.955 9.505 86.955 9.505 86.475 9.175 86.475 9.175 86.955 8.665 86.955 8.665 86.475 8.335 86.475 8.335 86.955 7.735 86.955 7.735 86.23 7.445 86.23 7.445 86.955 6.535 86.955 6.535 86.42 6.025 86.42 6.025 86.955 4.065 86.955 4.065 86.555 3.735 86.555 3.735 86.955 0 86.955 0 87.125 ; + RECT 69.92 84.235 73.6 84.405 ; + RECT 0 84.235 1.84 84.405 ; + RECT 69.92 81.515 73.6 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 72.68 78.795 73.6 78.965 ; + RECT 0 78.795 1.84 78.965 ; + RECT 72.68 76.075 73.6 76.245 ; + RECT 0 76.075 1.84 76.245 ; + RECT 69.92 73.355 73.6 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 69.92 70.635 73.6 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 72.68 67.915 73.6 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 72.68 65.195 73.6 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 72.68 62.475 73.6 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 72.68 59.755 73.6 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 72.68 57.035 73.6 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 72.68 54.315 73.6 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 72.68 51.595 73.6 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 72.68 48.875 73.6 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 72.68 46.155 73.6 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 72.68 43.435 73.6 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 72.68 40.715 73.6 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 72.68 37.995 73.6 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 72.68 35.275 73.6 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 72.68 32.555 73.6 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 72.68 29.835 73.6 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 72.68 27.115 73.6 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 72.68 24.395 73.6 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 72.68 21.675 73.6 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 72.68 18.955 73.6 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 72.68 16.235 73.6 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 72.68 13.515 73.6 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 72.68 10.795 73.6 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 72.68 8.075 73.6 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 72.68 5.355 73.6 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 72.68 2.635 73.6 2.805 ; + RECT 0 2.635 3.68 2.805 ; + POLYGON 63.925 0.885 63.925 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 73.6 0.085 73.6 -0.085 0 -0.085 0 0.085 3.735 0.085 3.735 0.485 4.065 0.485 4.065 0.085 6.025 0.085 6.025 0.62 6.535 0.62 6.535 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 8.255 0.085 8.255 0.565 8.425 0.565 8.425 0.085 9.095 0.085 9.095 0.565 9.265 0.565 9.265 0.085 9.855 0.085 9.855 0.565 10.185 0.565 10.185 0.085 10.695 0.085 10.695 0.565 11.025 0.565 11.025 0.085 11.535 0.085 11.535 0.885 11.865 0.885 11.865 0.085 13.435 0.085 13.435 0.885 13.765 0.885 13.765 0.085 14.275 0.085 14.275 0.565 14.605 0.565 14.605 0.085 15.115 0.085 15.115 0.565 15.445 0.565 15.445 0.085 16.035 0.085 16.035 0.565 16.205 0.565 16.205 0.085 16.875 0.085 16.875 0.565 17.045 0.565 17.045 0.085 18.455 0.085 18.455 0.485 18.785 0.485 18.785 0.085 20.745 0.085 20.745 0.62 21.255 0.62 21.255 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 23.015 0.085 23.015 0.885 23.345 0.885 23.345 0.085 23.855 0.085 23.855 0.565 24.185 0.565 24.185 0.085 24.695 0.085 24.695 0.565 25.025 0.565 25.025 0.085 25.535 0.085 25.535 0.565 25.865 0.565 25.865 0.085 26.375 0.085 26.375 0.565 26.705 0.565 26.705 0.085 27.215 0.085 27.215 0.565 27.545 0.565 27.545 0.085 29.495 0.085 29.495 0.565 29.825 0.565 29.825 0.085 30.335 0.085 30.335 0.565 30.665 0.565 30.665 0.085 31.175 0.085 31.175 0.565 31.505 0.565 31.505 0.085 32.015 0.085 32.015 0.565 32.345 0.565 32.345 0.085 32.855 0.085 32.855 0.565 33.185 0.565 33.185 0.085 33.695 0.085 33.695 0.885 34.025 0.885 34.025 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 40.535 0.085 40.535 0.565 40.865 0.565 40.865 0.085 41.375 0.085 41.375 0.565 41.705 0.565 41.705 0.085 42.215 0.085 42.215 0.565 42.545 0.565 42.545 0.085 43.055 0.085 43.055 0.565 43.385 0.565 43.385 0.085 43.895 0.085 43.895 0.565 44.225 0.565 44.225 0.085 44.735 0.085 44.735 0.885 45.065 0.885 45.065 0.085 46.975 0.085 46.975 0.565 47.305 0.565 47.305 0.085 47.815 0.085 47.815 0.565 48.145 0.565 48.145 0.085 48.655 0.085 48.655 0.565 48.985 0.565 48.985 0.085 49.495 0.085 49.495 0.565 49.825 0.565 49.825 0.085 50.335 0.085 50.335 0.565 50.665 0.565 50.665 0.085 51.175 0.085 51.175 0.885 51.505 0.885 51.505 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 52.955 0.085 52.955 0.565 53.285 0.565 53.285 0.085 53.795 0.085 53.795 0.565 54.125 0.565 54.125 0.085 54.635 0.085 54.635 0.565 54.965 0.565 54.965 0.085 55.475 0.085 55.475 0.565 55.805 0.565 55.805 0.085 56.315 0.085 56.315 0.565 56.645 0.565 56.645 0.085 57.155 0.085 57.155 0.885 57.485 0.885 57.485 0.085 59.395 0.085 59.395 0.565 59.725 0.565 59.725 0.085 60.235 0.085 60.235 0.565 60.565 0.565 60.565 0.085 61.075 0.085 61.075 0.565 61.405 0.565 61.405 0.085 61.915 0.085 61.915 0.565 62.245 0.565 62.245 0.085 62.755 0.085 62.755 0.565 63.085 0.565 63.085 0.085 63.595 0.085 63.595 0.885 ; + RECT 0.17 0.17 73.43 86.87 ; + LAYER met3 ; + POLYGON 59.045 87.085 59.045 87.08 59.26 87.08 59.26 86.76 59.045 86.76 59.045 86.755 58.715 86.755 58.715 86.76 58.5 86.76 58.5 87.08 58.715 87.08 58.715 87.085 ; + POLYGON 29.605 87.085 29.605 87.08 29.82 87.08 29.82 86.76 29.605 86.76 29.605 86.755 29.275 86.755 29.275 86.76 29.06 86.76 29.06 87.08 29.275 87.08 29.275 87.085 ; + POLYGON 16.035 86.865 16.035 86.85 26.03 86.85 26.03 86.86 26.41 86.86 26.41 86.54 26.03 86.54 26.03 86.55 16.035 86.55 16.035 86.535 15.705 86.535 15.705 86.865 ; + POLYGON 59.045 0.285 59.045 0.28 59.26 0.28 59.26 -0.04 59.045 -0.04 59.045 -0.045 58.715 -0.045 58.715 -0.04 58.5 -0.04 58.5 0.28 58.715 0.28 58.715 0.285 ; + POLYGON 29.605 0.285 29.605 0.28 29.82 0.28 29.82 -0.04 29.605 -0.04 29.605 -0.045 29.275 -0.045 29.275 -0.04 29.06 -0.04 29.06 0.28 29.275 0.28 29.275 0.285 ; + RECT 0.4 0.4 73.2 86.64 ; + LAYER via ; + RECT 58.805 86.845 58.955 86.995 ; + RECT 29.365 86.845 29.515 86.995 ; + RECT 48.455 86.455 48.605 86.605 ; + RECT 33.275 86.455 33.425 86.605 ; + RECT 14.875 86.455 15.025 86.605 ; + RECT 37.875 0.435 38.025 0.585 ; + RECT 22.235 0.435 22.385 0.585 ; + RECT 58.805 0.045 58.955 0.195 ; + RECT 29.365 0.045 29.515 0.195 ; + LAYER via2 ; + RECT 58.78 86.82 58.98 87.02 ; + RECT 29.34 86.82 29.54 87.02 ; + RECT 15.77 86.6 15.97 86.8 ; + RECT 58.78 0.02 58.98 0.22 ; + RECT 29.34 0.02 29.54 0.22 ; + LAYER via3 ; + RECT 58.78 86.82 58.98 87.02 ; + RECT 29.34 86.82 29.54 87.02 ; + RECT 26.12 86.6 26.32 86.8 ; + RECT 60.16 85.92 60.36 86.12 ; + RECT 58.78 0.02 58.98 0.22 ; + RECT 29.34 0.02 29.54 0.22 ; + LAYER via4 ; + RECT 43.76 84.72 44.56 85.52 ; + RECT 14.32 84.72 15.12 85.52 ; + RECT 43.76 1.52 44.56 2.32 ; + RECT 14.32 1.52 15.12 2.32 ; + LAYER OVERLAP ; + POLYGON 0 0 0 87.04 73.6 87.04 73.6 0 ; + END +END cby_2__1_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_0__0__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_0__0__icv_in_design.lef new file mode 100644 index 0000000..5ee28a1 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_0__0__icv_in_design.lef @@ -0,0 +1,1670 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_0__0_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 103.96 BY 87.04 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.68 86.555 51.82 87.04 ; + END + END pReset[0] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.16 86.555 69.3 87.04 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.36 86.555 55.5 87.04 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.2 86.555 57.34 87.04 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.68 86.555 28.82 87.04 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.48 86.555 65.62 87.04 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 86.555 64.7 87.04 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.44 86.555 8.58 87.04 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.12 86.555 12.26 87.04 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.16 86.555 23.3 87.04 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.24 86.555 22.38 87.04 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.08 86.555 24.22 87.04 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 31.44 86.555 31.58 87.04 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.52 86.555 30.66 87.04 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.4 86.555 66.54 87.04 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.28 86.555 56.42 87.04 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.88 86.555 61.02 87.04 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.2 86.555 34.34 87.04 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.24 86.555 45.38 87.04 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.52 86.555 7.66 87.04 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.36 86.555 32.5 87.04 ; + END + END chany_top_in[19] + PIN chany_top_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.96 86.555 60.1 87.04 ; + END + END chany_top_in[20] + PIN chany_top_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.64 86.555 63.78 87.04 ; + END + END chany_top_in[21] + PIN chany_top_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.36 86.555 9.5 87.04 ; + END + END chany_top_in[22] + PIN chany_top_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.92 86.555 26.06 87.04 ; + END + END chany_top_in[23] + PIN chany_top_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.76 86.555 27.9 87.04 ; + END + END chany_top_in[24] + PIN chany_top_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.6 86.555 6.74 87.04 ; + END + END chany_top_in[25] + PIN chany_top_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48 86.555 48.14 87.04 ; + END + END chany_top_in[26] + PIN chany_top_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.24 86.555 68.38 87.04 ; + END + END chany_top_in[27] + PIN chany_top_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.32 86.555 67.46 87.04 ; + END + END chany_top_in[28] + PIN chany_top_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 86.555 58.26 87.04 ; + END + END chany_top_in[29] + PIN top_left_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.44 86.555 54.58 87.04 ; + END + END top_left_grid_pin_1_[0] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 23.56 103.96 23.7 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 21.27 103.96 21.57 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 31.04 103.96 31.18 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 36.48 103.96 36.62 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 22.63 103.96 22.93 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 25.6 103.96 25.74 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 17.1 103.96 17.24 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 29 103.96 29.14 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 38.95 103.96 39.25 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 71.5 103.96 71.64 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 66.4 103.96 66.54 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 37.16 103.96 37.3 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 12.68 103.96 12.82 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 57.9 103.96 58.04 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 34.44 103.96 34.58 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 31.72 103.96 31.86 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 33.76 103.96 33.9 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 22.88 103.96 23.02 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 20.16 103.96 20.3 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 27.98 103.96 28.12 ; + END + END chanx_right_in[19] + PIN chanx_right_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 63.34 103.96 63.48 ; + END + END chanx_right_in[20] + PIN chanx_right_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 47.11 103.96 47.41 ; + END + END chanx_right_in[21] + PIN chanx_right_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 54.59 103.96 54.89 ; + END + END chanx_right_in[22] + PIN chanx_right_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 15.4 103.96 15.54 ; + END + END chanx_right_in[23] + PIN chanx_right_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 20.84 103.96 20.98 ; + END + END chanx_right_in[24] + PIN chanx_right_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 72.18 103.96 72.32 ; + END + END chanx_right_in[25] + PIN chanx_right_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 61.3 103.96 61.44 ; + END + END chanx_right_in[26] + PIN chanx_right_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 26.28 103.96 26.42 ; + END + END chanx_right_in[27] + PIN chanx_right_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 44.3 103.96 44.44 ; + END + END chanx_right_in[28] + PIN chanx_right_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 67.08 103.96 67.22 ; + END + END chanx_right_in[29] + PIN right_bottom_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 3.84 103.96 3.98 ; + END + END right_bottom_grid_pin_1_[0] + PIN right_bottom_grid_pin_3_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 9.28 103.96 9.42 ; + END + END right_bottom_grid_pin_3_[0] + PIN right_bottom_grid_pin_5_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 5.63 103.96 5.93 ; + END + END right_bottom_grid_pin_5_[0] + PIN right_bottom_grid_pin_7_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 6.56 103.96 6.7 ; + END + END right_bottom_grid_pin_7_[0] + PIN right_bottom_grid_pin_9_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 6.99 103.96 7.29 ; + END + END right_bottom_grid_pin_9_[0] + PIN right_bottom_grid_pin_11_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 7.24 103.96 7.38 ; + END + END right_bottom_grid_pin_11_[0] + PIN right_bottom_grid_pin_13_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 1.8 103.96 1.94 ; + END + END right_bottom_grid_pin_13_[0] + PIN right_bottom_grid_pin_15_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 14.72 103.96 14.86 ; + END + END right_bottom_grid_pin_15_[0] + PIN right_bottom_grid_pin_17_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 4.52 103.96 4.66 ; + END + END right_bottom_grid_pin_17_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 11.66 103.96 11.8 ; + END + END ccff_head[0] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 26.84 86.555 26.98 87.04 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.72 86.555 62.86 87.04 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 86.555 14.1 87.04 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.28 86.555 10.42 87.04 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.32 86.555 44.46 87.04 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.32 86.555 21.46 87.04 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.04 86.555 13.18 87.04 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.12 86.555 35.26 87.04 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.8 86.555 61.94 87.04 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.88 86.555 15.02 87.04 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.4 86.555 43.54 87.04 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 20.4 86.555 20.54 87.04 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25 86.555 25.14 87.04 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.8 86.555 15.94 87.04 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.16 86.555 46.3 87.04 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.04 86.555 36.18 87.04 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.48 86.555 42.62 87.04 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.48 86.555 19.62 87.04 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.28 86.555 33.42 87.04 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 86.555 37.1 87.04 ; + END + END chany_top_out[19] + PIN chany_top_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.56 86.555 41.7 87.04 ; + END + END chany_top_out[20] + PIN chany_top_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.72 86.555 16.86 87.04 ; + END + END chany_top_out[21] + PIN chany_top_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.2 86.555 11.34 87.04 ; + END + END chany_top_out[22] + PIN chany_top_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.88 86.555 38.02 87.04 ; + END + END chany_top_out[23] + PIN chany_top_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.08 86.555 47.22 87.04 ; + END + END chany_top_out[24] + PIN chany_top_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.64 86.555 40.78 87.04 ; + END + END chany_top_out[25] + PIN chany_top_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.8 86.555 38.94 87.04 ; + END + END chany_top_out[26] + PIN chany_top_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.56 86.555 18.7 87.04 ; + END + END chany_top_out[27] + PIN chany_top_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.64 86.555 17.78 87.04 ; + END + END chany_top_out[28] + PIN chany_top_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.72 86.555 39.86 87.04 ; + END + END chany_top_out[29] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 23.99 103.96 24.29 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 48.04 103.96 48.18 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 53.48 103.96 53.62 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 43.03 103.96 43.33 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 39.88 103.96 40.02 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 44.39 103.96 44.69 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 41.67 103.96 41.97 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 42.26 103.96 42.4 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 48.47 103.96 48.77 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 50.08 103.96 50.22 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 66.15 103.96 66.45 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 37.59 103.96 37.89 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 74.22 103.96 74.36 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 41.58 103.96 41.72 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 60.62 103.96 60.76 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 52.46 103.96 52.6 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 69.46 103.96 69.6 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 64.36 103.96 64.5 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 49.83 103.96 50.13 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 44.98 103.96 45.12 ; + END + END chanx_right_out[19] + PIN chanx_right_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 55.18 103.96 55.32 ; + END + END chanx_right_out[20] + PIN chanx_right_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 68.78 103.96 68.92 ; + END + END chanx_right_out[21] + PIN chanx_right_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 67.51 103.96 67.81 ; + END + END chanx_right_out[22] + PIN chanx_right_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 50.76 103.96 50.9 ; + END + END chanx_right_out[23] + PIN chanx_right_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 52.55 103.96 52.85 ; + END + END chanx_right_out[24] + PIN chanx_right_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 38.86 103.96 39 ; + END + END chanx_right_out[25] + PIN chanx_right_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 45.75 103.96 46.05 ; + END + END chanx_right_out[26] + PIN chanx_right_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 47.02 103.96 47.16 ; + END + END chanx_right_out[27] + PIN chanx_right_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 40.31 103.96 40.61 ; + END + END chanx_right_out[28] + PIN chanx_right_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 58.92 103.96 59.06 ; + END + END chanx_right_out[29] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 69.46 0.595 69.6 ; + END + END ccff_tail[0] + PIN pReset_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 9.96 103.96 10.1 ; + END + END pReset_E_in + PIN prog_clk_0_E_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met1 ; + RECT 103.365 56.2 103.96 56.34 ; + END + END prog_clk_0_E_in + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 16.08 3.2 19.28 ; + RECT 100.76 16.08 103.96 19.28 ; + RECT 0 56.88 3.2 60.08 ; + RECT 100.76 56.88 103.96 60.08 ; + LAYER met4 ; + RECT 14.42 0 15.02 0.6 ; + RECT 43.86 0 44.46 0.6 ; + RECT 89.86 0 90.46 0.6 ; + RECT 89.86 75.56 90.46 76.16 ; + RECT 14.42 86.44 15.02 87.04 ; + RECT 43.86 86.44 44.46 87.04 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 103.48 2.48 103.96 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 103.48 7.92 103.96 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 103.48 13.36 103.96 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 103.48 18.8 103.96 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 103.48 24.24 103.96 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 103.48 29.68 103.96 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 103.48 35.12 103.96 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 103.48 40.56 103.96 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 103.48 46 103.96 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 103.48 51.44 103.96 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 103.48 56.88 103.96 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 103.48 62.32 103.96 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 103.48 67.76 103.96 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 103.48 73.2 103.96 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 73.12 78.64 73.6 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 73.12 84.08 73.6 84.56 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 36.48 3.2 39.68 ; + RECT 100.76 36.48 103.96 39.68 ; + LAYER met4 ; + RECT 29.14 0 29.74 0.6 ; + RECT 58.58 0 59.18 0.6 ; + RECT 29.14 86.44 29.74 87.04 ; + RECT 58.58 86.44 59.18 87.04 ; + LAYER met1 ; + RECT 0 -0.24 0.48 0.24 ; + RECT 103.48 -0.24 103.96 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 103.48 5.2 103.96 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 103.48 10.64 103.96 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 103.48 16.08 103.96 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 103.48 21.52 103.96 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 103.48 26.96 103.96 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 103.48 32.4 103.96 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 103.48 37.84 103.96 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 103.48 43.28 103.96 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 103.48 48.72 103.96 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 103.48 54.16 103.96 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 103.48 59.6 103.96 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 103.48 65.04 103.96 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 103.48 70.48 103.96 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 103.48 75.92 103.96 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 73.12 81.36 73.6 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 73.12 86.8 73.6 87.28 ; + END + END VSS + OBS + LAYER met2 ; + RECT 58.74 86.735 59.02 87.105 ; + RECT 29.3 86.735 29.58 87.105 ; + POLYGON 60.56 86.94 60.56 83.06 60.42 83.06 60.42 86.8 60.38 86.8 60.38 86.94 ; + POLYGON 44.92 86.94 44.92 63.68 44.78 63.68 44.78 86.8 44.74 86.8 44.74 86.94 ; + POLYGON 17.36 86.94 17.36 86.8 17.32 86.8 17.32 82.04 17.18 82.04 17.18 86.94 ; + POLYGON 15.48 86.94 15.48 83.74 15.34 83.74 15.34 86.8 15.3 86.8 15.3 86.94 ; + POLYGON 4.97 86.885 4.97 86.515 4.9 86.515 4.9 86.12 4.76 86.12 4.76 86.515 4.69 86.515 4.69 86.885 ; + RECT 66.8 86.03 67.06 86.35 ; + RECT 54.84 86.03 55.1 86.35 ; + RECT 41.96 86.03 42.22 86.35 ; + RECT 26.32 86.03 26.58 86.35 ; + POLYGON 86.85 76.005 86.85 75.635 86.78 75.635 86.78 74.9 86.64 74.9 86.64 75.635 86.57 75.635 86.57 76.005 ; + RECT 58.74 -0.065 59.02 0.305 ; + RECT 29.3 -0.065 29.58 0.305 ; + POLYGON 73.32 86.76 73.32 75.88 103.68 75.88 103.68 0.28 0.28 0.28 0.28 86.76 6.32 86.76 6.32 86.275 7.02 86.275 7.02 86.76 7.24 86.76 7.24 86.275 7.94 86.275 7.94 86.76 8.16 86.76 8.16 86.275 8.86 86.275 8.86 86.76 9.08 86.76 9.08 86.275 9.78 86.275 9.78 86.76 10 86.76 10 86.275 10.7 86.275 10.7 86.76 10.92 86.76 10.92 86.275 11.62 86.275 11.62 86.76 11.84 86.76 11.84 86.275 12.54 86.275 12.54 86.76 12.76 86.76 12.76 86.275 13.46 86.275 13.46 86.76 13.68 86.76 13.68 86.275 14.38 86.275 14.38 86.76 14.6 86.76 14.6 86.275 15.3 86.275 15.3 86.76 15.52 86.76 15.52 86.275 16.22 86.275 16.22 86.76 16.44 86.76 16.44 86.275 17.14 86.275 17.14 86.76 17.36 86.76 17.36 86.275 18.06 86.275 18.06 86.76 18.28 86.76 18.28 86.275 18.98 86.275 18.98 86.76 19.2 86.76 19.2 86.275 19.9 86.275 19.9 86.76 20.12 86.76 20.12 86.275 20.82 86.275 20.82 86.76 21.04 86.76 21.04 86.275 21.74 86.275 21.74 86.76 21.96 86.76 21.96 86.275 22.66 86.275 22.66 86.76 22.88 86.76 22.88 86.275 23.58 86.275 23.58 86.76 23.8 86.76 23.8 86.275 24.5 86.275 24.5 86.76 24.72 86.76 24.72 86.275 25.42 86.275 25.42 86.76 25.64 86.76 25.64 86.275 26.34 86.275 26.34 86.76 26.56 86.76 26.56 86.275 27.26 86.275 27.26 86.76 27.48 86.76 27.48 86.275 28.18 86.275 28.18 86.76 28.4 86.76 28.4 86.275 29.1 86.275 29.1 86.76 30.24 86.76 30.24 86.275 30.94 86.275 30.94 86.76 31.16 86.76 31.16 86.275 31.86 86.275 31.86 86.76 32.08 86.76 32.08 86.275 32.78 86.275 32.78 86.76 33 86.76 33 86.275 33.7 86.275 33.7 86.76 33.92 86.76 33.92 86.275 34.62 86.275 34.62 86.76 34.84 86.76 34.84 86.275 35.54 86.275 35.54 86.76 35.76 86.76 35.76 86.275 36.46 86.275 36.46 86.76 36.68 86.76 36.68 86.275 37.38 86.275 37.38 86.76 37.6 86.76 37.6 86.275 38.3 86.275 38.3 86.76 38.52 86.76 38.52 86.275 39.22 86.275 39.22 86.76 39.44 86.76 39.44 86.275 40.14 86.275 40.14 86.76 40.36 86.76 40.36 86.275 41.06 86.275 41.06 86.76 41.28 86.76 41.28 86.275 41.98 86.275 41.98 86.76 42.2 86.76 42.2 86.275 42.9 86.275 42.9 86.76 43.12 86.76 43.12 86.275 43.82 86.275 43.82 86.76 44.04 86.76 44.04 86.275 44.74 86.275 44.74 86.76 44.96 86.76 44.96 86.275 45.66 86.275 45.66 86.76 45.88 86.76 45.88 86.275 46.58 86.275 46.58 86.76 46.8 86.76 46.8 86.275 47.5 86.275 47.5 86.76 47.72 86.76 47.72 86.275 48.42 86.275 48.42 86.76 51.4 86.76 51.4 86.275 52.1 86.275 52.1 86.76 54.16 86.76 54.16 86.275 54.86 86.275 54.86 86.76 55.08 86.76 55.08 86.275 55.78 86.275 55.78 86.76 56 86.76 56 86.275 56.7 86.275 56.7 86.76 56.92 86.76 56.92 86.275 57.62 86.275 57.62 86.76 57.84 86.76 57.84 86.275 58.54 86.275 58.54 86.76 59.68 86.76 59.68 86.275 60.38 86.275 60.38 86.76 60.6 86.76 60.6 86.275 61.3 86.275 61.3 86.76 61.52 86.76 61.52 86.275 62.22 86.275 62.22 86.76 62.44 86.76 62.44 86.275 63.14 86.275 63.14 86.76 63.36 86.76 63.36 86.275 64.06 86.275 64.06 86.76 64.28 86.76 64.28 86.275 64.98 86.275 64.98 86.76 65.2 86.76 65.2 86.275 65.9 86.275 65.9 86.76 66.12 86.76 66.12 86.275 66.82 86.275 66.82 86.76 67.04 86.76 67.04 86.275 67.74 86.275 67.74 86.76 67.96 86.76 67.96 86.275 68.66 86.275 68.66 86.76 68.88 86.76 68.88 86.275 69.58 86.275 69.58 86.76 ; + LAYER met1 ; + POLYGON 72.84 87.28 72.84 86.8 59.04 86.8 59.04 86.79 58.72 86.79 58.72 86.8 29.6 86.8 29.6 86.79 29.28 86.79 29.28 86.8 0.76 86.8 0.76 87.28 ; + RECT 70.84 75.92 103.2 76.4 ; + POLYGON 103.435 33.48 103.435 33.08 93.08 33.08 93.08 33.22 103.295 33.22 103.295 33.48 ; + POLYGON 59.04 0.25 59.04 0.24 103.2 0.24 103.2 -0.24 0.76 -0.24 0.76 0.24 29.28 0.24 29.28 0.25 29.6 0.25 29.6 0.24 58.72 0.24 58.72 0.25 ; + POLYGON 72.84 86.76 72.84 86.52 73.32 86.52 73.32 84.84 72.84 84.84 72.84 83.8 73.32 83.8 73.32 82.12 72.84 82.12 72.84 81.08 73.32 81.08 73.32 79.4 72.84 79.4 72.84 78.36 73.32 78.36 73.32 75.88 103.2 75.88 103.2 75.64 103.68 75.64 103.68 74.64 103.085 74.64 103.085 73.94 103.2 73.94 103.2 72.92 103.68 72.92 103.68 72.6 103.085 72.6 103.085 71.22 103.2 71.22 103.2 70.2 103.68 70.2 103.68 69.88 103.085 69.88 103.085 68.5 103.2 68.5 103.2 67.5 103.085 67.5 103.085 66.12 103.68 66.12 103.68 65.8 103.2 65.8 103.2 64.78 103.085 64.78 103.085 64.08 103.68 64.08 103.68 63.76 103.085 63.76 103.085 63.06 103.2 63.06 103.2 62.04 103.68 62.04 103.68 61.72 103.085 61.72 103.085 60.34 103.2 60.34 103.2 59.34 103.085 59.34 103.085 58.64 103.68 58.64 103.68 58.32 103.085 58.32 103.085 57.62 103.2 57.62 103.2 56.62 103.085 56.62 103.085 55.92 103.68 55.92 103.68 55.6 103.085 55.6 103.085 54.9 103.2 54.9 103.2 53.9 103.085 53.9 103.085 53.2 103.68 53.2 103.68 52.88 103.085 52.88 103.085 52.18 103.2 52.18 103.2 51.18 103.085 51.18 103.085 49.8 103.68 49.8 103.68 49.48 103.2 49.48 103.2 48.46 103.085 48.46 103.085 47.76 103.68 47.76 103.68 47.44 103.085 47.44 103.085 46.74 103.2 46.74 103.2 45.72 103.68 45.72 103.68 45.4 103.085 45.4 103.085 44.02 103.2 44.02 103.2 43 103.68 43 103.68 42.68 103.085 42.68 103.085 41.3 103.2 41.3 103.2 40.3 103.085 40.3 103.085 39.6 103.68 39.6 103.68 39.28 103.085 39.28 103.085 38.58 103.2 38.58 103.2 37.58 103.085 37.58 103.085 36.2 103.68 36.2 103.68 35.88 103.2 35.88 103.2 34.86 103.085 34.86 103.085 33.48 103.68 33.48 103.68 33.16 103.2 33.16 103.2 32.14 103.085 32.14 103.085 30.76 103.68 30.76 103.68 30.44 103.2 30.44 103.2 29.42 103.085 29.42 103.085 28.72 103.68 28.72 103.68 28.4 103.085 28.4 103.085 27.7 103.2 27.7 103.2 26.7 103.085 26.7 103.085 25.32 103.68 25.32 103.68 25 103.2 25 103.2 23.98 103.085 23.98 103.085 22.6 103.68 22.6 103.68 22.28 103.2 22.28 103.2 21.26 103.085 21.26 103.085 19.88 103.68 19.88 103.68 19.56 103.2 19.56 103.2 18.52 103.68 18.52 103.68 17.52 103.085 17.52 103.085 16.82 103.2 16.82 103.2 15.82 103.085 15.82 103.085 14.44 103.68 14.44 103.68 14.12 103.2 14.12 103.2 13.1 103.085 13.1 103.085 12.4 103.68 12.4 103.68 12.08 103.085 12.08 103.085 11.38 103.2 11.38 103.2 10.38 103.085 10.38 103.085 9 103.68 9 103.68 8.68 103.2 8.68 103.2 7.66 103.085 7.66 103.085 6.28 103.68 6.28 103.68 5.96 103.2 5.96 103.2 4.94 103.085 4.94 103.085 3.56 103.68 3.56 103.68 3.24 103.2 3.24 103.2 2.22 103.085 2.22 103.085 1.52 103.68 1.52 103.68 0.52 103.2 0.52 103.2 0.28 0.76 0.28 0.76 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 69.18 0.875 69.18 0.875 69.88 0.28 69.88 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 86.76 ; + LAYER met3 ; + POLYGON 59.045 87.085 59.045 87.08 59.26 87.08 59.26 86.76 59.045 86.76 59.045 86.755 58.715 86.755 58.715 86.76 58.5 86.76 58.5 87.08 58.715 87.08 58.715 87.085 ; + POLYGON 29.605 87.085 29.605 87.08 29.82 87.08 29.82 86.76 29.605 86.76 29.605 86.755 29.275 86.755 29.275 86.76 29.06 86.76 29.06 87.08 29.275 87.08 29.275 87.085 ; + POLYGON 38.115 86.865 38.115 86.85 53.63 86.85 53.63 86.86 54.01 86.86 54.01 86.54 53.63 86.54 53.63 86.55 38.115 86.55 38.115 86.535 37.785 86.535 37.785 86.865 ; + POLYGON 11.435 86.865 11.435 86.535 11.105 86.535 11.105 86.55 4.995 86.55 4.995 86.535 4.665 86.535 4.665 86.865 4.995 86.865 4.995 86.85 11.105 86.85 11.105 86.865 ; + POLYGON 86.875 75.985 86.875 75.655 86.545 75.655 86.545 75.67 61.72 75.67 61.72 75.97 86.545 75.97 86.545 75.985 ; + POLYGON 59.045 0.285 59.045 0.28 59.26 0.28 59.26 -0.04 59.045 -0.04 59.045 -0.045 58.715 -0.045 58.715 -0.04 58.5 -0.04 58.5 0.28 58.715 0.28 58.715 0.285 ; + POLYGON 29.605 0.285 29.605 0.28 29.82 0.28 29.82 -0.04 29.605 -0.04 29.605 -0.045 29.275 -0.045 29.275 -0.04 29.06 -0.04 29.06 0.28 29.275 0.28 29.275 0.285 ; + POLYGON 73.2 86.64 73.2 75.76 103.56 75.76 103.56 68.21 102.76 68.21 102.76 67.11 103.56 67.11 103.56 66.85 102.76 66.85 102.76 65.75 103.56 65.75 103.56 55.29 102.76 55.29 102.76 54.19 103.56 54.19 103.56 53.25 102.76 53.25 102.76 52.15 103.56 52.15 103.56 50.53 102.76 50.53 102.76 49.43 103.56 49.43 103.56 49.17 102.76 49.17 102.76 48.07 103.56 48.07 103.56 47.81 102.76 47.81 102.76 46.71 103.56 46.71 103.56 46.45 102.76 46.45 102.76 45.35 103.56 45.35 103.56 45.09 102.76 45.09 102.76 43.99 103.56 43.99 103.56 43.73 102.76 43.73 102.76 42.63 103.56 42.63 103.56 42.37 102.76 42.37 102.76 41.27 103.56 41.27 103.56 41.01 102.76 41.01 102.76 39.91 103.56 39.91 103.56 39.65 102.76 39.65 102.76 38.55 103.56 38.55 103.56 38.29 102.76 38.29 102.76 37.19 103.56 37.19 103.56 24.69 102.76 24.69 102.76 23.59 103.56 23.59 103.56 23.33 102.76 23.33 102.76 22.23 103.56 22.23 103.56 21.97 102.76 21.97 102.76 20.87 103.56 20.87 103.56 7.69 102.76 7.69 102.76 6.59 103.56 6.59 103.56 6.33 102.76 6.33 102.76 5.23 103.56 5.23 103.56 0.4 0.4 0.4 0.4 86.64 ; + LAYER met4 ; + POLYGON 53.985 86.865 53.985 86.535 53.97 86.535 53.97 73.63 53.67 73.63 53.67 86.535 53.655 86.535 53.655 86.865 ; + POLYGON 73.2 86.64 73.2 75.76 89.46 75.76 89.46 75.16 90.86 75.16 90.86 75.76 103.56 75.76 103.56 0.4 90.86 0.4 90.86 1 89.46 1 89.46 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 15.42 0.4 15.42 1 14.02 1 14.02 0.4 0.4 0.4 0.4 86.64 14.02 86.64 14.02 86.04 15.42 86.04 15.42 86.64 28.74 86.64 28.74 86.04 30.14 86.04 30.14 86.64 43.46 86.64 43.46 86.04 44.86 86.04 44.86 86.64 58.18 86.64 58.18 86.04 59.58 86.04 59.58 86.64 ; + LAYER met5 ; + POLYGON 72 85.44 72 74.56 102.36 74.56 102.36 61.68 99.16 61.68 99.16 55.28 102.36 55.28 102.36 41.28 99.16 41.28 99.16 34.88 102.36 34.88 102.36 20.88 99.16 20.88 99.16 14.48 102.36 14.48 102.36 1.6 1.6 1.6 1.6 14.48 4.8 14.48 4.8 20.88 1.6 20.88 1.6 34.88 4.8 34.88 4.8 41.28 1.6 41.28 1.6 55.28 4.8 55.28 4.8 61.68 1.6 61.68 1.6 85.44 ; + LAYER li1 ; + POLYGON 73.6 87.125 73.6 86.955 67.535 86.955 67.535 86.23 67.245 86.23 67.245 86.955 64.345 86.955 64.345 86.495 64.04 86.495 64.04 86.955 62.555 86.955 62.555 86.515 62.365 86.515 62.365 86.955 60.465 86.955 60.465 86.495 60.135 86.495 60.135 86.955 57.535 86.955 57.535 86.595 57.205 86.595 57.205 86.955 56.505 86.955 56.505 86.575 56.175 86.575 56.175 86.955 52.355 86.955 52.355 86.23 52.065 86.23 52.065 86.955 37.635 86.955 37.635 86.23 37.345 86.23 37.345 86.955 36.745 86.955 36.745 86.495 36.44 86.495 36.44 86.955 34.955 86.955 34.955 86.515 34.765 86.515 34.765 86.955 32.865 86.955 32.865 86.495 32.535 86.495 32.535 86.955 29.935 86.955 29.935 86.595 29.605 86.595 29.605 86.955 28.905 86.955 28.905 86.575 28.575 86.575 28.575 86.955 22.455 86.955 22.455 86.23 22.165 86.23 22.165 86.955 15.845 86.955 15.845 86.495 15.59 86.495 15.59 86.955 14.92 86.955 14.92 86.495 14.75 86.495 14.75 86.955 14.08 86.955 14.08 86.495 13.91 86.495 13.91 86.955 13.24 86.955 13.24 86.495 13.07 86.495 13.07 86.955 12.4 86.955 12.4 86.495 12.095 86.495 12.095 86.955 7.735 86.955 7.735 86.23 7.445 86.23 7.445 86.955 7.225 86.955 7.225 86.495 6.92 86.495 6.92 86.955 6.25 86.955 6.25 86.495 6.08 86.495 6.08 86.955 5.41 86.955 5.41 86.495 5.24 86.495 5.24 86.955 4.57 86.955 4.57 86.495 4.4 86.495 4.4 86.955 3.73 86.955 3.73 86.495 3.475 86.495 3.475 86.955 0 86.955 0 87.125 ; + RECT 72.68 84.235 73.6 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 72.68 81.515 73.6 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 72.68 78.795 73.6 78.965 ; + RECT 0 78.795 3.68 78.965 ; + POLYGON 103.96 76.245 103.96 76.075 97.435 76.075 97.435 75.35 97.145 75.35 97.145 76.075 96.625 76.075 96.625 75.595 96.455 75.595 96.455 76.075 95.785 76.075 95.785 75.595 95.615 75.595 95.615 76.075 95.025 76.075 95.025 75.595 94.695 75.595 94.695 76.075 94.185 76.075 94.185 75.595 93.855 75.595 93.855 76.075 93.345 76.075 93.345 75.275 93.015 75.275 93.015 76.075 90.185 76.075 90.185 75.595 90.015 75.595 90.015 76.075 89.345 76.075 89.345 75.595 89.175 75.595 89.175 76.075 88.585 76.075 88.585 75.595 88.255 75.595 88.255 76.075 87.745 76.075 87.745 75.595 87.415 75.595 87.415 76.075 86.905 76.075 86.905 75.275 86.575 75.275 86.575 76.075 82.255 76.075 82.255 75.35 81.965 75.35 81.965 76.075 77.215 76.075 77.215 75.695 76.885 75.695 76.885 76.075 74.89 76.075 74.89 75.275 74.635 75.275 74.635 76.075 74.045 76.075 74.045 75.695 73.715 75.695 73.715 76.075 71.63 76.075 71.63 75.575 71.43 75.575 71.43 76.075 70.84 76.075 70.84 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 103.04 73.355 103.96 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 103.04 70.635 103.96 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 103.04 67.915 103.96 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 103.04 65.195 103.96 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 103.04 62.475 103.96 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 103.04 59.755 103.96 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 103.04 57.035 103.96 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 103.04 54.315 103.96 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 103.04 51.595 103.96 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 103.04 48.875 103.96 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 103.04 46.155 103.96 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 103.04 43.435 103.96 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 103.04 40.715 103.96 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 103.04 37.995 103.96 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 103.5 35.275 103.96 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 103.04 32.555 103.96 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 103.04 29.835 103.96 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 103.04 27.115 103.96 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 103.04 24.395 103.96 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 103.04 21.675 103.96 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 103.04 18.955 103.96 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 103.04 16.235 103.96 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 103.04 13.515 103.96 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 103.04 10.795 103.96 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 103.04 8.075 103.96 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 103.04 5.355 103.96 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 103.04 2.635 103.96 2.805 ; + RECT 0 2.635 3.68 2.805 ; + POLYGON 97.435 0.81 97.435 0.085 103.96 0.085 103.96 -0.085 0 -0.085 0 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 81.965 0.085 81.965 0.81 82.255 0.81 82.255 0.085 97.145 0.085 97.145 0.81 ; + POLYGON 73.43 86.87 73.43 75.99 103.79 75.99 103.79 0.17 0.17 0.17 0.17 86.87 ; + LAYER via ; + RECT 58.805 86.845 58.955 86.995 ; + RECT 29.365 86.845 29.515 86.995 ; + RECT 13.035 86.455 13.185 86.605 ; + RECT 58.805 0.045 58.955 0.195 ; + RECT 29.365 0.045 29.515 0.195 ; + LAYER via2 ; + RECT 58.78 86.82 58.98 87.02 ; + RECT 29.34 86.82 29.54 87.02 ; + RECT 37.85 86.6 38.05 86.8 ; + RECT 11.17 86.6 11.37 86.8 ; + RECT 4.73 86.6 4.93 86.8 ; + RECT 86.61 75.72 86.81 75.92 ; + RECT 58.78 0.02 58.98 0.22 ; + RECT 29.34 0.02 29.54 0.22 ; + LAYER via3 ; + RECT 58.78 86.82 58.98 87.02 ; + RECT 29.34 86.82 29.54 87.02 ; + RECT 53.72 86.6 53.92 86.8 ; + RECT 58.78 0.02 58.98 0.22 ; + RECT 29.34 0.02 29.54 0.22 ; + LAYER OVERLAP ; + POLYGON 0 0 0 87.04 73.6 87.04 73.6 76.16 103.96 76.16 103.96 0 ; + END +END sb_0__0_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_0__1__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_0__1__icv_in_design.lef new file mode 100644 index 0000000..5d7211b --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_0__1__icv_in_design.lef @@ -0,0 +1,2181 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_0__1_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 103.96 BY 97.92 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.68 97.435 51.82 97.92 ; + END + END pReset[0] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.16 97.435 69.3 97.92 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.36 97.435 55.5 97.92 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.2 97.435 57.34 97.92 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.68 97.435 28.82 97.92 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.48 97.435 65.62 97.92 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 97.435 64.7 97.92 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.44 97.435 8.58 97.92 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.12 97.435 12.26 97.92 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.16 97.435 23.3 97.92 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.24 97.435 22.38 97.92 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.08 97.435 24.22 97.92 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 31.44 97.435 31.58 97.92 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.52 97.435 30.66 97.92 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.4 97.435 66.54 97.92 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.28 97.435 56.42 97.92 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.88 97.435 61.02 97.92 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.2 97.435 34.34 97.92 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.24 97.435 45.38 97.92 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.52 97.435 7.66 97.92 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 32.36 97.435 32.5 97.92 ; + END + END chany_top_in[19] + PIN chany_top_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.96 97.435 60.1 97.92 ; + END + END chany_top_in[20] + PIN chany_top_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.64 97.435 63.78 97.92 ; + END + END chany_top_in[21] + PIN chany_top_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.36 97.435 9.5 97.92 ; + END + END chany_top_in[22] + PIN chany_top_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25.92 97.435 26.06 97.92 ; + END + END chany_top_in[23] + PIN chany_top_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.76 97.435 27.9 97.92 ; + END + END chany_top_in[24] + PIN chany_top_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.6 97.435 6.74 97.92 ; + END + END chany_top_in[25] + PIN chany_top_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48 97.435 48.14 97.92 ; + END + END chany_top_in[26] + PIN chany_top_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.24 97.435 68.38 97.92 ; + END + END chany_top_in[27] + PIN chany_top_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.32 97.435 67.46 97.92 ; + END + END chany_top_in[28] + PIN chany_top_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 97.435 58.26 97.92 ; + END + END chany_top_in[29] + PIN top_left_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.44 97.435 54.58 97.92 ; + END + END top_left_grid_pin_1_[0] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 68.78 103.96 68.92 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 69.46 103.96 69.6 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 43.03 103.96 43.33 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 41.67 103.96 41.97 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 26.71 103.96 27.01 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 52.55 103.96 52.85 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 51.19 103.96 51.49 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 49.74 103.96 49.88 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 45.75 103.96 46.05 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 40.31 103.96 40.61 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 52.46 103.96 52.6 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 44.3 103.96 44.44 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 29.43 103.96 29.73 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 47.11 103.96 47.41 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 53.14 103.96 53.28 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 79.66 103.96 79.8 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 44.39 103.96 44.69 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 41.58 103.96 41.72 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 60.71 103.96 61.01 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 36.14 103.96 36.28 ; + END + END chanx_right_in[19] + PIN chanx_right_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 47.7 103.96 47.84 ; + END + END chanx_right_in[20] + PIN chanx_right_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 74.9 103.96 75.04 ; + END + END chanx_right_in[21] + PIN chanx_right_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 50.42 103.96 50.56 ; + END + END chanx_right_in[22] + PIN chanx_right_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 34.44 103.96 34.58 ; + END + END chanx_right_in[23] + PIN chanx_right_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 49.83 103.96 50.13 ; + END + END chanx_right_in[24] + PIN chanx_right_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 42.26 103.96 42.4 ; + END + END chanx_right_in[25] + PIN chanx_right_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 62.07 103.96 62.37 ; + END + END chanx_right_in[26] + PIN chanx_right_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 53.91 103.96 54.21 ; + END + END chanx_right_in[27] + PIN chanx_right_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 29 103.96 29.14 ; + END + END chanx_right_in[28] + PIN chanx_right_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 48.47 103.96 48.77 ; + END + END chanx_right_in[29] + PIN right_bottom_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 6.22 73.6 6.36 ; + END + END right_bottom_grid_pin_36_[0] + PIN right_bottom_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 12.68 103.96 12.82 ; + END + END right_bottom_grid_pin_37_[0] + PIN right_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 90.78 10.88 90.92 11.365 ; + END + END right_bottom_grid_pin_38_[0] + PIN right_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 14.38 103.96 14.52 ; + END + END right_bottom_grid_pin_39_[0] + PIN right_bottom_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.54 10.88 93.68 11.365 ; + END + END right_bottom_grid_pin_40_[0] + PIN right_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 1.8 73.6 1.94 ; + END + END right_bottom_grid_pin_41_[0] + PIN right_bottom_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 87.56 10.88 87.7 11.365 ; + END + END right_bottom_grid_pin_42_[0] + PIN right_bottom_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94.46 10.88 94.6 11.365 ; + END + END right_bottom_grid_pin_43_[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.24 0 68.38 0.485 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.52 0 53.66 0.485 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.44 0 54.58 0.485 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 17.79 0 18.09 0.8 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.64 0 63.78 0.485 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.96 0 60.1 0.485 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.52 0 30.66 0.485 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.48 0 42.62 0.485 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 0 37.1 0.485 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.36 0 55.5 0.485 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 5.68 0 5.82 0.485 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.2 0 34.34 0.485 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.76 0 50.9 0.485 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 0 58.26 0.485 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 0 64.7 0.485 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.54 0 70.68 0.485 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.62 0 69.76 0.485 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 19.63 0 19.93 0.8 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.24 0 45.38 0.485 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.12 0 12.26 0.485 ; + END + END chany_bottom_in[19] + PIN chany_bottom_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.32 0 44.46 0.485 ; + END + END chany_bottom_in[20] + PIN chany_bottom_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.4 0 66.54 0.485 ; + END + END chany_bottom_in[21] + PIN chany_bottom_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.12 0 35.26 0.485 ; + END + END chany_bottom_in[22] + PIN chany_bottom_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.44 0 8.58 0.485 ; + END + END chany_bottom_in[23] + PIN chany_bottom_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 21.47 0 21.77 0.8 ; + END + END chany_bottom_in[24] + PIN chany_bottom_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.48 0 65.62 0.485 ; + END + END chany_bottom_in[25] + PIN chany_bottom_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.4 0 43.54 0.485 ; + END + END chany_bottom_in[26] + PIN chany_bottom_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.88 0 61.02 0.485 ; + END + END chany_bottom_in[27] + PIN chany_bottom_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.28 0 56.42 0.485 ; + END + END chany_bottom_in[28] + PIN chany_bottom_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.2 0 57.34 0.485 ; + END + END chany_bottom_in[29] + PIN bottom_left_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.6 0 52.74 0.485 ; + END + END bottom_left_grid_pin_1_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 71.5 103.96 71.64 ; + END + END ccff_head[0] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 26.84 97.435 26.98 97.92 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.72 97.435 62.86 97.92 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 97.435 14.1 97.92 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.28 97.435 10.42 97.92 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.32 97.435 44.46 97.92 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.32 97.435 21.46 97.92 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.04 97.435 13.18 97.92 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.12 97.435 35.26 97.92 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.8 97.435 61.94 97.92 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.88 97.435 15.02 97.92 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.4 97.435 43.54 97.92 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 20.4 97.435 20.54 97.92 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25 97.435 25.14 97.92 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.8 97.435 15.94 97.92 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.16 97.435 46.3 97.92 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.04 97.435 36.18 97.92 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.48 97.435 42.62 97.92 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.48 97.435 19.62 97.92 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 33.28 97.435 33.42 97.92 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 97.435 37.1 97.92 ; + END + END chany_top_out[19] + PIN chany_top_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.56 97.435 41.7 97.92 ; + END + END chany_top_out[20] + PIN chany_top_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.72 97.435 16.86 97.92 ; + END + END chany_top_out[21] + PIN chany_top_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.2 97.435 11.34 97.92 ; + END + END chany_top_out[22] + PIN chany_top_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.88 97.435 38.02 97.92 ; + END + END chany_top_out[23] + PIN chany_top_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.08 97.435 47.22 97.92 ; + END + END chany_top_out[24] + PIN chany_top_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.64 97.435 40.78 97.92 ; + END + END chany_top_out[25] + PIN chany_top_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.8 97.435 38.94 97.92 ; + END + END chany_top_out[26] + PIN chany_top_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.56 97.435 18.7 97.92 ; + END + END chany_top_out[27] + PIN chany_top_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.64 97.435 17.78 97.92 ; + END + END chany_top_out[28] + PIN chany_top_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.72 97.435 39.86 97.92 ; + END + END chany_top_out[29] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 56.2 103.96 56.34 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 36.82 103.96 36.96 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 27.98 103.96 28.12 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 38.86 103.96 39 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 76.94 103.96 77.08 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 31.04 103.96 31.18 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 55.52 103.96 55.66 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 55.27 103.96 55.57 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 57.99 103.96 58.29 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 56.63 103.96 56.93 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 37.59 103.96 37.89 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 59.35 103.96 59.65 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 31.72 103.96 31.86 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 77.62 103.96 77.76 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 32.15 103.96 32.45 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 33.51 103.96 33.81 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 74.22 103.96 74.36 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 72.18 103.96 72.32 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 39.54 103.96 39.68 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 25.35 103.96 25.65 ; + END + END chanx_right_out[19] + PIN chanx_right_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 28.07 103.96 28.37 ; + END + END chanx_right_out[20] + PIN chanx_right_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 34.87 103.96 35.17 ; + END + END chanx_right_out[21] + PIN chanx_right_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 25.94 103.96 26.08 ; + END + END chanx_right_out[22] + PIN chanx_right_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 22.54 103.96 22.68 ; + END + END chanx_right_out[23] + PIN chanx_right_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 30.79 103.96 31.09 ; + END + END chanx_right_out[24] + PIN chanx_right_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 23.22 103.96 23.36 ; + END + END chanx_right_out[25] + PIN chanx_right_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 38.95 103.96 39.25 ; + END + END chanx_right_out[26] + PIN chanx_right_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 36.23 103.96 36.53 ; + END + END chanx_right_out[27] + PIN chanx_right_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 25.26 103.96 25.4 ; + END + END chanx_right_out[28] + PIN chanx_right_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 33.76 103.96 33.9 ; + END + END chanx_right_out[29] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.36 0 9.5 0.485 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.72 0 62.86 0.485 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.56 0 41.7 0.485 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.52 0 7.66 0.485 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.16 0 23.3 0.485 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.88 0 38.02 0.485 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.6 0 6.74 0.485 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.04 0 13.18 0.485 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.24 0 22.38 0.485 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.8 0 61.94 0.485 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.64 0 40.78 0.485 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.8 0 38.94 0.485 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.2 0 11.34 0.485 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 0 14.1 0.485 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.32 0 67.46 0.485 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.32 0 21.46 0.485 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.46 0 2.6 0.485 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.88 0 15.02 0.485 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.04 0 36.18 0.485 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 20.4 0 20.54 0.485 ; + END + END chany_bottom_out[19] + PIN chany_bottom_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.8 0 15.94 0.485 ; + END + END chany_bottom_out[20] + PIN chany_bottom_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.48 0 19.62 0.485 ; + END + END chany_bottom_out[21] + PIN chany_bottom_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.28 0 10.42 0.485 ; + END + END chany_bottom_out[22] + PIN chany_bottom_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.72 0 16.86 0.485 ; + END + END chany_bottom_out[23] + PIN chany_bottom_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25 0 25.14 0.485 ; + END + END chany_bottom_out[24] + PIN chany_bottom_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.56 0 18.7 0.485 ; + END + END chany_bottom_out[25] + PIN chany_bottom_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.72 0 39.86 0.485 ; + END + END chany_bottom_out[26] + PIN chany_bottom_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.64 0 17.78 0.485 ; + END + END chany_bottom_out[27] + PIN chany_bottom_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.3 0 4.44 0.485 ; + END + END chany_bottom_out[28] + PIN chany_bottom_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.38 0 3.52 0.485 ; + END + END chany_bottom_out[29] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.08 0 24.22 0.485 ; + END + END ccff_tail[0] + PIN pReset_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 15.4 103.96 15.54 ; + END + END pReset_E_in + PIN pReset_S_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.68 0 28.82 0.485 ; + END + END pReset_S_out + PIN prog_clk_0_E_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met1 ; + RECT 103.365 45.32 103.96 45.46 ; + END + END prog_clk_0_E_in + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 26.96 3.2 30.16 ; + RECT 100.76 26.96 103.96 30.16 ; + RECT 0 67.76 3.2 70.96 ; + RECT 100.76 67.76 103.96 70.96 ; + LAYER met4 ; + RECT 14.42 0 15.02 0.6 ; + RECT 43.86 0 44.46 0.6 ; + RECT 89.86 10.88 90.46 11.48 ; + RECT 89.86 86.44 90.46 87.04 ; + RECT 14.42 97.32 15.02 97.92 ; + RECT 43.86 97.32 44.46 97.92 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 73.12 2.48 73.6 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 73.12 7.92 73.6 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 103.48 13.36 103.96 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 103.48 18.8 103.96 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 103.48 24.24 103.96 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 103.48 29.68 103.96 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 103.48 35.12 103.96 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 103.48 40.56 103.96 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 103.48 46 103.96 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 103.48 51.44 103.96 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 103.48 56.88 103.96 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 103.48 62.32 103.96 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 103.48 67.76 103.96 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 103.48 73.2 103.96 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 103.48 78.64 103.96 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 103.48 84.08 103.96 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 73.12 89.52 73.6 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 73.12 94.96 73.6 95.44 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 47.36 3.2 50.56 ; + RECT 100.76 47.36 103.96 50.56 ; + LAYER met4 ; + RECT 29.14 0 29.74 0.6 ; + RECT 58.58 0 59.18 0.6 ; + RECT 29.14 97.32 29.74 97.92 ; + RECT 58.58 97.32 59.18 97.92 ; + LAYER met1 ; + RECT 0 -0.24 0.48 0.24 ; + RECT 73.12 -0.24 73.6 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 73.12 5.2 73.6 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 103.48 10.64 103.96 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 103.48 16.08 103.96 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 103.48 21.52 103.96 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 103.48 26.96 103.96 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 103.48 32.4 103.96 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 103.48 37.84 103.96 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 103.48 43.28 103.96 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 103.48 48.72 103.96 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 103.48 54.16 103.96 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 103.48 59.6 103.96 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 103.48 65.04 103.96 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 103.48 70.48 103.96 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 103.48 75.92 103.96 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 103.48 81.36 103.96 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 103.48 86.8 103.96 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 73.12 92.24 73.6 92.72 ; + RECT 0 97.68 0.48 98.16 ; + RECT 73.12 97.68 73.6 98.16 ; + END + END VSS + OBS + LAYER met2 ; + RECT 58.74 97.615 59.02 97.985 ; + RECT 29.3 97.615 29.58 97.985 ; + POLYGON 44.92 97.82 44.92 61.3 44.78 61.3 44.78 97.68 44.74 97.68 44.74 97.82 ; + POLYGON 15.48 97.82 15.48 94.11 15.34 94.11 15.34 97.68 15.3 97.68 15.3 97.82 ; + RECT 64.96 97.25 65.22 97.57 ; + POLYGON 100.65 86.885 100.65 86.515 100.58 86.515 100.58 80.34 100.44 80.34 100.44 86.515 100.37 86.515 100.37 86.885 ; + POLYGON 75.74 12.82 75.74 11.405 75.81 11.405 75.81 11.035 75.53 11.035 75.53 11.405 75.6 11.405 75.6 12.82 ; + RECT 93.02 11.23 93.28 11.55 ; + POLYGON 44.92 9.76 44.92 0.1 44.74 0.1 44.74 0.24 44.78 0.24 44.78 9.76 ; + POLYGON 21 4.32 21 0.525 21.07 0.525 21.07 0.155 20.79 0.155 20.79 0.525 20.86 0.525 20.86 4.32 ; + RECT 58.74 -0.065 59.02 0.305 ; + RECT 29.3 -0.065 29.58 0.305 ; + POLYGON 73.32 97.64 73.32 86.76 103.68 86.76 103.68 11.16 94.88 11.16 94.88 11.645 94.18 11.645 94.18 11.16 93.96 11.16 93.96 11.645 93.26 11.645 93.26 11.16 91.2 11.16 91.2 11.645 90.5 11.645 90.5 11.16 87.98 11.16 87.98 11.645 87.28 11.645 87.28 11.16 73.32 11.16 73.32 0.28 70.96 0.28 70.96 0.765 70.26 0.765 70.26 0.28 70.04 0.28 70.04 0.765 69.34 0.765 69.34 0.28 68.66 0.28 68.66 0.765 67.96 0.765 67.96 0.28 67.74 0.28 67.74 0.765 67.04 0.765 67.04 0.28 66.82 0.28 66.82 0.765 66.12 0.765 66.12 0.28 65.9 0.28 65.9 0.765 65.2 0.765 65.2 0.28 64.98 0.28 64.98 0.765 64.28 0.765 64.28 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 63.14 0.28 63.14 0.765 62.44 0.765 62.44 0.28 62.22 0.28 62.22 0.765 61.52 0.765 61.52 0.28 61.3 0.28 61.3 0.765 60.6 0.765 60.6 0.28 60.38 0.28 60.38 0.765 59.68 0.765 59.68 0.28 58.54 0.28 58.54 0.765 57.84 0.765 57.84 0.28 57.62 0.28 57.62 0.765 56.92 0.765 56.92 0.28 56.7 0.28 56.7 0.765 56 0.765 56 0.28 55.78 0.28 55.78 0.765 55.08 0.765 55.08 0.28 54.86 0.28 54.86 0.765 54.16 0.765 54.16 0.28 53.94 0.28 53.94 0.765 53.24 0.765 53.24 0.28 53.02 0.28 53.02 0.765 52.32 0.765 52.32 0.28 51.18 0.28 51.18 0.765 50.48 0.765 50.48 0.28 45.66 0.28 45.66 0.765 44.96 0.765 44.96 0.28 44.74 0.28 44.74 0.765 44.04 0.765 44.04 0.28 43.82 0.28 43.82 0.765 43.12 0.765 43.12 0.28 42.9 0.28 42.9 0.765 42.2 0.765 42.2 0.28 41.98 0.28 41.98 0.765 41.28 0.765 41.28 0.28 41.06 0.28 41.06 0.765 40.36 0.765 40.36 0.28 40.14 0.28 40.14 0.765 39.44 0.765 39.44 0.28 39.22 0.28 39.22 0.765 38.52 0.765 38.52 0.28 38.3 0.28 38.3 0.765 37.6 0.765 37.6 0.28 37.38 0.28 37.38 0.765 36.68 0.765 36.68 0.28 36.46 0.28 36.46 0.765 35.76 0.765 35.76 0.28 35.54 0.28 35.54 0.765 34.84 0.765 34.84 0.28 34.62 0.28 34.62 0.765 33.92 0.765 33.92 0.28 30.94 0.28 30.94 0.765 30.24 0.765 30.24 0.28 29.1 0.28 29.1 0.765 28.4 0.765 28.4 0.28 25.42 0.28 25.42 0.765 24.72 0.765 24.72 0.28 24.5 0.28 24.5 0.765 23.8 0.765 23.8 0.28 23.58 0.28 23.58 0.765 22.88 0.765 22.88 0.28 22.66 0.28 22.66 0.765 21.96 0.765 21.96 0.28 21.74 0.28 21.74 0.765 21.04 0.765 21.04 0.28 20.82 0.28 20.82 0.765 20.12 0.765 20.12 0.28 19.9 0.28 19.9 0.765 19.2 0.765 19.2 0.28 18.98 0.28 18.98 0.765 18.28 0.765 18.28 0.28 18.06 0.28 18.06 0.765 17.36 0.765 17.36 0.28 17.14 0.28 17.14 0.765 16.44 0.765 16.44 0.28 16.22 0.28 16.22 0.765 15.52 0.765 15.52 0.28 15.3 0.28 15.3 0.765 14.6 0.765 14.6 0.28 14.38 0.28 14.38 0.765 13.68 0.765 13.68 0.28 13.46 0.28 13.46 0.765 12.76 0.765 12.76 0.28 12.54 0.28 12.54 0.765 11.84 0.765 11.84 0.28 11.62 0.28 11.62 0.765 10.92 0.765 10.92 0.28 10.7 0.28 10.7 0.765 10 0.765 10 0.28 9.78 0.28 9.78 0.765 9.08 0.765 9.08 0.28 8.86 0.28 8.86 0.765 8.16 0.765 8.16 0.28 7.94 0.28 7.94 0.765 7.24 0.765 7.24 0.28 7.02 0.28 7.02 0.765 6.32 0.765 6.32 0.28 6.1 0.28 6.1 0.765 5.4 0.765 5.4 0.28 4.72 0.28 4.72 0.765 4.02 0.765 4.02 0.28 3.8 0.28 3.8 0.765 3.1 0.765 3.1 0.28 2.88 0.28 2.88 0.765 2.18 0.765 2.18 0.28 0.28 0.28 0.28 97.64 6.32 97.64 6.32 97.155 7.02 97.155 7.02 97.64 7.24 97.64 7.24 97.155 7.94 97.155 7.94 97.64 8.16 97.64 8.16 97.155 8.86 97.155 8.86 97.64 9.08 97.64 9.08 97.155 9.78 97.155 9.78 97.64 10 97.64 10 97.155 10.7 97.155 10.7 97.64 10.92 97.64 10.92 97.155 11.62 97.155 11.62 97.64 11.84 97.64 11.84 97.155 12.54 97.155 12.54 97.64 12.76 97.64 12.76 97.155 13.46 97.155 13.46 97.64 13.68 97.64 13.68 97.155 14.38 97.155 14.38 97.64 14.6 97.64 14.6 97.155 15.3 97.155 15.3 97.64 15.52 97.64 15.52 97.155 16.22 97.155 16.22 97.64 16.44 97.64 16.44 97.155 17.14 97.155 17.14 97.64 17.36 97.64 17.36 97.155 18.06 97.155 18.06 97.64 18.28 97.64 18.28 97.155 18.98 97.155 18.98 97.64 19.2 97.64 19.2 97.155 19.9 97.155 19.9 97.64 20.12 97.64 20.12 97.155 20.82 97.155 20.82 97.64 21.04 97.64 21.04 97.155 21.74 97.155 21.74 97.64 21.96 97.64 21.96 97.155 22.66 97.155 22.66 97.64 22.88 97.64 22.88 97.155 23.58 97.155 23.58 97.64 23.8 97.64 23.8 97.155 24.5 97.155 24.5 97.64 24.72 97.64 24.72 97.155 25.42 97.155 25.42 97.64 25.64 97.64 25.64 97.155 26.34 97.155 26.34 97.64 26.56 97.64 26.56 97.155 27.26 97.155 27.26 97.64 27.48 97.64 27.48 97.155 28.18 97.155 28.18 97.64 28.4 97.64 28.4 97.155 29.1 97.155 29.1 97.64 30.24 97.64 30.24 97.155 30.94 97.155 30.94 97.64 31.16 97.64 31.16 97.155 31.86 97.155 31.86 97.64 32.08 97.64 32.08 97.155 32.78 97.155 32.78 97.64 33 97.64 33 97.155 33.7 97.155 33.7 97.64 33.92 97.64 33.92 97.155 34.62 97.155 34.62 97.64 34.84 97.64 34.84 97.155 35.54 97.155 35.54 97.64 35.76 97.64 35.76 97.155 36.46 97.155 36.46 97.64 36.68 97.64 36.68 97.155 37.38 97.155 37.38 97.64 37.6 97.64 37.6 97.155 38.3 97.155 38.3 97.64 38.52 97.64 38.52 97.155 39.22 97.155 39.22 97.64 39.44 97.64 39.44 97.155 40.14 97.155 40.14 97.64 40.36 97.64 40.36 97.155 41.06 97.155 41.06 97.64 41.28 97.64 41.28 97.155 41.98 97.155 41.98 97.64 42.2 97.64 42.2 97.155 42.9 97.155 42.9 97.64 43.12 97.64 43.12 97.155 43.82 97.155 43.82 97.64 44.04 97.64 44.04 97.155 44.74 97.155 44.74 97.64 44.96 97.64 44.96 97.155 45.66 97.155 45.66 97.64 45.88 97.64 45.88 97.155 46.58 97.155 46.58 97.64 46.8 97.64 46.8 97.155 47.5 97.155 47.5 97.64 47.72 97.64 47.72 97.155 48.42 97.155 48.42 97.64 51.4 97.64 51.4 97.155 52.1 97.155 52.1 97.64 54.16 97.64 54.16 97.155 54.86 97.155 54.86 97.64 55.08 97.64 55.08 97.155 55.78 97.155 55.78 97.64 56 97.64 56 97.155 56.7 97.155 56.7 97.64 56.92 97.64 56.92 97.155 57.62 97.155 57.62 97.64 57.84 97.64 57.84 97.155 58.54 97.155 58.54 97.64 59.68 97.64 59.68 97.155 60.38 97.155 60.38 97.64 60.6 97.64 60.6 97.155 61.3 97.155 61.3 97.64 61.52 97.64 61.52 97.155 62.22 97.155 62.22 97.64 62.44 97.64 62.44 97.155 63.14 97.155 63.14 97.64 63.36 97.64 63.36 97.155 64.06 97.155 64.06 97.64 64.28 97.64 64.28 97.155 64.98 97.155 64.98 97.64 65.2 97.64 65.2 97.155 65.9 97.155 65.9 97.64 66.12 97.64 66.12 97.155 66.82 97.155 66.82 97.64 67.04 97.64 67.04 97.155 67.74 97.155 67.74 97.64 67.96 97.64 67.96 97.155 68.66 97.155 68.66 97.64 68.88 97.64 68.88 97.155 69.58 97.155 69.58 97.64 ; + LAYER met1 ; + POLYGON 72.84 98.16 72.84 97.68 59.04 97.68 59.04 97.67 58.72 97.67 58.72 97.68 29.6 97.68 29.6 97.67 29.28 97.67 29.28 97.68 0.76 97.68 0.76 98.16 ; + RECT 65.78 86.8 103.2 87.28 ; + RECT 72.22 10.64 103.2 11.12 ; + POLYGON 59.04 0.25 59.04 0.24 72.84 0.24 72.84 -0.24 0.76 -0.24 0.76 0.24 29.28 0.24 29.28 0.25 29.6 0.25 29.6 0.24 58.72 0.24 58.72 0.25 ; + POLYGON 72.84 97.64 72.84 97.4 73.32 97.4 73.32 95.72 72.84 95.72 72.84 94.68 73.32 94.68 73.32 93 72.84 93 72.84 91.96 73.32 91.96 73.32 90.28 72.84 90.28 72.84 89.24 73.32 89.24 73.32 86.76 103.2 86.76 103.2 86.52 103.68 86.52 103.68 84.84 103.2 84.84 103.2 83.8 103.68 83.8 103.68 82.12 103.2 82.12 103.2 81.08 103.68 81.08 103.68 80.08 103.085 80.08 103.085 79.38 103.2 79.38 103.2 78.36 103.68 78.36 103.68 78.04 103.085 78.04 103.085 76.66 103.2 76.66 103.2 75.64 103.68 75.64 103.68 75.32 103.085 75.32 103.085 73.94 103.2 73.94 103.2 72.92 103.68 72.92 103.68 72.6 103.085 72.6 103.085 71.22 103.2 71.22 103.2 70.2 103.68 70.2 103.68 69.88 103.085 69.88 103.085 68.5 103.2 68.5 103.2 67.48 103.68 67.48 103.68 65.8 103.2 65.8 103.2 64.76 103.68 64.76 103.68 63.08 103.2 63.08 103.2 62.04 103.68 62.04 103.68 60.36 103.2 60.36 103.2 59.32 103.68 59.32 103.68 57.64 103.2 57.64 103.2 56.62 103.085 56.62 103.085 55.24 103.68 55.24 103.68 54.92 103.2 54.92 103.2 53.88 103.68 53.88 103.68 53.56 103.085 53.56 103.085 52.18 103.2 52.18 103.2 51.16 103.68 51.16 103.68 50.84 103.085 50.84 103.085 49.46 103.2 49.46 103.2 48.44 103.68 48.44 103.68 48.12 103.085 48.12 103.085 47.42 103.68 47.42 103.68 46.76 103.2 46.76 103.2 45.74 103.085 45.74 103.085 45.04 103.68 45.04 103.68 44.72 103.085 44.72 103.085 44.02 103.2 44.02 103.2 43 103.68 43 103.68 42.68 103.085 42.68 103.085 41.3 103.2 41.3 103.2 40.28 103.68 40.28 103.68 39.96 103.085 39.96 103.085 38.58 103.2 38.58 103.2 37.56 103.68 37.56 103.68 37.24 103.085 37.24 103.085 35.86 103.2 35.86 103.2 34.86 103.085 34.86 103.085 33.48 103.68 33.48 103.68 33.16 103.2 33.16 103.2 32.14 103.085 32.14 103.085 30.76 103.68 30.76 103.68 30.44 103.2 30.44 103.2 29.42 103.085 29.42 103.085 28.72 103.68 28.72 103.68 28.4 103.085 28.4 103.085 27.7 103.2 27.7 103.2 26.68 103.68 26.68 103.68 26.36 103.085 26.36 103.085 24.98 103.2 24.98 103.2 23.96 103.68 23.96 103.68 23.64 103.085 23.64 103.085 22.26 103.2 22.26 103.2 21.24 103.68 21.24 103.68 19.56 103.2 19.56 103.2 18.52 103.68 18.52 103.68 16.84 103.2 16.84 103.2 15.82 103.085 15.82 103.085 15.12 103.68 15.12 103.68 14.8 103.085 14.8 103.085 14.1 103.2 14.1 103.2 13.1 103.085 13.1 103.085 12.4 103.68 12.4 103.68 11.4 103.2 11.4 103.2 11.16 73.32 11.16 73.32 8.68 72.84 8.68 72.84 7.64 73.32 7.64 73.32 6.64 72.725 6.64 72.725 5.94 72.84 5.94 72.84 4.92 73.32 4.92 73.32 3.24 72.84 3.24 72.84 2.22 72.725 2.22 72.725 1.52 73.32 1.52 73.32 0.52 72.84 0.52 72.84 0.28 0.76 0.28 0.76 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 0.76 97.4 0.76 97.64 ; + LAYER met3 ; + POLYGON 59.045 97.965 59.045 97.96 59.26 97.96 59.26 97.64 59.045 97.64 59.045 97.635 58.715 97.635 58.715 97.64 58.5 97.64 58.5 97.96 58.715 97.96 58.715 97.965 ; + POLYGON 29.605 97.965 29.605 97.96 29.82 97.96 29.82 97.64 29.605 97.64 29.605 97.635 29.275 97.635 29.275 97.64 29.06 97.64 29.06 97.96 29.275 97.96 29.275 97.965 ; + POLYGON 100.675 86.865 100.675 86.535 100.345 86.535 100.345 86.55 72.3 86.55 72.3 86.85 100.345 86.85 100.345 86.865 ; + POLYGON 87.795 11.385 87.795 11.055 87.465 11.055 87.465 11.07 75.835 11.07 75.835 11.055 75.505 11.055 75.505 11.385 75.835 11.385 75.835 11.37 87.465 11.37 87.465 11.385 ; + POLYGON 21.095 0.505 21.095 0.49 21.43 0.49 21.43 0.5 21.81 0.5 21.81 0.18 21.43 0.18 21.43 0.19 21.095 0.19 21.095 0.175 20.765 0.175 20.765 0.505 ; + POLYGON 59.045 0.285 59.045 0.28 59.26 0.28 59.26 -0.04 59.045 -0.04 59.045 -0.045 58.715 -0.045 58.715 -0.04 58.5 -0.04 58.5 0.28 58.715 0.28 58.715 0.285 ; + POLYGON 29.605 0.285 29.605 0.28 29.82 0.28 29.82 -0.04 29.605 -0.04 29.605 -0.045 29.275 -0.045 29.275 -0.04 29.06 -0.04 29.06 0.28 29.275 0.28 29.275 0.285 ; + POLYGON 73.2 97.52 73.2 86.64 103.56 86.64 103.56 62.77 102.76 62.77 102.76 61.67 103.56 61.67 103.56 61.41 102.76 61.41 102.76 60.31 103.56 60.31 103.56 60.05 102.76 60.05 102.76 58.95 103.56 58.95 103.56 58.69 102.76 58.69 102.76 57.59 103.56 57.59 103.56 57.33 102.76 57.33 102.76 56.23 103.56 56.23 103.56 55.97 102.76 55.97 102.76 54.87 103.56 54.87 103.56 54.61 102.76 54.61 102.76 53.51 103.56 53.51 103.56 53.25 102.76 53.25 102.76 52.15 103.56 52.15 103.56 51.89 102.76 51.89 102.76 50.79 103.56 50.79 103.56 50.53 102.76 50.53 102.76 49.43 103.56 49.43 103.56 49.17 102.76 49.17 102.76 48.07 103.56 48.07 103.56 47.81 102.76 47.81 102.76 46.71 103.56 46.71 103.56 46.45 102.76 46.45 102.76 45.35 103.56 45.35 103.56 45.09 102.76 45.09 102.76 43.99 103.56 43.99 103.56 43.73 102.76 43.73 102.76 42.63 103.56 42.63 103.56 42.37 102.76 42.37 102.76 41.27 103.56 41.27 103.56 41.01 102.76 41.01 102.76 39.91 103.56 39.91 103.56 39.65 102.76 39.65 102.76 38.55 103.56 38.55 103.56 38.29 102.76 38.29 102.76 37.19 103.56 37.19 103.56 36.93 102.76 36.93 102.76 35.83 103.56 35.83 103.56 35.57 102.76 35.57 102.76 34.47 103.56 34.47 103.56 34.21 102.76 34.21 102.76 33.11 103.56 33.11 103.56 32.85 102.76 32.85 102.76 31.75 103.56 31.75 103.56 31.49 102.76 31.49 102.76 30.39 103.56 30.39 103.56 30.13 102.76 30.13 102.76 29.03 103.56 29.03 103.56 28.77 102.76 28.77 102.76 27.67 103.56 27.67 103.56 27.41 102.76 27.41 102.76 26.31 103.56 26.31 103.56 26.05 102.76 26.05 102.76 24.95 103.56 24.95 103.56 11.28 73.2 11.28 73.2 0.4 0.4 0.4 0.4 97.52 ; + LAYER met4 ; + POLYGON 73.29 35.17 73.29 0.87 72.07 0.87 72.07 1.17 72.99 1.17 72.99 35.17 ; + POLYGON 73.2 97.52 73.2 86.64 89.46 86.64 89.46 86.04 90.86 86.04 90.86 86.64 103.56 86.64 103.56 11.28 90.86 11.28 90.86 11.88 89.46 11.88 89.46 11.28 73.2 11.28 73.2 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 22.17 0.4 22.17 1.2 21.07 1.2 21.07 0.4 20.33 0.4 20.33 1.2 19.23 1.2 19.23 0.4 18.49 0.4 18.49 1.2 17.39 1.2 17.39 0.4 15.42 0.4 15.42 1 14.02 1 14.02 0.4 0.4 0.4 0.4 97.52 14.02 97.52 14.02 96.92 15.42 96.92 15.42 97.52 28.74 97.52 28.74 96.92 30.14 96.92 30.14 97.52 43.46 97.52 43.46 96.92 44.86 96.92 44.86 97.52 58.18 97.52 58.18 96.92 59.58 96.92 59.58 97.52 ; + LAYER met5 ; + POLYGON 72 96.32 72 85.44 102.36 85.44 102.36 72.56 99.16 72.56 99.16 66.16 102.36 66.16 102.36 52.16 99.16 52.16 99.16 45.76 102.36 45.76 102.36 31.76 99.16 31.76 99.16 25.36 102.36 25.36 102.36 12.48 72 12.48 72 1.6 1.6 1.6 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 96.32 ; + LAYER li1 ; + POLYGON 73.6 98.005 73.6 97.835 67.535 97.835 67.535 97.11 67.245 97.11 67.245 97.835 66.185 97.835 66.185 97.355 65.855 97.355 65.855 97.835 65.345 97.835 65.345 97.355 65.015 97.355 65.015 97.835 64.505 97.835 64.505 97.355 64.175 97.355 64.175 97.835 63.665 97.835 63.665 97.355 63.335 97.355 63.335 97.835 62.825 97.835 62.825 97.355 62.495 97.355 62.495 97.835 61.985 97.835 61.985 97.035 61.655 97.035 61.655 97.835 60.745 97.835 60.745 97.355 60.575 97.355 60.575 97.835 59.905 97.835 59.905 97.355 59.735 97.355 59.735 97.835 59.145 97.835 59.145 97.355 58.815 97.355 58.815 97.835 58.305 97.835 58.305 97.355 57.975 97.355 57.975 97.835 57.465 97.835 57.465 97.035 57.135 97.035 57.135 97.835 52.355 97.835 52.355 97.11 52.065 97.11 52.065 97.835 51.845 97.835 51.845 97.375 51.54 97.375 51.54 97.835 50.87 97.835 50.87 97.375 50.7 97.375 50.7 97.835 50.03 97.835 50.03 97.375 49.86 97.375 49.86 97.835 49.19 97.835 49.19 97.375 49.02 97.375 49.02 97.835 48.35 97.835 48.35 97.375 48.095 97.375 48.095 97.835 47.325 97.835 47.325 97.355 46.995 97.355 46.995 97.835 46.485 97.835 46.485 97.355 46.155 97.355 46.155 97.835 45.645 97.835 45.645 97.355 45.315 97.355 45.315 97.835 44.805 97.835 44.805 97.355 44.475 97.355 44.475 97.835 43.965 97.835 43.965 97.355 43.635 97.355 43.635 97.835 43.125 97.835 43.125 97.035 42.795 97.035 42.795 97.835 42.065 97.835 42.065 97.375 41.81 97.375 41.81 97.835 41.14 97.835 41.14 97.375 40.97 97.375 40.97 97.835 40.3 97.835 40.3 97.375 40.13 97.375 40.13 97.835 39.46 97.835 39.46 97.375 39.29 97.375 39.29 97.835 38.62 97.835 38.62 97.375 38.315 97.375 38.315 97.835 37.635 97.835 37.635 97.11 37.345 97.11 37.345 97.835 33.565 97.835 33.565 97.035 33.235 97.035 33.235 97.835 32.725 97.835 32.725 97.355 32.395 97.355 32.395 97.835 31.885 97.835 31.885 97.355 31.555 97.355 31.555 97.835 31.045 97.835 31.045 97.355 30.715 97.355 30.715 97.835 30.205 97.835 30.205 97.355 29.875 97.355 29.875 97.835 29.365 97.835 29.365 97.355 29.035 97.355 29.035 97.835 28.005 97.835 28.005 97.355 27.675 97.355 27.675 97.835 27.165 97.835 27.165 97.355 26.835 97.355 26.835 97.835 26.325 97.835 26.325 97.355 25.995 97.355 25.995 97.835 25.485 97.835 25.485 97.355 25.155 97.355 25.155 97.835 24.645 97.835 24.645 97.355 24.315 97.355 24.315 97.835 23.805 97.835 23.805 97.035 23.475 97.035 23.475 97.835 22.455 97.835 22.455 97.11 22.165 97.11 22.165 97.835 21.645 97.835 21.645 97.355 21.475 97.355 21.475 97.835 20.805 97.835 20.805 97.355 20.635 97.355 20.635 97.835 20.045 97.835 20.045 97.355 19.715 97.355 19.715 97.835 19.205 97.835 19.205 97.355 18.875 97.355 18.875 97.835 18.365 97.835 18.365 97.035 18.035 97.035 18.035 97.835 16.125 97.835 16.125 97.355 15.955 97.355 15.955 97.835 15.285 97.835 15.285 97.355 15.115 97.355 15.115 97.835 14.525 97.835 14.525 97.355 14.195 97.355 14.195 97.835 13.685 97.835 13.685 97.355 13.355 97.355 13.355 97.835 12.845 97.835 12.845 97.035 12.515 97.035 12.515 97.835 7.735 97.835 7.735 97.11 7.445 97.11 7.445 97.835 6.385 97.835 6.385 97.435 6.055 97.435 6.055 97.835 4.095 97.835 4.095 97.3 3.585 97.3 3.585 97.835 0 97.835 0 98.005 ; + RECT 73.14 95.115 73.6 95.285 ; + RECT 0 95.115 3.68 95.285 ; + RECT 72.68 92.395 73.6 92.565 ; + RECT 0 92.395 3.68 92.565 ; + RECT 72.68 89.675 73.6 89.845 ; + RECT 0 89.675 3.68 89.845 ; + POLYGON 103.96 87.125 103.96 86.955 97.435 86.955 97.435 86.23 97.145 86.23 97.145 86.955 96.97 86.955 96.97 86.155 96.715 86.155 96.715 86.955 96.125 86.955 96.125 86.575 95.795 86.575 95.795 86.955 93.71 86.955 93.71 86.455 93.51 86.455 93.51 86.955 92.395 86.955 92.395 86.575 92.065 86.575 92.065 86.955 91.025 86.955 91.025 86.495 90.72 86.495 90.72 86.955 89.235 86.955 89.235 86.515 89.045 86.515 89.045 86.955 87.145 86.955 87.145 86.495 86.815 86.495 86.815 86.955 84.215 86.955 84.215 86.595 83.885 86.595 83.885 86.955 83.185 86.955 83.185 86.575 82.855 86.575 82.855 86.955 82.255 86.955 82.255 86.23 81.965 86.23 81.965 86.955 79.065 86.955 79.065 86.555 78.735 86.555 78.735 86.955 76.775 86.955 76.775 86.42 76.265 86.42 76.265 86.955 74.465 86.955 74.465 86.495 74.16 86.495 74.16 86.955 72.675 86.955 72.675 86.515 72.485 86.515 72.485 86.955 70.585 86.955 70.585 86.495 70.255 86.495 70.255 86.955 67.655 86.955 67.655 86.595 67.325 86.595 67.325 86.955 66.625 86.955 66.625 86.575 66.295 86.575 66.295 86.955 65.78 86.955 65.78 87.125 ; + RECT 0 86.955 3.68 87.125 ; + RECT 103.04 84.235 103.96 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 103.04 81.515 103.96 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 103.04 78.795 103.96 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 103.04 76.075 103.96 76.245 ; + RECT 0 76.075 1.84 76.245 ; + RECT 103.04 73.355 103.96 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 103.04 70.635 103.96 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 103.04 67.915 103.96 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 103.04 65.195 103.96 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 103.04 62.475 103.96 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 103.04 59.755 103.96 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 103.04 57.035 103.96 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 103.04 54.315 103.96 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 103.04 51.595 103.96 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 103.04 48.875 103.96 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 103.04 46.155 103.96 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 103.04 43.435 103.96 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 103.04 40.715 103.96 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 103.04 37.995 103.96 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 103.04 35.275 103.96 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 103.04 32.555 103.96 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 103.04 29.835 103.96 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 103.04 27.115 103.96 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 103.04 24.395 103.96 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 103.04 21.675 103.96 21.845 ; + RECT 0 21.675 1.84 21.845 ; + RECT 103.04 18.955 103.96 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 103.04 16.235 103.96 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 103.04 13.515 103.96 13.685 ; + RECT 0 13.515 3.68 13.685 ; + POLYGON 96.23 11.785 96.23 10.965 97.145 10.965 97.145 11.69 97.435 11.69 97.435 10.965 103.96 10.965 103.96 10.795 72.22 10.795 72.22 10.965 72.745 10.965 72.745 11.345 73.075 11.345 73.075 10.965 74.425 10.965 74.425 11.5 74.935 11.5 74.935 10.965 76.895 10.965 76.895 11.365 77.225 11.365 77.225 10.965 78.565 10.965 78.565 11.5 79.075 11.5 79.075 10.965 81.035 10.965 81.035 11.365 81.365 11.365 81.365 10.965 81.965 10.965 81.965 11.69 82.255 11.69 82.255 10.965 84.705 10.965 84.705 11.345 85.035 11.345 85.035 10.965 87.305 10.965 87.305 11.5 87.815 11.5 87.815 10.965 89.775 10.965 89.775 11.365 90.105 11.365 90.105 10.965 92.365 10.965 92.365 11.5 92.875 11.5 92.875 10.965 94.835 10.965 94.835 11.365 95.165 11.365 95.165 10.965 96 10.965 96 11.785 ; + RECT 0 10.795 3.68 10.965 ; + RECT 72.68 8.075 73.6 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 72.68 5.355 73.6 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 72.68 2.635 73.6 2.805 ; + RECT 0 2.635 3.68 2.805 ; + POLYGON 62.445 0.885 62.445 0.085 62.955 0.085 62.955 0.565 63.285 0.565 63.285 0.085 63.795 0.085 63.795 0.565 64.125 0.565 64.125 0.085 64.635 0.085 64.635 0.565 64.965 0.565 64.965 0.085 65.475 0.085 65.475 0.565 65.805 0.565 65.805 0.085 66.315 0.085 66.315 0.565 66.645 0.565 66.645 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 73.6 0.085 73.6 -0.085 0 -0.085 0 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 8.255 0.085 8.255 0.565 8.425 0.565 8.425 0.085 9.095 0.085 9.095 0.565 9.265 0.565 9.265 0.085 9.855 0.085 9.855 0.565 10.185 0.565 10.185 0.085 10.695 0.085 10.695 0.565 11.025 0.565 11.025 0.085 11.535 0.085 11.535 0.885 11.865 0.885 11.865 0.085 14.815 0.085 14.815 0.885 15.145 0.885 15.145 0.085 15.655 0.085 15.655 0.565 15.985 0.565 15.985 0.085 16.495 0.085 16.495 0.565 16.825 0.565 16.825 0.085 17.415 0.085 17.415 0.565 17.585 0.565 17.585 0.085 18.255 0.085 18.255 0.565 18.425 0.565 18.425 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 25.395 0.085 25.395 0.885 25.725 0.885 25.725 0.085 26.235 0.085 26.235 0.565 26.565 0.565 26.565 0.085 27.075 0.085 27.075 0.565 27.405 0.565 27.405 0.085 27.995 0.085 27.995 0.565 28.165 0.565 28.165 0.085 28.835 0.085 28.835 0.565 29.005 0.565 29.005 0.085 29.955 0.085 29.955 0.565 30.285 0.565 30.285 0.085 30.795 0.085 30.795 0.565 31.125 0.565 31.125 0.085 31.635 0.085 31.635 0.565 31.965 0.565 31.965 0.085 32.475 0.085 32.475 0.565 32.805 0.565 32.805 0.085 33.315 0.085 33.315 0.565 33.645 0.565 33.645 0.085 34.155 0.085 34.155 0.885 34.485 0.885 34.485 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 39.195 0.085 39.195 0.885 39.525 0.885 39.525 0.085 40.035 0.085 40.035 0.565 40.365 0.565 40.365 0.085 40.875 0.085 40.875 0.565 41.205 0.565 41.205 0.085 41.795 0.085 41.795 0.565 41.965 0.565 41.965 0.085 42.635 0.085 42.635 0.565 42.805 0.565 42.805 0.085 43.755 0.085 43.755 0.565 44.085 0.565 44.085 0.085 44.595 0.085 44.595 0.565 44.925 0.565 44.925 0.085 45.435 0.085 45.435 0.565 45.765 0.565 45.765 0.085 46.275 0.085 46.275 0.565 46.605 0.565 46.605 0.085 47.115 0.085 47.115 0.565 47.445 0.565 47.445 0.085 47.955 0.085 47.955 0.885 48.285 0.885 48.285 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 56.595 0.085 56.595 0.885 56.925 0.885 56.925 0.085 57.435 0.085 57.435 0.565 57.765 0.565 57.765 0.085 58.275 0.085 58.275 0.565 58.605 0.565 58.605 0.085 59.115 0.085 59.115 0.565 59.445 0.565 59.445 0.085 59.955 0.085 59.955 0.565 60.285 0.565 60.285 0.085 60.795 0.085 60.795 0.565 61.125 0.565 61.125 0.085 62.115 0.085 62.115 0.885 ; + POLYGON 73.43 97.75 73.43 86.87 103.79 86.87 103.79 11.05 73.43 11.05 73.43 0.17 0.17 0.17 0.17 97.75 ; + LAYER via ; + RECT 58.805 97.725 58.955 97.875 ; + RECT 29.365 97.725 29.515 97.875 ; + RECT 69.155 97.335 69.305 97.485 ; + RECT 62.715 97.335 62.865 97.485 ; + RECT 38.795 97.335 38.945 97.485 ; + RECT 32.355 97.335 32.505 97.485 ; + RECT 13.955 97.335 14.105 97.485 ; + RECT 6.595 97.335 6.745 97.485 ; + RECT 42.475 0.435 42.625 0.585 ; + RECT 28.675 0.435 28.825 0.585 ; + RECT 58.805 0.045 58.955 0.195 ; + RECT 29.365 0.045 29.515 0.195 ; + LAYER via2 ; + RECT 58.78 97.7 58.98 97.9 ; + RECT 29.34 97.7 29.54 97.9 ; + RECT 100.41 86.6 100.61 86.8 ; + RECT 102.71 62.12 102.91 62.32 ; + RECT 87.53 11.12 87.73 11.32 ; + RECT 75.57 11.12 75.77 11.32 ; + RECT 20.83 0.24 21.03 0.44 ; + RECT 58.78 0.02 58.98 0.22 ; + RECT 29.34 0.02 29.54 0.22 ; + LAYER via3 ; + RECT 58.78 97.7 58.98 97.9 ; + RECT 29.34 97.7 29.54 97.9 ; + RECT 19.68 0.92 19.88 1.12 ; + RECT 21.52 0.24 21.72 0.44 ; + RECT 58.78 0.02 58.98 0.22 ; + RECT 29.34 0.02 29.54 0.22 ; + LAYER OVERLAP ; + POLYGON 0 0 0 97.92 73.6 97.92 73.6 87.04 103.96 87.04 103.96 10.88 73.6 10.88 73.6 0 ; + END +END sb_0__1_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_0__2__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_0__2__icv_in_design.lef new file mode 100644 index 0000000..1a2a245 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_0__2__icv_in_design.lef @@ -0,0 +1,1692 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_0__2_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 103.96 BY 87.04 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.14 86.555 52.28 87.04 ; + END + END pReset[0] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 43.03 103.96 43.33 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 77.28 103.96 77.42 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 61.3 103.96 61.44 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 50.42 103.96 50.56 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 55.27 103.96 55.57 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 53.48 103.96 53.62 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 56.63 103.96 56.93 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 18.12 103.96 18.26 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 36.23 103.96 36.53 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 52.46 103.96 52.6 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 32.15 103.96 32.45 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 34.87 103.96 35.17 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 36.14 103.96 36.28 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 49.74 103.96 49.88 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 60.62 103.96 60.76 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 33.51 103.96 33.81 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 53.91 103.96 54.21 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 23.56 103.96 23.7 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 31.72 103.96 31.86 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 55.86 103.96 56 ; + END + END chanx_right_in[19] + PIN chanx_right_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 68.78 103.96 68.92 ; + END + END chanx_right_in[20] + PIN chanx_right_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 37.16 103.96 37.3 ; + END + END chanx_right_in[21] + PIN chanx_right_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 52.55 103.96 52.85 ; + END + END chanx_right_in[22] + PIN chanx_right_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 33.76 103.96 33.9 ; + END + END chanx_right_in[23] + PIN chanx_right_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 57.9 103.96 58.04 ; + END + END chanx_right_in[24] + PIN chanx_right_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 45.75 103.96 46.05 ; + END + END chanx_right_in[25] + PIN chanx_right_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 34.44 103.96 34.58 ; + END + END chanx_right_in[26] + PIN chanx_right_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 71.5 103.96 71.64 ; + END + END chanx_right_in[27] + PIN chanx_right_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 41.58 103.96 41.72 ; + END + END chanx_right_in[28] + PIN chanx_right_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 69.46 103.96 69.6 ; + END + END chanx_right_in[29] + PIN right_top_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 42.26 103.96 42.4 ; + END + END right_top_grid_pin_1_[0] + PIN right_bottom_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 99.52 10.88 99.66 11.365 ; + END + END right_bottom_grid_pin_36_[0] + PIN right_bottom_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 12.68 103.96 12.82 ; + END + END right_bottom_grid_pin_37_[0] + PIN right_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 90.78 10.88 90.92 11.365 ; + END + END right_bottom_grid_pin_38_[0] + PIN right_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 14.38 103.96 14.52 ; + END + END right_bottom_grid_pin_39_[0] + PIN right_bottom_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.54 10.88 93.68 11.365 ; + END + END right_bottom_grid_pin_40_[0] + PIN right_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 73.005 1.8 73.6 1.94 ; + END + END right_bottom_grid_pin_41_[0] + PIN right_bottom_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 87.56 10.88 87.7 11.365 ; + END + END right_bottom_grid_pin_42_[0] + PIN right_bottom_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94.46 10.88 94.6 11.365 ; + END + END right_bottom_grid_pin_43_[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.24 0 68.38 0.485 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.52 0 53.66 0.485 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.44 0 54.58 0.485 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 17.79 0 18.09 0.8 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.64 0 63.78 0.485 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.96 0 60.1 0.485 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 30.52 0 30.66 0.485 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.48 0 42.62 0.485 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 0 37.1 0.485 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.36 0 55.5 0.485 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 5.68 0 5.82 0.485 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.2 0 34.34 0.485 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.76 0 50.9 0.485 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 0 58.26 0.485 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 0 64.7 0.485 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.54 0 70.68 0.485 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.62 0 69.76 0.485 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 19.63 0 19.93 0.8 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.24 0 45.38 0.485 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.12 0 12.26 0.485 ; + END + END chany_bottom_in[19] + PIN chany_bottom_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.32 0 44.46 0.485 ; + END + END chany_bottom_in[20] + PIN chany_bottom_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.4 0 66.54 0.485 ; + END + END chany_bottom_in[21] + PIN chany_bottom_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.12 0 35.26 0.485 ; + END + END chany_bottom_in[22] + PIN chany_bottom_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.44 0 8.58 0.485 ; + END + END chany_bottom_in[23] + PIN chany_bottom_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 21.47 0 21.77 0.8 ; + END + END chany_bottom_in[24] + PIN chany_bottom_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.48 0 65.62 0.485 ; + END + END chany_bottom_in[25] + PIN chany_bottom_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.4 0 43.54 0.485 ; + END + END chany_bottom_in[26] + PIN chany_bottom_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.88 0 61.02 0.485 ; + END + END chany_bottom_in[27] + PIN chany_bottom_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.28 0 56.42 0.485 ; + END + END chany_bottom_in[28] + PIN chany_bottom_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.2 0 57.34 0.485 ; + END + END chany_bottom_in[29] + PIN bottom_left_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.6 0 52.74 0.485 ; + END + END bottom_left_grid_pin_1_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 17.44 103.96 17.58 ; + END + END ccff_head[0] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 47.11 103.96 47.41 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 44.98 103.96 45.12 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 47.7 103.96 47.84 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 48.47 103.96 48.77 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 23.99 103.96 24.29 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 38.95 103.96 39.25 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 25.35 103.96 25.65 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 16.51 103.96 16.81 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 30.7 103.96 30.84 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 38.86 103.96 39 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 26.71 103.96 27.01 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 25.94 103.96 26.08 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 29 103.96 29.14 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 22.63 103.96 22.93 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 41.67 103.96 41.97 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 40.31 103.96 40.61 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 17.87 103.96 18.17 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 28.32 103.96 28.46 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 44.39 103.96 44.69 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 20.59 103.96 20.89 ; + END + END chanx_right_out[19] + PIN chanx_right_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 28.07 103.96 28.37 ; + END + END chanx_right_out[20] + PIN chanx_right_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 37.59 103.96 37.89 ; + END + END chanx_right_out[21] + PIN chanx_right_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 44.3 103.96 44.44 ; + END + END chanx_right_out[22] + PIN chanx_right_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 30.79 103.96 31.09 ; + END + END chanx_right_out[23] + PIN chanx_right_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 51.19 103.96 51.49 ; + END + END chanx_right_out[24] + PIN chanx_right_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 49.83 103.96 50.13 ; + END + END chanx_right_out[25] + PIN chanx_right_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 58.58 103.96 58.72 ; + END + END chanx_right_out[26] + PIN chanx_right_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 55.18 103.96 55.32 ; + END + END chanx_right_out[27] + PIN chanx_right_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 19.23 103.96 19.53 ; + END + END chanx_right_out[28] + PIN chanx_right_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 29.43 103.96 29.73 ; + END + END chanx_right_out[29] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.36 0 9.5 0.485 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.72 0 62.86 0.485 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.56 0 41.7 0.485 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.52 0 7.66 0.485 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 23.16 0 23.3 0.485 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.88 0 38.02 0.485 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.6 0 6.74 0.485 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.04 0 13.18 0.485 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 22.24 0 22.38 0.485 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.8 0 61.94 0.485 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.64 0 40.78 0.485 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 38.8 0 38.94 0.485 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.2 0 11.34 0.485 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 0 14.1 0.485 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.32 0 67.46 0.485 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 21.32 0 21.46 0.485 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.46 0 2.6 0.485 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.88 0 15.02 0.485 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.04 0 36.18 0.485 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 20.4 0 20.54 0.485 ; + END + END chany_bottom_out[19] + PIN chany_bottom_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.8 0 15.94 0.485 ; + END + END chany_bottom_out[20] + PIN chany_bottom_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.48 0 19.62 0.485 ; + END + END chany_bottom_out[21] + PIN chany_bottom_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.28 0 10.42 0.485 ; + END + END chany_bottom_out[22] + PIN chany_bottom_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.72 0 16.86 0.485 ; + END + END chany_bottom_out[23] + PIN chany_bottom_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 25 0 25.14 0.485 ; + END + END chany_bottom_out[24] + PIN chany_bottom_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.56 0 18.7 0.485 ; + END + END chany_bottom_out[25] + PIN chany_bottom_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 39.72 0 39.86 0.485 ; + END + END chany_bottom_out[26] + PIN chany_bottom_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.64 0 17.78 0.485 ; + END + END chany_bottom_out[27] + PIN chany_bottom_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 4.3 0 4.44 0.485 ; + END + END chany_bottom_out[28] + PIN chany_bottom_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.38 0 3.52 0.485 ; + END + END chany_bottom_out[29] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 24.08 0 24.22 0.485 ; + END + END ccff_tail[0] + PIN SC_IN_TOP + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.06 10.88 76.2 11.365 ; + END + END SC_IN_TOP + PIN SC_OUT_BOT + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 22.54 103.96 22.68 ; + END + END SC_OUT_BOT + PIN pReset_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 39.88 103.96 40.02 ; + END + END pReset_E_in + PIN pReset_S_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 28.68 0 28.82 0.485 ; + END + END pReset_S_out + PIN prog_clk_0_E_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met1 ; + RECT 103.365 25.26 103.96 25.4 ; + END + END prog_clk_0_E_in + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 26.96 3.2 30.16 ; + RECT 100.76 26.96 103.96 30.16 ; + RECT 0 67.76 3.2 70.96 ; + RECT 100.76 67.76 103.96 70.96 ; + LAYER met4 ; + RECT 14.42 0 15.02 0.6 ; + RECT 43.86 0 44.46 0.6 ; + RECT 89.86 10.88 90.46 11.48 ; + RECT 14.42 86.44 15.02 87.04 ; + RECT 43.86 86.44 44.46 87.04 ; + RECT 89.86 86.44 90.46 87.04 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 73.12 2.48 73.6 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 73.12 7.92 73.6 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 103.48 13.36 103.96 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 103.48 18.8 103.96 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 103.48 24.24 103.96 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 103.48 29.68 103.96 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 103.48 35.12 103.96 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 103.48 40.56 103.96 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 103.48 46 103.96 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 103.48 51.44 103.96 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 103.48 56.88 103.96 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 103.48 62.32 103.96 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 103.48 67.76 103.96 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 103.48 73.2 103.96 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 103.48 78.64 103.96 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 103.48 84.08 103.96 84.56 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 47.36 3.2 50.56 ; + RECT 100.76 47.36 103.96 50.56 ; + LAYER met4 ; + RECT 29.14 0 29.74 0.6 ; + RECT 58.58 0 59.18 0.6 ; + RECT 29.14 86.44 29.74 87.04 ; + RECT 58.58 86.44 59.18 87.04 ; + LAYER met1 ; + RECT 0 -0.24 0.48 0.24 ; + RECT 73.12 -0.24 73.6 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 73.12 5.2 73.6 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 103.48 10.64 103.96 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 103.48 16.08 103.96 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 103.48 21.52 103.96 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 103.48 26.96 103.96 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 103.48 32.4 103.96 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 103.48 37.84 103.96 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 103.48 43.28 103.96 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 103.48 48.72 103.96 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 103.48 54.16 103.96 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 103.48 59.6 103.96 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 103.48 65.04 103.96 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 103.48 70.48 103.96 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 103.48 75.92 103.96 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 103.48 81.36 103.96 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 103.48 86.8 103.96 87.28 ; + END + END VSS + OBS + LAYER met2 ; + RECT 58.74 86.735 59.02 87.105 ; + RECT 29.3 86.735 29.58 87.105 ; + POLYGON 35.72 26.25 35.72 0.24 35.76 0.24 35.76 0.1 35.58 0.1 35.58 26.25 ; + POLYGON 9.96 19.96 9.96 0.1 9.78 0.1 9.78 0.24 9.82 0.24 9.82 19.96 ; + POLYGON 52.28 17.24 52.28 0.24 52.32 0.24 52.32 0.1 52.14 0.1 52.14 17.24 ; + POLYGON 44.92 15.88 44.92 0.1 44.74 0.1 44.74 0.24 44.78 0.24 44.78 15.88 ; + POLYGON 80.8 12.14 80.8 11.405 80.87 11.405 80.87 11.035 80.59 11.035 80.59 11.405 80.66 11.405 80.66 12.14 ; + POLYGON 62.4 10.61 62.4 0.1 62.22 0.1 62.22 0.24 62.26 0.24 62.26 10.61 ; + RECT 53.92 0.69 54.18 1.01 ; + RECT 40.12 0.69 40.38 1.01 ; + RECT 34.6 0.69 34.86 1.01 ; + RECT 58.74 -0.065 59.02 0.305 ; + RECT 29.3 -0.065 29.58 0.305 ; + POLYGON 103.68 86.76 103.68 11.16 99.94 11.16 99.94 11.645 99.24 11.645 99.24 11.16 94.88 11.16 94.88 11.645 94.18 11.645 94.18 11.16 93.96 11.16 93.96 11.645 93.26 11.645 93.26 11.16 91.2 11.16 91.2 11.645 90.5 11.645 90.5 11.16 87.98 11.16 87.98 11.645 87.28 11.645 87.28 11.16 76.48 11.16 76.48 11.645 75.78 11.645 75.78 11.16 73.32 11.16 73.32 0.28 70.96 0.28 70.96 0.765 70.26 0.765 70.26 0.28 70.04 0.28 70.04 0.765 69.34 0.765 69.34 0.28 68.66 0.28 68.66 0.765 67.96 0.765 67.96 0.28 67.74 0.28 67.74 0.765 67.04 0.765 67.04 0.28 66.82 0.28 66.82 0.765 66.12 0.765 66.12 0.28 65.9 0.28 65.9 0.765 65.2 0.765 65.2 0.28 64.98 0.28 64.98 0.765 64.28 0.765 64.28 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 63.14 0.28 63.14 0.765 62.44 0.765 62.44 0.28 62.22 0.28 62.22 0.765 61.52 0.765 61.52 0.28 61.3 0.28 61.3 0.765 60.6 0.765 60.6 0.28 60.38 0.28 60.38 0.765 59.68 0.765 59.68 0.28 58.54 0.28 58.54 0.765 57.84 0.765 57.84 0.28 57.62 0.28 57.62 0.765 56.92 0.765 56.92 0.28 56.7 0.28 56.7 0.765 56 0.765 56 0.28 55.78 0.28 55.78 0.765 55.08 0.765 55.08 0.28 54.86 0.28 54.86 0.765 54.16 0.765 54.16 0.28 53.94 0.28 53.94 0.765 53.24 0.765 53.24 0.28 53.02 0.28 53.02 0.765 52.32 0.765 52.32 0.28 51.18 0.28 51.18 0.765 50.48 0.765 50.48 0.28 45.66 0.28 45.66 0.765 44.96 0.765 44.96 0.28 44.74 0.28 44.74 0.765 44.04 0.765 44.04 0.28 43.82 0.28 43.82 0.765 43.12 0.765 43.12 0.28 42.9 0.28 42.9 0.765 42.2 0.765 42.2 0.28 41.98 0.28 41.98 0.765 41.28 0.765 41.28 0.28 41.06 0.28 41.06 0.765 40.36 0.765 40.36 0.28 40.14 0.28 40.14 0.765 39.44 0.765 39.44 0.28 39.22 0.28 39.22 0.765 38.52 0.765 38.52 0.28 38.3 0.28 38.3 0.765 37.6 0.765 37.6 0.28 37.38 0.28 37.38 0.765 36.68 0.765 36.68 0.28 36.46 0.28 36.46 0.765 35.76 0.765 35.76 0.28 35.54 0.28 35.54 0.765 34.84 0.765 34.84 0.28 34.62 0.28 34.62 0.765 33.92 0.765 33.92 0.28 30.94 0.28 30.94 0.765 30.24 0.765 30.24 0.28 29.1 0.28 29.1 0.765 28.4 0.765 28.4 0.28 25.42 0.28 25.42 0.765 24.72 0.765 24.72 0.28 24.5 0.28 24.5 0.765 23.8 0.765 23.8 0.28 23.58 0.28 23.58 0.765 22.88 0.765 22.88 0.28 22.66 0.28 22.66 0.765 21.96 0.765 21.96 0.28 21.74 0.28 21.74 0.765 21.04 0.765 21.04 0.28 20.82 0.28 20.82 0.765 20.12 0.765 20.12 0.28 19.9 0.28 19.9 0.765 19.2 0.765 19.2 0.28 18.98 0.28 18.98 0.765 18.28 0.765 18.28 0.28 18.06 0.28 18.06 0.765 17.36 0.765 17.36 0.28 17.14 0.28 17.14 0.765 16.44 0.765 16.44 0.28 16.22 0.28 16.22 0.765 15.52 0.765 15.52 0.28 15.3 0.28 15.3 0.765 14.6 0.765 14.6 0.28 14.38 0.28 14.38 0.765 13.68 0.765 13.68 0.28 13.46 0.28 13.46 0.765 12.76 0.765 12.76 0.28 12.54 0.28 12.54 0.765 11.84 0.765 11.84 0.28 11.62 0.28 11.62 0.765 10.92 0.765 10.92 0.28 10.7 0.28 10.7 0.765 10 0.765 10 0.28 9.78 0.28 9.78 0.765 9.08 0.765 9.08 0.28 8.86 0.28 8.86 0.765 8.16 0.765 8.16 0.28 7.94 0.28 7.94 0.765 7.24 0.765 7.24 0.28 7.02 0.28 7.02 0.765 6.32 0.765 6.32 0.28 6.1 0.28 6.1 0.765 5.4 0.765 5.4 0.28 4.72 0.28 4.72 0.765 4.02 0.765 4.02 0.28 3.8 0.28 3.8 0.765 3.1 0.765 3.1 0.28 2.88 0.28 2.88 0.765 2.18 0.765 2.18 0.28 0.28 0.28 0.28 86.76 51.86 86.76 51.86 86.275 52.56 86.275 52.56 86.76 ; + LAYER met3 ; + POLYGON 59.045 87.085 59.045 87.08 59.26 87.08 59.26 86.76 59.045 86.76 59.045 86.755 58.715 86.755 58.715 86.76 58.5 86.76 58.5 87.08 58.715 87.08 58.715 87.085 ; + POLYGON 29.605 87.085 29.605 87.08 29.82 87.08 29.82 86.76 29.605 86.76 29.605 86.755 29.275 86.755 29.275 86.76 29.06 86.76 29.06 87.08 29.275 87.08 29.275 87.085 ; + POLYGON 103.31 33.13 103.31 32.85 102.76 32.85 102.76 32.83 101.74 32.83 101.74 33.13 ; + POLYGON 102.76 30.41 102.76 30.39 103.31 30.39 103.31 30.11 100.36 30.11 100.36 30.41 ; + POLYGON 80.895 11.385 80.895 11.055 80.565 11.055 80.565 11.07 64.48 11.07 64.48 11.37 80.565 11.37 80.565 11.385 ; + POLYGON 63.875 0.505 63.875 0.49 72.03 0.49 72.03 0.5 72.41 0.5 72.41 0.18 72.03 0.18 72.03 0.19 63.875 0.19 63.875 0.175 63.545 0.175 63.545 0.505 ; + POLYGON 59.045 0.285 59.045 0.28 59.26 0.28 59.26 -0.04 59.045 -0.04 59.045 -0.045 58.715 -0.045 58.715 -0.04 58.5 -0.04 58.5 0.28 58.715 0.28 58.715 0.285 ; + POLYGON 29.605 0.285 29.605 0.28 29.82 0.28 29.82 -0.04 29.605 -0.04 29.605 -0.045 29.275 -0.045 29.275 -0.04 29.06 -0.04 29.06 0.28 29.275 0.28 29.275 0.285 ; + POLYGON 103.56 86.64 103.56 57.33 102.76 57.33 102.76 56.23 103.56 56.23 103.56 55.97 102.76 55.97 102.76 54.87 103.56 54.87 103.56 54.61 102.76 54.61 102.76 53.51 103.56 53.51 103.56 53.25 102.76 53.25 102.76 52.15 103.56 52.15 103.56 51.89 102.76 51.89 102.76 50.79 103.56 50.79 103.56 50.53 102.76 50.53 102.76 49.43 103.56 49.43 103.56 49.17 102.76 49.17 102.76 48.07 103.56 48.07 103.56 47.81 102.76 47.81 102.76 46.71 103.56 46.71 103.56 46.45 102.76 46.45 102.76 45.35 103.56 45.35 103.56 45.09 102.76 45.09 102.76 43.99 103.56 43.99 103.56 43.73 102.76 43.73 102.76 42.63 103.56 42.63 103.56 42.37 102.76 42.37 102.76 41.27 103.56 41.27 103.56 41.01 102.76 41.01 102.76 39.91 103.56 39.91 103.56 39.65 102.76 39.65 102.76 38.55 103.56 38.55 103.56 38.29 102.76 38.29 102.76 37.19 103.56 37.19 103.56 36.93 102.76 36.93 102.76 35.83 103.56 35.83 103.56 35.57 102.76 35.57 102.76 34.47 103.56 34.47 103.56 34.21 102.76 34.21 102.76 33.11 103.56 33.11 103.56 32.85 102.76 32.85 102.76 31.75 103.56 31.75 103.56 31.49 102.76 31.49 102.76 30.39 103.56 30.39 103.56 30.13 102.76 30.13 102.76 29.03 103.56 29.03 103.56 28.77 102.76 28.77 102.76 27.67 103.56 27.67 103.56 27.41 102.76 27.41 102.76 26.31 103.56 26.31 103.56 26.05 102.76 26.05 102.76 24.95 103.56 24.95 103.56 24.69 102.76 24.69 102.76 23.59 103.56 23.59 103.56 23.33 102.76 23.33 102.76 22.23 103.56 22.23 103.56 21.29 102.76 21.29 102.76 20.19 103.56 20.19 103.56 19.93 102.76 19.93 102.76 18.83 103.56 18.83 103.56 18.57 102.76 18.57 102.76 17.47 103.56 17.47 103.56 17.21 102.76 17.21 102.76 16.11 103.56 16.11 103.56 11.28 73.2 11.28 73.2 0.4 0.4 0.4 0.4 86.64 ; + LAYER met1 ; + POLYGON 103.2 87.28 103.2 86.8 59.04 86.8 59.04 86.79 58.72 86.79 58.72 86.8 29.6 86.8 29.6 86.79 29.28 86.79 29.28 86.8 0.76 86.8 0.76 87.28 ; + POLYGON 103.435 48.52 103.435 48.12 103.295 48.12 103.295 48.38 94.46 48.38 94.46 48.52 ; + RECT 69.92 10.64 103.2 11.12 ; + POLYGON 59.04 0.25 59.04 0.24 72.84 0.24 72.84 -0.24 0.76 -0.24 0.76 0.24 29.28 0.24 29.28 0.25 29.6 0.25 29.6 0.24 58.72 0.24 58.72 0.25 ; + POLYGON 103.2 86.76 103.2 86.52 103.68 86.52 103.68 84.84 103.2 84.84 103.2 83.8 103.68 83.8 103.68 82.12 103.2 82.12 103.2 81.08 103.68 81.08 103.68 79.4 103.2 79.4 103.2 78.36 103.68 78.36 103.68 77.7 103.085 77.7 103.085 77 103.68 77 103.68 76.68 103.2 76.68 103.2 75.64 103.68 75.64 103.68 73.96 103.2 73.96 103.2 72.92 103.68 72.92 103.68 71.92 103.085 71.92 103.085 71.22 103.2 71.22 103.2 70.2 103.68 70.2 103.68 69.88 103.085 69.88 103.085 68.5 103.2 68.5 103.2 67.48 103.68 67.48 103.68 65.8 103.2 65.8 103.2 64.76 103.68 64.76 103.68 63.08 103.2 63.08 103.2 62.04 103.68 62.04 103.68 61.72 103.085 61.72 103.085 60.34 103.2 60.34 103.2 59.32 103.68 59.32 103.68 59 103.085 59 103.085 57.62 103.2 57.62 103.2 56.6 103.68 56.6 103.68 56.28 103.085 56.28 103.085 54.9 103.2 54.9 103.2 53.9 103.085 53.9 103.085 53.2 103.68 53.2 103.68 52.88 103.085 52.88 103.085 52.18 103.2 52.18 103.2 51.16 103.68 51.16 103.68 50.84 103.085 50.84 103.085 49.46 103.2 49.46 103.2 48.44 103.68 48.44 103.68 48.12 103.085 48.12 103.085 47.42 103.68 47.42 103.68 46.76 103.2 46.76 103.2 45.72 103.68 45.72 103.68 45.4 103.085 45.4 103.085 44.02 103.2 44.02 103.2 43 103.68 43 103.68 42.68 103.085 42.68 103.085 41.3 103.2 41.3 103.2 40.3 103.085 40.3 103.085 39.6 103.68 39.6 103.68 39.28 103.085 39.28 103.085 38.58 103.2 38.58 103.2 37.58 103.085 37.58 103.085 36.88 103.68 36.88 103.68 36.56 103.085 36.56 103.085 35.86 103.2 35.86 103.2 34.86 103.085 34.86 103.085 33.48 103.68 33.48 103.68 33.16 103.2 33.16 103.2 32.14 103.085 32.14 103.085 31.44 103.68 31.44 103.68 31.12 103.085 31.12 103.085 30.42 103.2 30.42 103.2 29.42 103.085 29.42 103.085 28.04 103.68 28.04 103.68 27.72 103.2 27.72 103.2 26.68 103.68 26.68 103.68 26.36 103.085 26.36 103.085 24.98 103.2 24.98 103.2 23.98 103.085 23.98 103.085 23.28 103.68 23.28 103.68 22.96 103.085 22.96 103.085 22.26 103.2 22.26 103.2 21.24 103.68 21.24 103.68 19.56 103.2 19.56 103.2 18.54 103.085 18.54 103.085 17.16 103.68 17.16 103.68 16.84 103.2 16.84 103.2 15.8 103.68 15.8 103.68 14.8 103.085 14.8 103.085 14.1 103.2 14.1 103.2 13.1 103.085 13.1 103.085 12.4 103.68 12.4 103.68 11.4 103.2 11.4 103.2 11.16 73.32 11.16 73.32 8.68 72.84 8.68 72.84 7.64 73.32 7.64 73.32 5.96 72.84 5.96 72.84 4.92 73.32 4.92 73.32 3.24 72.84 3.24 72.84 2.22 72.725 2.22 72.725 1.52 73.32 1.52 73.32 0.52 72.84 0.52 72.84 0.28 0.76 0.28 0.76 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 86.76 ; + LAYER met4 ; + POLYGON 73.29 58.97 73.29 8.35 72.37 8.35 72.37 0.505 72.385 0.505 72.385 0.175 72.055 0.175 72.055 0.505 72.07 0.505 72.07 8.65 72.99 8.65 72.99 58.97 ; + POLYGON 103.56 86.64 103.56 11.28 90.86 11.28 90.86 11.88 89.46 11.88 89.46 11.28 73.2 11.28 73.2 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 22.17 0.4 22.17 1.2 21.07 1.2 21.07 0.4 20.33 0.4 20.33 1.2 19.23 1.2 19.23 0.4 18.49 0.4 18.49 1.2 17.39 1.2 17.39 0.4 15.42 0.4 15.42 1 14.02 1 14.02 0.4 0.4 0.4 0.4 86.64 14.02 86.64 14.02 86.04 15.42 86.04 15.42 86.64 28.74 86.64 28.74 86.04 30.14 86.04 30.14 86.64 43.46 86.64 43.46 86.04 44.86 86.04 44.86 86.64 58.18 86.64 58.18 86.04 59.58 86.04 59.58 86.64 89.46 86.64 89.46 86.04 90.86 86.04 90.86 86.64 ; + LAYER met5 ; + POLYGON 102.36 85.44 102.36 72.56 99.16 72.56 99.16 66.16 102.36 66.16 102.36 52.16 99.16 52.16 99.16 45.76 102.36 45.76 102.36 31.76 99.16 31.76 99.16 25.36 102.36 25.36 102.36 12.48 72 12.48 72 1.6 1.6 1.6 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 85.44 ; + LAYER li1 ; + POLYGON 103.96 87.125 103.96 86.955 97.435 86.955 97.435 86.23 97.145 86.23 97.145 86.955 82.255 86.955 82.255 86.23 81.965 86.23 81.965 86.955 67.535 86.955 67.535 86.23 67.245 86.23 67.245 86.955 52.355 86.955 52.355 86.23 52.065 86.23 52.065 86.955 37.635 86.955 37.635 86.23 37.345 86.23 37.345 86.955 22.455 86.955 22.455 86.23 22.165 86.23 22.165 86.955 7.735 86.955 7.735 86.23 7.445 86.23 7.445 86.955 0 86.955 0 87.125 ; + RECT 103.04 84.235 103.96 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 103.04 81.515 103.96 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 103.04 78.795 103.96 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 103.04 76.075 103.96 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 103.04 73.355 103.96 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 103.04 70.635 103.96 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 103.5 67.915 103.96 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 103.04 65.195 103.96 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 103.04 62.475 103.96 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 103.04 59.755 103.96 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 103.04 57.035 103.96 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 103.04 54.315 103.96 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 103.04 51.595 103.96 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 103.04 48.875 103.96 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 103.04 46.155 103.96 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 103.04 43.435 103.96 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 103.04 40.715 103.96 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 103.04 37.995 103.96 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 103.04 35.275 103.96 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 103.04 32.555 103.96 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 103.04 29.835 103.96 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 103.04 27.115 103.96 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 103.04 24.395 103.96 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 103.04 21.675 103.96 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 103.04 18.955 103.96 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 103.04 16.235 103.96 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 103.04 13.515 103.96 13.685 ; + RECT 0 13.515 3.68 13.685 ; + POLYGON 86.57 11.785 86.57 10.965 87.535 10.965 87.535 11.425 87.84 11.425 87.84 10.965 88.51 10.965 88.51 11.425 88.68 11.425 88.68 10.965 89.35 10.965 89.35 11.425 89.52 11.425 89.52 10.965 90.19 10.965 90.19 11.425 90.36 11.425 90.36 10.965 91.03 10.965 91.03 11.425 91.285 11.425 91.285 10.965 91.975 10.965 91.975 11.445 92.145 11.445 92.145 10.965 92.815 10.965 92.815 11.445 92.985 11.445 92.985 10.965 93.575 10.965 93.575 11.445 93.905 11.445 93.905 10.965 94.415 10.965 94.415 11.445 94.745 11.445 94.745 10.965 95.255 10.965 95.255 11.765 95.585 11.765 95.585 10.965 97.145 10.965 97.145 11.69 97.435 11.69 97.435 10.965 103.96 10.965 103.96 10.795 69.92 10.795 69.92 10.965 74.495 10.965 74.495 11.445 74.665 11.445 74.665 10.965 75.335 10.965 75.335 11.445 75.505 11.445 75.505 10.965 76.095 10.965 76.095 11.445 76.425 11.445 76.425 10.965 76.935 10.965 76.935 11.445 77.265 11.445 77.265 10.965 77.775 10.965 77.775 11.765 78.105 11.765 78.105 10.965 80.82 10.965 80.82 11.785 81.05 11.785 81.05 10.965 81.965 10.965 81.965 11.69 82.255 11.69 82.255 10.965 84.5 10.965 84.5 11.785 84.73 11.785 84.73 10.965 86.34 10.965 86.34 11.785 ; + RECT 0 10.795 3.68 10.965 ; + RECT 69.92 8.075 73.6 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 72.68 5.355 73.6 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 72.68 2.635 73.6 2.805 ; + RECT 0 2.635 3.68 2.805 ; + POLYGON 14.225 0.885 14.225 0.085 14.735 0.085 14.735 0.565 15.065 0.565 15.065 0.085 15.575 0.085 15.575 0.565 15.905 0.565 15.905 0.085 16.495 0.085 16.495 0.565 16.665 0.565 16.665 0.085 17.335 0.085 17.335 0.565 17.505 0.565 17.505 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 26.275 0.085 26.275 0.465 26.605 0.465 26.605 0.085 27.305 0.085 27.305 0.445 27.635 0.445 27.635 0.085 30.235 0.085 30.235 0.545 30.565 0.545 30.565 0.085 32.465 0.085 32.465 0.525 32.655 0.525 32.655 0.085 34.14 0.085 34.14 0.545 34.445 0.545 34.445 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 43.295 0.085 43.295 0.465 43.625 0.465 43.625 0.085 44.325 0.085 44.325 0.445 44.655 0.445 44.655 0.085 47.255 0.085 47.255 0.545 47.585 0.545 47.585 0.085 49.485 0.085 49.485 0.525 49.675 0.525 49.675 0.085 51.16 0.085 51.16 0.545 51.465 0.545 51.465 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 56.945 0.085 56.945 0.62 57.455 0.62 57.455 0.085 59.415 0.085 59.415 0.485 59.745 0.485 59.745 0.085 61.245 0.085 61.245 0.465 61.575 0.465 61.575 0.085 63.535 0.085 63.535 0.485 63.865 0.485 63.865 0.085 65.825 0.085 65.825 0.62 66.335 0.62 66.335 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 73.6 0.085 73.6 -0.085 0 -0.085 0 0.085 3.315 0.085 3.315 0.885 3.645 0.885 3.645 0.085 4.155 0.085 4.155 0.565 4.485 0.565 4.485 0.085 4.995 0.085 4.995 0.565 5.325 0.565 5.325 0.085 5.915 0.085 5.915 0.565 6.085 0.565 6.085 0.085 6.755 0.085 6.755 0.565 6.925 0.565 6.925 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 13.895 0.085 13.895 0.885 ; + POLYGON 103.79 86.87 103.79 11.05 73.43 11.05 73.43 0.17 0.17 0.17 0.17 86.87 ; + LAYER via ; + RECT 58.805 86.845 58.955 86.995 ; + RECT 29.365 86.845 29.515 86.995 ; + RECT 36.955 0.435 37.105 0.585 ; + RECT 58.805 0.045 58.955 0.195 ; + RECT 29.365 0.045 29.515 0.195 ; + LAYER via2 ; + RECT 58.78 86.82 58.98 87.02 ; + RECT 29.34 86.82 29.54 87.02 ; + RECT 80.63 11.12 80.83 11.32 ; + RECT 63.61 0.24 63.81 0.44 ; + RECT 58.78 0.02 58.98 0.22 ; + RECT 29.34 0.02 29.54 0.22 ; + LAYER via3 ; + RECT 58.78 86.82 58.98 87.02 ; + RECT 29.34 86.82 29.54 87.02 ; + RECT 72.12 0.24 72.32 0.44 ; + RECT 58.78 0.02 58.98 0.22 ; + RECT 29.34 0.02 29.54 0.22 ; + LAYER OVERLAP ; + POLYGON 0 0 0 87.04 103.96 87.04 103.96 10.88 73.6 10.88 73.6 0 ; + END +END sb_0__2_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_1__0__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_1__0__icv_in_design.lef new file mode 100644 index 0000000..7bee5a0 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_1__0__icv_in_design.lef @@ -0,0 +1,2404 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_1__0_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 134.32 BY 87.04 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.54 86.555 70.68 87.04 ; + END + END pReset[0] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 98.75 86.24 99.05 87.04 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 87.71 86.24 88.01 87.04 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.68 86.555 51.82 87.04 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 95.99 86.24 96.29 87.04 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 70.23 86.24 70.53 87.04 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 61.03 86.24 61.33 87.04 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 84.03 86.24 84.33 87.04 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 87.56 86.555 87.7 87.04 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 92.31 86.24 92.61 87.04 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.8 86.555 84.94 87.04 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 85.72 86.555 85.86 87.04 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.04 86.555 82.18 87.04 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 66.55 86.24 66.85 87.04 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 82.19 86.24 82.49 87.04 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 90.47 86.24 90.77 87.04 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 80.35 86.24 80.65 87.04 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 99.52 86.555 99.66 87.04 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.94 86.555 66.08 87.04 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94.92 86.555 95.06 87.04 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 78.51 86.24 78.81 87.04 ; + END + END chany_top_in[19] + PIN chany_top_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 68.39 86.24 68.69 87.04 ; + END + END chany_top_in[20] + PIN chany_top_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 62.87 86.24 63.17 87.04 ; + END + END chany_top_in[21] + PIN chany_top_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 100.44 86.555 100.58 87.04 ; + END + END chany_top_in[22] + PIN chany_top_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.44 86.555 77.58 87.04 ; + END + END chany_top_in[23] + PIN chany_top_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 76.67 86.24 76.97 87.04 ; + END + END chany_top_in[24] + PIN chany_top_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 64.71 86.24 65.01 87.04 ; + END + END chany_top_in[25] + PIN chany_top_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 94.15 86.24 94.45 87.04 ; + END + END chany_top_in[26] + PIN chany_top_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94 86.555 94.14 87.04 ; + END + END chany_top_in[27] + PIN chany_top_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 85.87 86.24 86.17 87.04 ; + END + END chany_top_in[28] + PIN chany_top_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 89.86 86.555 90 87.04 ; + END + END chany_top_in[29] + PIN top_left_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.66 75.675 11.8 76.16 ; + END + END top_left_grid_pin_44_[0] + PIN top_left_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 75.675 14.1 76.16 ; + END + END top_left_grid_pin_45_[0] + PIN top_left_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.84 75.675 3.98 76.16 ; + END + END top_left_grid_pin_46_[0] + PIN top_left_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.82 75.675 9.96 76.16 ; + END + END top_left_grid_pin_47_[0] + PIN top_left_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.94 75.675 20.08 76.16 ; + END + END top_left_grid_pin_48_[0] + PIN top_left_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.56 75.675 18.7 76.16 ; + END + END top_left_grid_pin_49_[0] + PIN top_left_grid_pin_50_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.72 75.675 16.86 76.16 ; + END + END top_left_grid_pin_50_[0] + PIN top_left_grid_pin_51_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.64 75.675 17.78 76.16 ; + END + END top_left_grid_pin_51_[0] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 23.56 134.32 23.7 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 21.27 134.32 21.57 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 31.04 134.32 31.18 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 36.48 134.32 36.62 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 22.63 134.32 22.93 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 25.6 134.32 25.74 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 17.1 134.32 17.24 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 29 134.32 29.14 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 38.95 134.32 39.25 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 71.5 134.32 71.64 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 66.4 134.32 66.54 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 37.16 134.32 37.3 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 12.68 134.32 12.82 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 57.9 134.32 58.04 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 34.44 134.32 34.58 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 31.72 134.32 31.86 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 33.76 134.32 33.9 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 22.88 134.32 23.02 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 20.16 134.32 20.3 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 27.98 134.32 28.12 ; + END + END chanx_right_in[19] + PIN chanx_right_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 63.34 134.32 63.48 ; + END + END chanx_right_in[20] + PIN chanx_right_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 47.11 134.32 47.41 ; + END + END chanx_right_in[21] + PIN chanx_right_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 54.59 134.32 54.89 ; + END + END chanx_right_in[22] + PIN chanx_right_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 15.4 134.32 15.54 ; + END + END chanx_right_in[23] + PIN chanx_right_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 20.84 134.32 20.98 ; + END + END chanx_right_in[24] + PIN chanx_right_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 72.18 134.32 72.32 ; + END + END chanx_right_in[25] + PIN chanx_right_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 61.3 134.32 61.44 ; + END + END chanx_right_in[26] + PIN chanx_right_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 26.28 134.32 26.42 ; + END + END chanx_right_in[27] + PIN chanx_right_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 44.3 134.32 44.44 ; + END + END chanx_right_in[28] + PIN chanx_right_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 67.08 134.32 67.22 ; + END + END chanx_right_in[29] + PIN right_bottom_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 3.84 134.32 3.98 ; + END + END right_bottom_grid_pin_1_[0] + PIN right_bottom_grid_pin_3_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 9.28 134.32 9.42 ; + END + END right_bottom_grid_pin_3_[0] + PIN right_bottom_grid_pin_5_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 5.63 134.32 5.93 ; + END + END right_bottom_grid_pin_5_[0] + PIN right_bottom_grid_pin_7_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 6.56 134.32 6.7 ; + END + END right_bottom_grid_pin_7_[0] + PIN right_bottom_grid_pin_9_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 6.99 134.32 7.29 ; + END + END right_bottom_grid_pin_9_[0] + PIN right_bottom_grid_pin_11_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 7.24 134.32 7.38 ; + END + END right_bottom_grid_pin_11_[0] + PIN right_bottom_grid_pin_13_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 1.8 134.32 1.94 ; + END + END right_bottom_grid_pin_13_[0] + PIN right_bottom_grid_pin_15_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 14.72 134.32 14.86 ; + END + END right_bottom_grid_pin_15_[0] + PIN right_bottom_grid_pin_17_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 4.52 134.32 4.66 ; + END + END right_bottom_grid_pin_17_[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 20.84 0.595 20.98 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.72 0.595 31.86 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 63.68 0.595 63.82 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 29 0.595 29.14 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 42.6 0.595 42.74 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 12 0.595 12.14 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 30.79 0.8 31.09 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 37.59 0.8 37.89 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 32.15 0.8 32.45 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 61.64 0.595 61.78 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 38.95 0.8 39.25 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 41.67 0.8 41.97 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.51 0.8 33.81 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 58.58 0.595 58.72 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 69.46 0.595 69.6 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 66.15 0.8 66.45 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 71.5 0.595 71.64 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 72.18 0.595 72.32 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.23 0.8 36.53 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 53.14 0.595 53.28 ; + END + END chanx_left_in[19] + PIN chanx_left_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 34.87 0.8 35.17 ; + END + END chanx_left_in[20] + PIN chanx_left_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 60.96 0.595 61.1 ; + END + END chanx_left_in[21] + PIN chanx_left_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.31 0.8 40.61 ; + END + END chanx_left_in[22] + PIN chanx_left_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 34.44 0.595 34.58 ; + END + END chanx_left_in[23] + PIN chanx_left_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 26.28 0.595 26.42 ; + END + END chanx_left_in[24] + PIN chanx_left_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 67.51 0.8 67.81 ; + END + END chanx_left_in[25] + PIN chanx_left_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 22.88 0.595 23.02 ; + END + END chanx_left_in[26] + PIN chanx_left_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 49.74 0.595 49.88 ; + END + END chanx_left_in[27] + PIN chanx_left_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 68.78 0.595 68.92 ; + END + END chanx_left_in[28] + PIN chanx_left_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 67.08 0.595 67.22 ; + END + END chanx_left_in[29] + PIN left_bottom_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 4.52 0.595 4.66 ; + END + END left_bottom_grid_pin_1_[0] + PIN left_bottom_grid_pin_3_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 15.4 0.595 15.54 ; + END + END left_bottom_grid_pin_3_[0] + PIN left_bottom_grid_pin_5_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 3.84 0.595 3.98 ; + END + END left_bottom_grid_pin_5_[0] + PIN left_bottom_grid_pin_7_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 6.56 0.595 6.7 ; + END + END left_bottom_grid_pin_7_[0] + PIN left_bottom_grid_pin_9_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 8.94 0.595 9.08 ; + END + END left_bottom_grid_pin_9_[0] + PIN left_bottom_grid_pin_11_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 17.44 0.595 17.58 ; + END + END left_bottom_grid_pin_11_[0] + PIN left_bottom_grid_pin_13_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 7.24 0.595 7.38 ; + END + END left_bottom_grid_pin_13_[0] + PIN left_bottom_grid_pin_15_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 14.72 0.595 14.86 ; + END + END left_bottom_grid_pin_15_[0] + PIN left_bottom_grid_pin_17_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 12.68 0.595 12.82 ; + END + END left_bottom_grid_pin_17_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 11.66 134.32 11.8 ; + END + END ccff_head[0] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.12 86.555 81.26 87.04 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.2 86.555 80.34 87.04 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.48 86.555 42.62 87.04 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.64 86.555 86.78 87.04 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.92 86.555 72.06 87.04 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.1 86.555 41.24 87.04 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.88 86.555 84.02 87.04 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.3 86.555 73.44 87.04 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.6 86.555 75.74 87.04 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.18 86.555 63.32 87.04 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.8 86.555 61.94 87.04 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.92 86.555 49.06 87.04 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.7 86.555 68.84 87.04 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.36 86.555 78.5 87.04 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.32 86.555 44.46 87.04 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 101.36 86.555 101.5 87.04 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.28 86.555 79.42 87.04 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.62 86.555 46.76 87.04 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.86 86.555 67 87.04 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 72.07 86.24 72.37 87.04 ; + END + END chany_top_out[19] + PIN chany_top_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48 86.555 48.14 87.04 ; + END + END chany_top_out[20] + PIN chany_top_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.08 86.555 93.22 87.04 ; + END + END chany_top_out[21] + PIN chany_top_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.88 86.555 61.02 87.04 ; + END + END chany_top_out[22] + PIN chany_top_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.88 86.555 38.02 87.04 ; + END + END chany_top_out[23] + PIN chany_top_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.52 86.555 76.66 87.04 ; + END + END chany_top_out[24] + PIN chany_top_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.78 86.555 67.92 87.04 ; + END + END chany_top_out[25] + PIN chany_top_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 86.555 37.1 87.04 ; + END + END chany_top_out[26] + PIN chany_top_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.02 86.555 65.16 87.04 ; + END + END chany_top_out[27] + PIN chany_top_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.62 86.555 69.76 87.04 ; + END + END chany_top_out[28] + PIN chany_top_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.1 86.555 64.24 87.04 ; + END + END chany_top_out[29] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 23.99 134.32 24.29 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 48.04 134.32 48.18 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 53.48 134.32 53.62 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 43.03 134.32 43.33 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 39.88 134.32 40.02 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 44.39 134.32 44.69 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 41.67 134.32 41.97 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 42.26 134.32 42.4 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 48.47 134.32 48.77 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 50.08 134.32 50.22 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 66.15 134.32 66.45 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 37.59 134.32 37.89 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 74.22 134.32 74.36 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 41.58 134.32 41.72 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 60.62 134.32 60.76 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 52.46 134.32 52.6 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 69.46 134.32 69.6 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 64.36 134.32 64.5 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 49.83 134.32 50.13 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 44.98 134.32 45.12 ; + END + END chanx_right_out[19] + PIN chanx_right_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 55.18 134.32 55.32 ; + END + END chanx_right_out[20] + PIN chanx_right_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 68.78 134.32 68.92 ; + END + END chanx_right_out[21] + PIN chanx_right_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 67.51 134.32 67.81 ; + END + END chanx_right_out[22] + PIN chanx_right_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 50.76 134.32 50.9 ; + END + END chanx_right_out[23] + PIN chanx_right_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 52.55 134.32 52.85 ; + END + END chanx_right_out[24] + PIN chanx_right_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 38.86 134.32 39 ; + END + END chanx_right_out[25] + PIN chanx_right_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 45.75 134.32 46.05 ; + END + END chanx_right_out[26] + PIN chanx_right_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 47.02 134.32 47.16 ; + END + END chanx_right_out[27] + PIN chanx_right_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 40.31 134.32 40.61 ; + END + END chanx_right_out[28] + PIN chanx_right_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 58.92 134.32 59.06 ; + END + END chanx_right_out[29] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 1.8 0.595 1.94 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 37.16 0.595 37.3 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 50.51 0.8 50.81 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 39.2 0.595 39.34 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.04 0.595 31.18 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.11 0.8 47.41 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.03 0.8 43.33 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 45.75 0.8 46.05 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 49.15 0.8 49.45 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 47.02 0.595 47.16 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 56.2 0.595 56.34 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 45.32 0.595 45.46 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 52.46 0.595 52.6 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 41.92 0.595 42.06 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.48 0.595 36.62 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 47.7 0.595 47.84 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 64.36 0.595 64.5 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 66.4 0.595 66.54 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 22.63 0.8 22.93 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 50.42 0.595 50.56 ; + END + END chanx_left_out[19] + PIN chanx_left_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 25.6 0.595 25.74 ; + END + END chanx_left_out[20] + PIN chanx_left_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 57.9 0.595 58.04 ; + END + END chanx_left_out[21] + PIN chanx_left_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.39 0.8 44.69 ; + END + END chanx_left_out[22] + PIN chanx_left_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.64 0.595 44.78 ; + END + END chanx_left_out[23] + PIN chanx_left_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 39.88 0.595 40.02 ; + END + END chanx_left_out[24] + PIN chanx_left_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 23.56 0.595 23.7 ; + END + END chanx_left_out[25] + PIN chanx_left_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 23.99 0.8 24.29 ; + END + END chanx_left_out[26] + PIN chanx_left_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 27.98 0.595 28.12 ; + END + END chanx_left_out[27] + PIN chanx_left_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 33.42 0.595 33.56 ; + END + END chanx_left_out[28] + PIN chanx_left_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 55.52 0.595 55.66 ; + END + END chanx_left_out[29] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 18.12 0.595 18.26 ; + END + END ccff_tail[0] + PIN SC_IN_TOP + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.46 75.675 2.6 76.16 ; + END + END SC_IN_TOP + PIN SC_OUT_TOP + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 131.72 75.675 131.86 76.16 ; + END + END SC_OUT_TOP + PIN Test_en_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.06 0 76.2 0.485 ; + END + END Test_en_S_in + PIN Test_en_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.96 86.555 83.1 87.04 ; + END + END Test_en_N_out + PIN pReset_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.2 0 57.34 0.485 ; + END + END pReset_S_in + PIN pReset_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 9.96 134.32 10.1 ; + END + END pReset_E_in + PIN pReset_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 19.82 0.595 19.96 ; + END + END pReset_W_in + PIN pReset_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.66 86.555 34.8 87.04 ; + END + END pReset_N_out + PIN pReset_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 9.62 0.595 9.76 ; + END + END pReset_W_out + PIN pReset_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 17.78 134.32 17.92 ; + END + END pReset_E_out + PIN Reset_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.68 0 74.82 0.485 ; + END + END Reset_S_in + PIN Reset_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.68 86.555 74.82 87.04 ; + END + END Reset_N_out + PIN prog_clk_0_N_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 33.74 86.555 33.88 87.04 ; + END + END prog_clk_0_N_in + PIN prog_clk_3_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.08 0 70.22 0.485 ; + END + END prog_clk_3_S_in + PIN prog_clk_3_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 90.78 86.555 90.92 87.04 ; + END + END prog_clk_3_N_out + PIN clk_3_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.76 0 73.9 0.485 ; + END + END clk_3_S_in + PIN clk_3_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 98.6 86.555 98.74 87.04 ; + END + END clk_3_N_out + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 16.08 3.2 19.28 ; + RECT 131.12 16.08 134.32 19.28 ; + RECT 0 56.88 3.2 60.08 ; + RECT 131.12 56.88 134.32 60.08 ; + LAYER met4 ; + RECT 13.5 0 14.1 0.6 ; + RECT 44.78 0 45.38 0.6 ; + RECT 74.22 0 74.82 0.6 ; + RECT 120.22 0 120.82 0.6 ; + RECT 13.5 75.56 14.1 76.16 ; + RECT 120.22 75.56 120.82 76.16 ; + RECT 44.78 86.44 45.38 87.04 ; + RECT 74.22 86.44 74.82 87.04 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 133.84 2.48 134.32 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 133.84 7.92 134.32 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 133.84 13.36 134.32 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 133.84 18.8 134.32 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 133.84 24.24 134.32 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 133.84 29.68 134.32 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 133.84 35.12 134.32 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 133.84 40.56 134.32 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 133.84 46 134.32 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 133.84 51.44 134.32 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 133.84 56.88 134.32 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 133.84 62.32 134.32 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 133.84 67.76 134.32 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 133.84 73.2 134.32 73.68 ; + RECT 30.36 78.64 30.84 79.12 ; + RECT 103.48 78.64 103.96 79.12 ; + RECT 30.36 84.08 30.84 84.56 ; + RECT 103.48 84.08 103.96 84.56 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 36.48 3.2 39.68 ; + RECT 131.12 36.48 134.32 39.68 ; + LAYER met4 ; + RECT 59.5 0 60.1 0.6 ; + RECT 88.94 0 89.54 0.6 ; + RECT 59.5 86.44 60.1 87.04 ; + RECT 88.94 86.44 89.54 87.04 ; + LAYER met1 ; + RECT 0 -0.24 0.48 0.24 ; + RECT 133.84 -0.24 134.32 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 133.84 5.2 134.32 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 133.84 10.64 134.32 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 133.84 16.08 134.32 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 133.84 21.52 134.32 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 133.84 26.96 134.32 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 133.84 32.4 134.32 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 133.84 37.84 134.32 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 133.84 43.28 134.32 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 133.84 48.72 134.32 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 133.84 54.16 134.32 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 133.84 59.6 134.32 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 133.84 65.04 134.32 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 133.84 70.48 134.32 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 133.84 75.92 134.32 76.4 ; + RECT 30.36 81.36 30.84 81.84 ; + RECT 103.48 81.36 103.96 81.84 ; + RECT 30.36 86.8 30.84 87.28 ; + RECT 103.48 86.8 103.96 87.28 ; + END + END VSS + OBS + LAYER met2 ; + RECT 89.1 86.735 89.38 87.105 ; + RECT 59.66 86.735 59.94 87.105 ; + POLYGON 75.28 86.94 75.28 80.68 75.14 80.68 75.14 86.8 75.1 86.8 75.1 86.94 ; + POLYGON 64.74 86.94 64.74 86.8 64.7 86.8 64.7 83.23 64.56 83.23 64.56 86.94 ; + RECT 79.68 86.03 79.94 86.35 ; + RECT 72.32 86.03 72.58 86.35 ; + RECT 48.4 86.03 48.66 86.35 ; + RECT 29.53 75.635 29.81 76.005 ; + POLYGON 6.81 76.005 6.81 75.635 6.74 75.635 6.74 72.18 6.6 72.18 6.6 75.635 6.53 75.635 6.53 76.005 ; + POLYGON 75.28 4.32 75.28 0.1 75.1 0.1 75.1 0.24 75.14 0.24 75.14 4.32 ; + RECT 89.1 -0.065 89.38 0.305 ; + RECT 59.66 -0.065 59.94 0.305 ; + POLYGON 103.68 86.76 103.68 75.88 131.44 75.88 131.44 75.395 132.14 75.395 132.14 75.88 134.04 75.88 134.04 0.28 76.48 0.28 76.48 0.765 75.78 0.765 75.78 0.28 75.1 0.28 75.1 0.765 74.4 0.765 74.4 0.28 74.18 0.28 74.18 0.765 73.48 0.765 73.48 0.28 70.5 0.28 70.5 0.765 69.8 0.765 69.8 0.28 57.62 0.28 57.62 0.765 56.92 0.765 56.92 0.28 0.28 0.28 0.28 75.88 2.18 75.88 2.18 75.395 2.88 75.395 2.88 75.88 3.56 75.88 3.56 75.395 4.26 75.395 4.26 75.88 9.54 75.88 9.54 75.395 10.24 75.395 10.24 75.88 11.38 75.88 11.38 75.395 12.08 75.395 12.08 75.88 13.68 75.88 13.68 75.395 14.38 75.395 14.38 75.88 16.44 75.88 16.44 75.395 17.14 75.395 17.14 75.88 17.36 75.88 17.36 75.395 18.06 75.395 18.06 75.88 18.28 75.88 18.28 75.395 18.98 75.395 18.98 75.88 19.66 75.88 19.66 75.395 20.36 75.395 20.36 75.88 30.64 75.88 30.64 86.76 33.46 86.76 33.46 86.275 34.16 86.275 34.16 86.76 34.38 86.76 34.38 86.275 35.08 86.275 35.08 86.76 36.68 86.76 36.68 86.275 37.38 86.275 37.38 86.76 37.6 86.76 37.6 86.275 38.3 86.275 38.3 86.76 40.82 86.76 40.82 86.275 41.52 86.275 41.52 86.76 42.2 86.76 42.2 86.275 42.9 86.275 42.9 86.76 44.04 86.76 44.04 86.275 44.74 86.275 44.74 86.76 46.34 86.76 46.34 86.275 47.04 86.275 47.04 86.76 47.72 86.76 47.72 86.275 48.42 86.275 48.42 86.76 48.64 86.76 48.64 86.275 49.34 86.275 49.34 86.76 51.4 86.76 51.4 86.275 52.1 86.275 52.1 86.76 60.6 86.76 60.6 86.275 61.3 86.275 61.3 86.76 61.52 86.76 61.52 86.275 62.22 86.275 62.22 86.76 62.9 86.76 62.9 86.275 63.6 86.275 63.6 86.76 63.82 86.76 63.82 86.275 64.52 86.275 64.52 86.76 64.74 86.76 64.74 86.275 65.44 86.275 65.44 86.76 65.66 86.76 65.66 86.275 66.36 86.275 66.36 86.76 66.58 86.76 66.58 86.275 67.28 86.275 67.28 86.76 67.5 86.76 67.5 86.275 68.2 86.275 68.2 86.76 68.42 86.76 68.42 86.275 69.12 86.275 69.12 86.76 69.34 86.76 69.34 86.275 70.04 86.275 70.04 86.76 70.26 86.76 70.26 86.275 70.96 86.275 70.96 86.76 71.64 86.76 71.64 86.275 72.34 86.275 72.34 86.76 73.02 86.76 73.02 86.275 73.72 86.275 73.72 86.76 74.4 86.76 74.4 86.275 75.1 86.275 75.1 86.76 75.32 86.76 75.32 86.275 76.02 86.275 76.02 86.76 76.24 86.76 76.24 86.275 76.94 86.275 76.94 86.76 77.16 86.76 77.16 86.275 77.86 86.275 77.86 86.76 78.08 86.76 78.08 86.275 78.78 86.275 78.78 86.76 79 86.76 79 86.275 79.7 86.275 79.7 86.76 79.92 86.76 79.92 86.275 80.62 86.275 80.62 86.76 80.84 86.76 80.84 86.275 81.54 86.275 81.54 86.76 81.76 86.76 81.76 86.275 82.46 86.275 82.46 86.76 82.68 86.76 82.68 86.275 83.38 86.275 83.38 86.76 83.6 86.76 83.6 86.275 84.3 86.275 84.3 86.76 84.52 86.76 84.52 86.275 85.22 86.275 85.22 86.76 85.44 86.76 85.44 86.275 86.14 86.275 86.14 86.76 86.36 86.76 86.36 86.275 87.06 86.275 87.06 86.76 87.28 86.76 87.28 86.275 87.98 86.275 87.98 86.76 89.58 86.76 89.58 86.275 90.28 86.275 90.28 86.76 90.5 86.76 90.5 86.275 91.2 86.275 91.2 86.76 92.8 86.76 92.8 86.275 93.5 86.275 93.5 86.76 93.72 86.76 93.72 86.275 94.42 86.275 94.42 86.76 94.64 86.76 94.64 86.275 95.34 86.275 95.34 86.76 98.32 86.76 98.32 86.275 99.02 86.275 99.02 86.76 99.24 86.76 99.24 86.275 99.94 86.275 99.94 86.76 100.16 86.76 100.16 86.275 100.86 86.275 100.86 86.76 101.08 86.76 101.08 86.275 101.78 86.275 101.78 86.76 ; + LAYER met4 ; + POLYGON 83.41 86.85 83.41 15.32 83.11 15.32 83.11 86.55 82.89 86.55 82.89 86.85 ; + POLYGON 30.985 75.985 30.985 75.655 30.97 75.655 30.97 52.55 30.67 52.55 30.67 75.655 30.655 75.655 30.655 75.985 ; + POLYGON 103.56 86.64 103.56 75.76 119.82 75.76 119.82 75.16 121.22 75.16 121.22 75.76 133.92 75.76 133.92 0.4 121.22 0.4 121.22 1 119.82 1 119.82 0.4 89.94 0.4 89.94 1 88.54 1 88.54 0.4 75.22 0.4 75.22 1 73.82 1 73.82 0.4 60.5 0.4 60.5 1 59.1 1 59.1 0.4 45.78 0.4 45.78 1 44.38 1 44.38 0.4 14.5 0.4 14.5 1 13.1 1 13.1 0.4 0.4 0.4 0.4 75.76 13.1 75.76 13.1 75.16 14.5 75.16 14.5 75.76 30.76 75.76 30.76 86.64 44.38 86.64 44.38 86.04 45.78 86.04 45.78 86.64 59.1 86.64 59.1 86.04 60.5 86.04 60.5 86.64 60.63 86.64 60.63 85.84 61.73 85.84 61.73 86.64 62.47 86.64 62.47 85.84 63.57 85.84 63.57 86.64 64.31 86.64 64.31 85.84 65.41 85.84 65.41 86.64 66.15 86.64 66.15 85.84 67.25 85.84 67.25 86.64 67.99 86.64 67.99 85.84 69.09 85.84 69.09 86.64 69.83 86.64 69.83 85.84 70.93 85.84 70.93 86.64 71.67 86.64 71.67 85.84 72.77 85.84 72.77 86.64 73.82 86.64 73.82 86.04 75.22 86.04 75.22 86.64 76.27 86.64 76.27 85.84 77.37 85.84 77.37 86.64 78.11 86.64 78.11 85.84 79.21 85.84 79.21 86.64 79.95 86.64 79.95 85.84 81.05 85.84 81.05 86.64 81.79 86.64 81.79 85.84 82.89 85.84 82.89 86.64 83.63 86.64 83.63 85.84 84.73 85.84 84.73 86.64 85.47 86.64 85.47 85.84 86.57 85.84 86.57 86.64 87.31 86.64 87.31 85.84 88.41 85.84 88.41 86.64 88.54 86.64 88.54 86.04 89.94 86.04 89.94 86.64 90.07 86.64 90.07 85.84 91.17 85.84 91.17 86.64 91.91 86.64 91.91 85.84 93.01 85.84 93.01 86.64 93.75 86.64 93.75 85.84 94.85 85.84 94.85 86.64 95.59 86.64 95.59 85.84 96.69 85.84 96.69 86.64 98.35 86.64 98.35 85.84 99.45 85.84 99.45 86.64 ; + LAYER met1 ; + POLYGON 103.2 87.28 103.2 86.8 89.4 86.8 89.4 86.79 89.08 86.79 89.08 86.8 59.96 86.8 59.96 86.79 59.64 86.79 59.64 86.8 31.12 86.8 31.12 87.28 ; + RECT 72.36 75.92 133.56 76.4 ; + RECT 0.76 75.92 71.16 76.4 ; + POLYGON 133.795 43.08 133.795 42.68 133.655 42.68 133.655 42.94 130.34 42.94 130.34 43.08 ; + POLYGON 0.665 11.72 0.665 11.46 9.04 11.46 9.04 11.32 0.525 11.32 0.525 11.72 ; + POLYGON 89.4 0.25 89.4 0.24 133.56 0.24 133.56 -0.24 0.76 -0.24 0.76 0.24 59.64 0.24 59.64 0.25 59.96 0.25 59.96 0.24 89.08 0.24 89.08 0.25 ; + POLYGON 103.2 86.76 103.2 86.52 103.68 86.52 103.68 84.84 103.2 84.84 103.2 83.8 103.68 83.8 103.68 82.12 103.2 82.12 103.2 81.08 103.68 81.08 103.68 79.4 103.2 79.4 103.2 78.36 103.68 78.36 103.68 75.88 133.56 75.88 133.56 75.64 134.04 75.64 134.04 74.64 133.445 74.64 133.445 73.94 133.56 73.94 133.56 72.92 134.04 72.92 134.04 72.6 133.445 72.6 133.445 71.22 133.56 71.22 133.56 70.2 134.04 70.2 134.04 69.88 133.445 69.88 133.445 68.5 133.56 68.5 133.56 67.5 133.445 67.5 133.445 66.12 134.04 66.12 134.04 65.8 133.56 65.8 133.56 64.78 133.445 64.78 133.445 64.08 134.04 64.08 134.04 63.76 133.445 63.76 133.445 63.06 133.56 63.06 133.56 62.04 134.04 62.04 134.04 61.72 133.445 61.72 133.445 60.34 133.56 60.34 133.56 59.34 133.445 59.34 133.445 58.64 134.04 58.64 134.04 58.32 133.445 58.32 133.445 57.62 133.56 57.62 133.56 56.6 134.04 56.6 134.04 55.6 133.445 55.6 133.445 54.9 133.56 54.9 133.56 53.9 133.445 53.9 133.445 53.2 134.04 53.2 134.04 52.88 133.445 52.88 133.445 52.18 133.56 52.18 133.56 51.18 133.445 51.18 133.445 49.8 134.04 49.8 134.04 49.48 133.56 49.48 133.56 48.46 133.445 48.46 133.445 47.76 134.04 47.76 134.04 47.44 133.445 47.44 133.445 46.74 133.56 46.74 133.56 45.72 134.04 45.72 134.04 45.4 133.445 45.4 133.445 44.02 133.56 44.02 133.56 43 134.04 43 134.04 42.68 133.445 42.68 133.445 41.3 133.56 41.3 133.56 40.3 133.445 40.3 133.445 39.6 134.04 39.6 134.04 39.28 133.445 39.28 133.445 38.58 133.56 38.58 133.56 37.58 133.445 37.58 133.445 36.2 134.04 36.2 134.04 35.88 133.56 35.88 133.56 34.86 133.445 34.86 133.445 33.48 134.04 33.48 134.04 33.16 133.56 33.16 133.56 32.14 133.445 32.14 133.445 30.76 134.04 30.76 134.04 30.44 133.56 30.44 133.56 29.42 133.445 29.42 133.445 28.72 134.04 28.72 134.04 28.4 133.445 28.4 133.445 27.7 133.56 27.7 133.56 26.7 133.445 26.7 133.445 25.32 134.04 25.32 134.04 25 133.56 25 133.56 23.98 133.445 23.98 133.445 22.6 134.04 22.6 134.04 22.28 133.56 22.28 133.56 21.26 133.445 21.26 133.445 19.88 134.04 19.88 134.04 19.56 133.56 19.56 133.56 18.52 134.04 18.52 134.04 18.2 133.445 18.2 133.445 16.82 133.56 16.82 133.56 15.82 133.445 15.82 133.445 14.44 134.04 14.44 134.04 14.12 133.56 14.12 133.56 13.1 133.445 13.1 133.445 12.4 134.04 12.4 134.04 12.08 133.445 12.08 133.445 11.38 133.56 11.38 133.56 10.38 133.445 10.38 133.445 9 134.04 9 134.04 8.68 133.56 8.68 133.56 7.66 133.445 7.66 133.445 6.28 134.04 6.28 134.04 5.96 133.56 5.96 133.56 4.94 133.445 4.94 133.445 3.56 134.04 3.56 134.04 3.24 133.56 3.24 133.56 2.22 133.445 2.22 133.445 1.52 134.04 1.52 134.04 0.52 133.56 0.52 133.56 0.28 0.76 0.28 0.76 0.52 0.28 0.52 0.28 1.52 0.875 1.52 0.875 2.22 0.76 2.22 0.76 3.24 0.28 3.24 0.28 3.56 0.875 3.56 0.875 4.94 0.76 4.94 0.76 5.96 0.28 5.96 0.28 6.28 0.875 6.28 0.875 7.66 0.76 7.66 0.76 8.66 0.875 8.66 0.875 10.04 0.28 10.04 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 11.72 0.875 11.72 0.875 13.1 0.76 13.1 0.76 14.12 0.28 14.12 0.28 14.44 0.875 14.44 0.875 15.82 0.76 15.82 0.76 16.84 0.28 16.84 0.28 17.16 0.875 17.16 0.875 18.54 0.76 18.54 0.76 19.54 0.875 19.54 0.875 20.24 0.28 20.24 0.28 20.56 0.875 20.56 0.875 21.26 0.76 21.26 0.76 22.28 0.28 22.28 0.28 22.6 0.875 22.6 0.875 23.98 0.76 23.98 0.76 25 0.28 25 0.28 25.32 0.875 25.32 0.875 26.7 0.76 26.7 0.76 27.7 0.875 27.7 0.875 28.4 0.28 28.4 0.28 28.72 0.875 28.72 0.875 29.42 0.76 29.42 0.76 30.44 0.28 30.44 0.28 30.76 0.875 30.76 0.875 32.14 0.76 32.14 0.76 33.14 0.875 33.14 0.875 33.84 0.28 33.84 0.28 34.16 0.875 34.16 0.875 34.86 0.76 34.86 0.76 35.88 0.28 35.88 0.28 36.2 0.875 36.2 0.875 37.58 0.76 37.58 0.76 38.6 0.28 38.6 0.28 38.92 0.875 38.92 0.875 40.3 0.76 40.3 0.76 41.32 0.28 41.32 0.28 41.64 0.875 41.64 0.875 43.02 0.76 43.02 0.76 44.04 0.28 44.04 0.28 44.36 0.875 44.36 0.875 45.74 0.76 45.74 0.76 46.74 0.875 46.74 0.875 48.12 0.28 48.12 0.28 48.44 0.76 48.44 0.76 49.46 0.875 49.46 0.875 50.84 0.28 50.84 0.28 51.16 0.76 51.16 0.76 52.18 0.875 52.18 0.875 53.56 0.28 53.56 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 55.24 0.875 55.24 0.875 56.62 0.76 56.62 0.76 57.62 0.875 57.62 0.875 59 0.28 59 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 60.68 0.875 60.68 0.875 62.06 0.76 62.06 0.76 63.08 0.28 63.08 0.28 63.4 0.875 63.4 0.875 64.78 0.76 64.78 0.76 65.8 0.28 65.8 0.28 66.12 0.875 66.12 0.875 67.5 0.76 67.5 0.76 68.5 0.875 68.5 0.875 69.88 0.28 69.88 0.28 70.2 0.76 70.2 0.76 71.22 0.875 71.22 0.875 72.6 0.28 72.6 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 75.88 30.64 75.88 30.64 78.36 31.12 78.36 31.12 79.4 30.64 79.4 30.64 81.08 31.12 81.08 31.12 82.12 30.64 82.12 30.64 83.8 31.12 83.8 31.12 84.84 30.64 84.84 30.64 86.52 31.12 86.52 31.12 86.76 ; + LAYER met3 ; + POLYGON 89.405 87.085 89.405 87.08 89.62 87.08 89.62 86.76 89.405 86.76 89.405 86.755 89.075 86.755 89.075 86.76 88.86 86.76 88.86 87.08 89.075 87.08 89.075 87.085 ; + POLYGON 59.965 87.085 59.965 87.08 60.18 87.08 60.18 86.76 59.965 86.76 59.965 86.755 59.635 86.755 59.635 86.76 59.42 86.76 59.42 87.08 59.635 87.08 59.635 87.085 ; + POLYGON 71.22 78.01 71.22 77.71 30.97 77.71 30.97 75.98 31.01 75.98 31.01 75.66 30.63 75.66 30.63 75.98 30.67 75.98 30.67 78.01 ; + POLYGON 29.835 75.985 29.835 75.655 29.505 75.655 29.505 75.67 6.835 75.67 6.835 75.655 6.505 75.655 6.505 75.985 6.835 75.985 6.835 75.97 29.505 75.97 29.505 75.985 ; + POLYGON 133.12 6.61 133.12 6.59 133.67 6.59 133.67 6.31 114.16 6.31 114.16 6.61 ; + POLYGON 89.405 0.285 89.405 0.28 89.62 0.28 89.62 -0.04 89.405 -0.04 89.405 -0.045 89.075 -0.045 89.075 -0.04 88.86 -0.04 88.86 0.28 89.075 0.28 89.075 0.285 ; + POLYGON 59.965 0.285 59.965 0.28 60.18 0.28 60.18 -0.04 59.965 -0.04 59.965 -0.045 59.635 -0.045 59.635 -0.04 59.42 -0.04 59.42 0.28 59.635 0.28 59.635 0.285 ; + POLYGON 103.56 86.64 103.56 75.76 133.92 75.76 133.92 68.21 133.12 68.21 133.12 67.11 133.92 67.11 133.92 66.85 133.12 66.85 133.12 65.75 133.92 65.75 133.92 55.29 133.12 55.29 133.12 54.19 133.92 54.19 133.92 53.25 133.12 53.25 133.12 52.15 133.92 52.15 133.92 50.53 133.12 50.53 133.12 49.43 133.92 49.43 133.92 49.17 133.12 49.17 133.12 48.07 133.92 48.07 133.92 47.81 133.12 47.81 133.12 46.71 133.92 46.71 133.92 46.45 133.12 46.45 133.12 45.35 133.92 45.35 133.92 45.09 133.12 45.09 133.12 43.99 133.92 43.99 133.92 43.73 133.12 43.73 133.12 42.63 133.92 42.63 133.92 42.37 133.12 42.37 133.12 41.27 133.92 41.27 133.92 41.01 133.12 41.01 133.12 39.91 133.92 39.91 133.92 39.65 133.12 39.65 133.12 38.55 133.92 38.55 133.92 38.29 133.12 38.29 133.12 37.19 133.92 37.19 133.92 24.69 133.12 24.69 133.12 23.59 133.92 23.59 133.92 23.33 133.12 23.33 133.12 22.23 133.92 22.23 133.92 21.97 133.12 21.97 133.12 20.87 133.92 20.87 133.92 7.69 133.12 7.69 133.12 6.59 133.92 6.59 133.92 6.33 133.12 6.33 133.12 5.23 133.92 5.23 133.92 0.4 0.4 0.4 0.4 22.23 1.2 22.23 1.2 23.33 0.4 23.33 0.4 23.59 1.2 23.59 1.2 24.69 0.4 24.69 0.4 30.39 1.2 30.39 1.2 31.49 0.4 31.49 0.4 31.75 1.2 31.75 1.2 32.85 0.4 32.85 0.4 33.11 1.2 33.11 1.2 34.21 0.4 34.21 0.4 34.47 1.2 34.47 1.2 35.57 0.4 35.57 0.4 35.83 1.2 35.83 1.2 36.93 0.4 36.93 0.4 37.19 1.2 37.19 1.2 38.29 0.4 38.29 0.4 38.55 1.2 38.55 1.2 39.65 0.4 39.65 0.4 39.91 1.2 39.91 1.2 41.01 0.4 41.01 0.4 41.27 1.2 41.27 1.2 42.37 0.4 42.37 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 48.75 1.2 48.75 1.2 49.85 0.4 49.85 0.4 50.11 1.2 50.11 1.2 51.21 0.4 51.21 0.4 65.75 1.2 65.75 1.2 66.85 0.4 66.85 0.4 67.11 1.2 67.11 1.2 68.21 0.4 68.21 0.4 75.76 30.76 75.76 30.76 86.64 ; + LAYER met5 ; + POLYGON 102.36 85.44 102.36 74.56 132.72 74.56 132.72 61.68 129.52 61.68 129.52 55.28 132.72 55.28 132.72 41.28 129.52 41.28 129.52 34.88 132.72 34.88 132.72 20.88 129.52 20.88 129.52 14.48 132.72 14.48 132.72 1.6 1.6 1.6 1.6 14.48 4.8 14.48 4.8 20.88 1.6 20.88 1.6 34.88 4.8 34.88 4.8 41.28 1.6 41.28 1.6 55.28 4.8 55.28 4.8 61.68 1.6 61.68 1.6 74.56 31.96 74.56 31.96 85.44 ; + LAYER li1 ; + POLYGON 103.96 87.125 103.96 86.955 97.435 86.955 97.435 86.23 97.145 86.23 97.145 86.955 95.585 86.955 95.585 86.155 95.255 86.155 95.255 86.955 94.745 86.955 94.745 86.475 94.415 86.475 94.415 86.955 93.905 86.955 93.905 86.475 93.575 86.475 93.575 86.955 92.985 86.955 92.985 86.475 92.815 86.475 92.815 86.955 92.145 86.955 92.145 86.475 91.975 86.475 91.975 86.955 90.525 86.955 90.525 86.155 90.195 86.155 90.195 86.955 89.685 86.955 89.685 86.475 89.355 86.475 89.355 86.955 88.845 86.955 88.845 86.475 88.515 86.475 88.515 86.955 87.925 86.955 87.925 86.475 87.755 86.475 87.755 86.955 87.085 86.955 87.085 86.475 86.915 86.475 86.915 86.955 86.345 86.955 86.345 86.495 86.04 86.495 86.04 86.955 85.37 86.955 85.37 86.495 85.2 86.495 85.2 86.955 84.53 86.955 84.53 86.495 84.36 86.495 84.36 86.955 83.69 86.955 83.69 86.495 83.52 86.495 83.52 86.955 82.85 86.955 82.85 86.495 82.595 86.495 82.595 86.955 82.255 86.955 82.255 86.23 81.965 86.23 81.965 86.955 81.745 86.955 81.745 86.495 81.44 86.495 81.44 86.955 80.77 86.955 80.77 86.495 80.6 86.495 80.6 86.955 79.93 86.955 79.93 86.495 79.76 86.495 79.76 86.955 79.09 86.955 79.09 86.495 78.92 86.495 78.92 86.955 78.25 86.955 78.25 86.495 77.995 86.495 77.995 86.955 77.485 86.955 77.485 86.495 77.23 86.495 77.23 86.955 76.56 86.955 76.56 86.495 76.39 86.495 76.39 86.955 75.72 86.955 75.72 86.495 75.55 86.495 75.55 86.955 74.88 86.955 74.88 86.495 74.71 86.495 74.71 86.955 74.04 86.955 74.04 86.495 73.735 86.495 73.735 86.955 73.345 86.955 73.345 86.495 73.09 86.495 73.09 86.955 72.42 86.955 72.42 86.495 72.25 86.495 72.25 86.955 71.58 86.955 71.58 86.495 71.41 86.495 71.41 86.955 70.74 86.955 70.74 86.495 70.57 86.495 70.57 86.955 69.9 86.955 69.9 86.495 69.595 86.495 69.595 86.955 67.535 86.955 67.535 86.23 67.245 86.23 67.245 86.955 66.565 86.955 66.565 86.495 66.26 86.495 66.26 86.955 65.59 86.955 65.59 86.495 65.42 86.495 65.42 86.955 64.75 86.955 64.75 86.495 64.58 86.495 64.58 86.955 63.91 86.955 63.91 86.495 63.74 86.495 63.74 86.955 63.07 86.955 63.07 86.495 62.815 86.495 62.815 86.955 61.505 86.955 61.505 86.495 61.2 86.495 61.2 86.955 60.53 86.955 60.53 86.495 60.36 86.495 60.36 86.955 59.69 86.955 59.69 86.495 59.52 86.495 59.52 86.955 58.85 86.955 58.85 86.495 58.68 86.495 58.68 86.955 58.01 86.955 58.01 86.495 57.755 86.495 57.755 86.955 57.245 86.955 57.245 86.495 56.99 86.495 56.99 86.955 56.32 86.955 56.32 86.495 56.15 86.495 56.15 86.955 55.48 86.955 55.48 86.495 55.31 86.495 55.31 86.955 54.64 86.955 54.64 86.495 54.47 86.495 54.47 86.955 53.8 86.955 53.8 86.495 53.495 86.495 53.495 86.955 52.355 86.955 52.355 86.23 52.065 86.23 52.065 86.955 51.725 86.955 51.725 86.495 51.47 86.495 51.47 86.955 50.8 86.955 50.8 86.495 50.63 86.495 50.63 86.955 49.96 86.955 49.96 86.495 49.79 86.495 49.79 86.955 49.12 86.955 49.12 86.495 48.95 86.495 48.95 86.955 48.28 86.955 48.28 86.495 47.975 86.495 47.975 86.955 47.585 86.955 47.585 86.495 47.33 86.495 47.33 86.955 46.66 86.955 46.66 86.495 46.49 86.495 46.49 86.955 45.82 86.955 45.82 86.495 45.65 86.495 45.65 86.955 44.98 86.955 44.98 86.495 44.81 86.495 44.81 86.955 44.14 86.955 44.14 86.495 43.835 86.495 43.835 86.955 42.87 86.955 42.87 86.135 42.64 86.135 42.64 86.955 42.185 86.955 42.185 86.495 41.88 86.495 41.88 86.955 41.21 86.955 41.21 86.495 41.04 86.495 41.04 86.955 40.37 86.955 40.37 86.495 40.2 86.495 40.2 86.955 39.53 86.955 39.53 86.495 39.36 86.495 39.36 86.955 38.69 86.955 38.69 86.495 38.435 86.495 38.435 86.955 37.635 86.955 37.635 86.23 37.345 86.23 37.345 86.955 37.125 86.955 37.125 86.495 36.82 86.495 36.82 86.955 36.15 86.955 36.15 86.495 35.98 86.495 35.98 86.955 35.31 86.955 35.31 86.495 35.14 86.495 35.14 86.955 34.47 86.955 34.47 86.495 34.3 86.495 34.3 86.955 33.63 86.955 33.63 86.495 33.375 86.495 33.375 86.955 30.36 86.955 30.36 87.125 ; + RECT 103.04 84.235 103.96 84.405 ; + RECT 30.36 84.235 34.04 84.405 ; + RECT 103.04 81.515 103.96 81.685 ; + RECT 30.36 81.515 34.04 81.685 ; + RECT 103.04 78.795 103.96 78.965 ; + RECT 30.36 78.795 32.2 78.965 ; + POLYGON 134.32 76.245 134.32 76.075 131.465 76.075 131.465 75.275 131.135 75.275 131.135 76.075 130.625 76.075 130.625 75.595 130.295 75.595 130.295 76.075 129.785 76.075 129.785 75.595 129.455 75.595 129.455 76.075 128.865 76.075 128.865 75.595 128.695 75.595 128.695 76.075 128.025 76.075 128.025 75.595 127.855 75.595 127.855 76.075 127.335 76.075 127.335 75.35 127.045 75.35 127.045 76.075 126.445 76.075 126.445 75.675 126.115 75.675 126.115 76.075 124.155 76.075 124.155 75.54 123.645 75.54 123.645 76.075 120.925 76.075 120.925 75.615 120.62 75.615 120.62 76.075 119.135 76.075 119.135 75.635 118.945 75.635 118.945 76.075 117.045 76.075 117.045 75.615 116.715 75.615 116.715 76.075 114.115 76.075 114.115 75.715 113.785 75.715 113.785 76.075 113.085 76.075 113.085 75.695 112.755 75.695 112.755 76.075 112.155 76.075 112.155 75.35 111.865 75.35 111.865 76.075 111.265 76.075 111.265 75.615 110.96 75.615 110.96 76.075 109.475 76.075 109.475 75.635 109.285 75.635 109.285 76.075 107.385 76.075 107.385 75.615 107.055 75.615 107.055 76.075 104.455 76.075 104.455 75.715 104.125 75.715 104.125 76.075 103.425 76.075 103.425 75.695 103.095 75.695 103.095 76.075 102.58 76.075 102.58 76.245 ; + POLYGON 32.2 76.245 32.2 76.075 31.685 76.075 31.685 75.675 31.355 75.675 31.355 76.075 29.395 76.075 29.395 75.54 28.885 75.54 28.885 76.075 27.585 76.075 27.585 75.275 27.255 75.275 27.255 76.075 26.745 76.075 26.745 75.595 26.415 75.595 26.415 76.075 25.905 76.075 25.905 75.595 25.575 75.595 25.575 76.075 25.065 76.075 25.065 75.595 24.735 75.595 24.735 76.075 24.225 76.075 24.225 75.595 23.895 75.595 23.895 76.075 23.385 76.075 23.385 75.595 23.055 75.595 23.055 76.075 22.455 76.075 22.455 75.35 22.165 75.35 22.165 76.075 21.105 76.075 21.105 75.675 20.775 75.675 20.775 76.075 18.815 76.075 18.815 75.54 18.305 75.54 18.305 76.075 17.005 76.075 17.005 75.275 16.675 75.275 16.675 76.075 16.165 76.075 16.165 75.595 15.835 75.595 15.835 76.075 15.325 76.075 15.325 75.595 14.995 75.595 14.995 76.075 14.485 76.075 14.485 75.595 14.155 75.595 14.155 76.075 13.645 76.075 13.645 75.595 13.315 75.595 13.315 76.075 12.805 76.075 12.805 75.595 12.475 75.595 12.475 76.075 11.865 76.075 11.865 75.275 11.535 75.275 11.535 76.075 11.025 76.075 11.025 75.595 10.695 75.595 10.695 76.075 10.185 76.075 10.185 75.595 9.855 75.595 9.855 76.075 9.265 76.075 9.265 75.595 9.095 75.595 9.095 76.075 8.425 76.075 8.425 75.595 8.255 75.595 8.255 76.075 7.735 76.075 7.735 75.35 7.445 75.35 7.445 76.075 0 76.075 0 76.245 ; + RECT 133.4 73.355 134.32 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 133.4 70.635 134.32 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 133.4 67.915 134.32 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 133.4 65.195 134.32 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 133.4 62.475 134.32 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 133.4 59.755 134.32 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 133.86 57.035 134.32 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 133.4 54.315 134.32 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 133.4 51.595 134.32 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 133.4 48.875 134.32 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 133.4 46.155 134.32 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 133.4 43.435 134.32 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 133.4 40.715 134.32 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 133.4 37.995 134.32 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 133.4 35.275 134.32 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 133.4 32.555 134.32 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 133.4 29.835 134.32 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 133.4 27.115 134.32 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 133.4 24.395 134.32 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 133.4 21.675 134.32 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 133.4 18.955 134.32 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 133.4 16.235 134.32 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 133.4 13.515 134.32 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 133.86 10.795 134.32 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 133.4 8.075 134.32 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 133.4 5.355 134.32 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 133.4 2.635 134.32 2.805 ; + RECT 0 2.635 3.68 2.805 ; + POLYGON 77.83 0.905 77.83 0.085 79.185 0.085 79.185 0.465 79.515 0.465 79.515 0.085 81.965 0.085 81.965 0.81 82.255 0.81 82.255 0.085 82.855 0.085 82.855 0.465 83.185 0.465 83.185 0.085 83.885 0.085 83.885 0.445 84.215 0.445 84.215 0.085 86.815 0.085 86.815 0.545 87.145 0.545 87.145 0.085 89.045 0.085 89.045 0.525 89.235 0.525 89.235 0.085 90.72 0.085 90.72 0.545 91.025 0.545 91.025 0.085 97.145 0.085 97.145 0.81 97.435 0.81 97.435 0.085 100.335 0.085 100.335 0.465 100.665 0.465 100.665 0.085 101.365 0.085 101.365 0.445 101.695 0.445 101.695 0.085 104.295 0.085 104.295 0.545 104.625 0.545 104.625 0.085 106.525 0.085 106.525 0.525 106.715 0.525 106.715 0.085 108.2 0.085 108.2 0.545 108.505 0.545 108.505 0.085 111.865 0.085 111.865 0.81 112.155 0.81 112.155 0.085 112.755 0.085 112.755 0.465 113.085 0.465 113.085 0.085 113.785 0.085 113.785 0.445 114.115 0.445 114.115 0.085 116.715 0.085 116.715 0.545 117.045 0.545 117.045 0.085 118.945 0.085 118.945 0.525 119.135 0.525 119.135 0.085 120.62 0.085 120.62 0.545 120.925 0.545 120.925 0.085 127.045 0.085 127.045 0.81 127.335 0.81 127.335 0.085 134.32 0.085 134.32 -0.085 0 -0.085 0 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 13.395 0.085 13.395 0.465 13.725 0.465 13.725 0.085 14.425 0.085 14.425 0.445 14.755 0.445 14.755 0.085 17.355 0.085 17.355 0.545 17.685 0.545 17.685 0.085 19.585 0.085 19.585 0.525 19.775 0.525 19.775 0.085 21.26 0.085 21.26 0.545 21.565 0.545 21.565 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 25.815 0.085 25.815 0.465 26.145 0.465 26.145 0.085 26.845 0.085 26.845 0.445 27.175 0.445 27.175 0.085 29.775 0.085 29.775 0.545 30.105 0.545 30.105 0.085 32.005 0.085 32.005 0.525 32.195 0.525 32.195 0.085 33.68 0.085 33.68 0.545 33.985 0.545 33.985 0.085 35.485 0.085 35.485 0.465 35.815 0.465 35.815 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 39.01 0.085 39.01 0.905 39.24 0.905 39.24 0.085 40.545 0.085 40.545 0.465 40.875 0.465 40.875 0.085 43.295 0.085 43.295 0.465 43.625 0.465 43.625 0.085 44.325 0.085 44.325 0.445 44.655 0.445 44.655 0.085 47.255 0.085 47.255 0.545 47.585 0.545 47.585 0.085 49.485 0.085 49.485 0.525 49.675 0.525 49.675 0.085 51.16 0.085 51.16 0.545 51.465 0.545 51.465 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 61.705 0.085 61.705 0.465 62.035 0.465 62.035 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 68.135 0.085 68.135 0.465 68.465 0.465 68.465 0.085 69.165 0.085 69.165 0.445 69.495 0.445 69.495 0.085 72.095 0.085 72.095 0.545 72.425 0.545 72.425 0.085 74.325 0.085 74.325 0.525 74.515 0.525 74.515 0.085 76 0.085 76 0.545 76.305 0.545 76.305 0.085 77.6 0.085 77.6 0.905 ; + POLYGON 103.79 86.87 103.79 75.99 134.15 75.99 134.15 0.17 0.17 0.17 0.17 75.99 30.53 75.99 30.53 86.87 ; + LAYER via ; + RECT 89.165 86.845 89.315 86.995 ; + RECT 59.725 86.845 59.875 86.995 ; + RECT 93.075 86.455 93.225 86.605 ; + RECT 66.855 86.455 67.005 86.605 ; + RECT 47.995 86.455 48.145 86.605 ; + RECT 34.655 86.455 34.805 86.605 ; + RECT 18.555 75.575 18.705 75.725 ; + RECT 73.755 0.435 73.905 0.585 ; + RECT 89.165 0.045 89.315 0.195 ; + RECT 59.725 0.045 59.875 0.195 ; + LAYER via2 ; + RECT 89.14 86.82 89.34 87.02 ; + RECT 59.7 86.82 59.9 87.02 ; + RECT 29.57 75.72 29.77 75.92 ; + RECT 6.57 75.72 6.77 75.92 ; + RECT 89.14 0.02 89.34 0.22 ; + RECT 59.7 0.02 59.9 0.22 ; + LAYER via3 ; + RECT 89.14 86.82 89.34 87.02 ; + RECT 59.7 86.82 59.9 87.02 ; + RECT 30.72 75.72 30.92 75.92 ; + RECT 89.14 0.02 89.34 0.22 ; + RECT 59.7 0.02 59.9 0.22 ; + LAYER OVERLAP ; + POLYGON 0 0 0 76.16 30.36 76.16 30.36 87.04 103.96 87.04 103.96 76.16 134.32 76.16 134.32 0 ; + END +END sb_1__0_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_1__1__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_1__1__icv_in_design.lef new file mode 100644 index 0000000..d865eac --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_1__1__icv_in_design.lef @@ -0,0 +1,3275 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_1__1_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 134.32 BY 97.92 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 97.435 58.26 97.92 ; + END + END pReset[0] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 98.75 97.12 99.05 97.92 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.6 97.435 75.74 97.92 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.68 97.435 51.82 97.92 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 80.35 97.12 80.65 97.92 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 70.23 97.12 70.53 97.92 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 61.03 97.12 61.33 97.92 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 84.03 97.12 84.33 97.92 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 87.56 97.435 87.7 97.92 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 92.31 97.12 92.61 97.92 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.8 97.435 84.94 97.92 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 85.72 97.435 85.86 97.92 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.04 97.435 82.18 97.92 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 66.55 97.12 66.85 97.92 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 82.19 97.12 82.49 97.92 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 90.47 97.12 90.77 97.92 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.04 97.435 59.18 97.92 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 99.52 97.435 99.66 97.92 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.94 97.435 66.08 97.92 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94.92 97.435 95.06 97.92 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 78.51 97.12 78.81 97.92 ; + END + END chany_top_in[19] + PIN chany_top_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 68.39 97.12 68.69 97.92 ; + END + END chany_top_in[20] + PIN chany_top_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 62.87 97.12 63.17 97.92 ; + END + END chany_top_in[21] + PIN chany_top_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 100.44 97.435 100.58 97.92 ; + END + END chany_top_in[22] + PIN chany_top_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.44 97.435 77.58 97.92 ; + END + END chany_top_in[23] + PIN chany_top_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 76.67 97.12 76.97 97.92 ; + END + END chany_top_in[24] + PIN chany_top_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 64.71 97.12 65.01 97.92 ; + END + END chany_top_in[25] + PIN chany_top_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 94.15 97.12 94.45 97.92 ; + END + END chany_top_in[26] + PIN chany_top_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94 97.435 94.14 97.92 ; + END + END chany_top_in[27] + PIN chany_top_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 85.87 97.12 86.17 97.92 ; + END + END chany_top_in[28] + PIN chany_top_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 89.86 97.435 90 97.92 ; + END + END chany_top_in[29] + PIN top_left_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 30.36 91.56 30.955 91.7 ; + END + END top_left_grid_pin_44_[0] + PIN top_left_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 86.555 14.1 87.04 ; + END + END top_left_grid_pin_45_[0] + PIN top_left_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 30.36 90.88 30.955 91.02 ; + END + END top_left_grid_pin_46_[0] + PIN top_left_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.82 86.555 9.96 87.04 ; + END + END top_left_grid_pin_47_[0] + PIN top_left_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 30.36 91.99 31.16 92.29 ; + END + END top_left_grid_pin_48_[0] + PIN top_left_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.56 86.555 18.7 87.04 ; + END + END top_left_grid_pin_49_[0] + PIN top_left_grid_pin_50_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 30.36 88.84 30.955 88.98 ; + END + END top_left_grid_pin_50_[0] + PIN top_left_grid_pin_51_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.64 86.555 17.78 87.04 ; + END + END top_left_grid_pin_51_[0] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 68.78 134.32 68.92 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 69.46 134.32 69.6 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 43.03 134.32 43.33 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 41.67 134.32 41.97 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 26.71 134.32 27.01 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 52.55 134.32 52.85 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 51.19 134.32 51.49 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 49.74 134.32 49.88 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 45.75 134.32 46.05 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 40.31 134.32 40.61 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 52.46 134.32 52.6 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 44.3 134.32 44.44 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 29.43 134.32 29.73 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 47.11 134.32 47.41 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 53.14 134.32 53.28 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 79.66 134.32 79.8 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 44.39 134.32 44.69 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 41.58 134.32 41.72 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 60.71 134.32 61.01 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 36.14 134.32 36.28 ; + END + END chanx_right_in[19] + PIN chanx_right_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 47.7 134.32 47.84 ; + END + END chanx_right_in[20] + PIN chanx_right_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 74.9 134.32 75.04 ; + END + END chanx_right_in[21] + PIN chanx_right_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 50.42 134.32 50.56 ; + END + END chanx_right_in[22] + PIN chanx_right_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 34.44 134.32 34.58 ; + END + END chanx_right_in[23] + PIN chanx_right_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 49.83 134.32 50.13 ; + END + END chanx_right_in[24] + PIN chanx_right_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 42.26 134.32 42.4 ; + END + END chanx_right_in[25] + PIN chanx_right_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 62.07 134.32 62.37 ; + END + END chanx_right_in[26] + PIN chanx_right_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 53.91 134.32 54.21 ; + END + END chanx_right_in[27] + PIN chanx_right_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 29 134.32 29.14 ; + END + END chanx_right_in[28] + PIN chanx_right_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 48.47 134.32 48.77 ; + END + END chanx_right_in[29] + PIN right_bottom_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 6.22 103.96 6.36 ; + END + END right_bottom_grid_pin_36_[0] + PIN right_bottom_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 12.68 134.32 12.82 ; + END + END right_bottom_grid_pin_37_[0] + PIN right_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 121.14 10.88 121.28 11.365 ; + END + END right_bottom_grid_pin_38_[0] + PIN right_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 14.38 134.32 14.52 ; + END + END right_bottom_grid_pin_39_[0] + PIN right_bottom_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 123.9 10.88 124.04 11.365 ; + END + END right_bottom_grid_pin_40_[0] + PIN right_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 1.8 103.96 1.94 ; + END + END right_bottom_grid_pin_41_[0] + PIN right_bottom_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 6.9 103.96 7.04 ; + END + END right_bottom_grid_pin_42_[0] + PIN right_bottom_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 124.82 10.88 124.96 11.365 ; + END + END right_bottom_grid_pin_43_[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 58.27 0 58.57 0.8 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.36 0 55.5 0.485 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 68.39 0 68.69 0.8 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94 0 94.14 0.485 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 80.35 0 80.65 0.8 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 98.75 0 99.05 0.8 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.82 0 78.96 0.485 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 66.55 0 66.85 0.8 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 76.67 0 76.97 0.8 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 84.95 0 85.25 0.8 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 92.31 0 92.61 0.8 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 0 58.26 0.485 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.08 0 93.22 0.485 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 71.15 0 71.45 0.8 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.88 0 84.02 0.485 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 99.52 0 99.66 0.485 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 100.44 0 100.58 0.485 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 64.71 0 65.01 0.8 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.24 0 68.38 0.485 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 85.72 0 85.86 0.485 ; + END + END chany_bottom_in[19] + PIN chany_bottom_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.78 0 44.92 0.485 ; + END + END chany_bottom_in[20] + PIN chany_bottom_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 62.87 0 63.17 0.8 ; + END + END chany_bottom_in[21] + PIN chany_bottom_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.04 0 59.18 0.485 ; + END + END chany_bottom_in[22] + PIN chany_bottom_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.48 0 65.62 0.485 ; + END + END chany_bottom_in[23] + PIN chany_bottom_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 90.47 0 90.77 0.8 ; + END + END chany_bottom_in[24] + PIN chany_bottom_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 87.56 0 87.7 0.485 ; + END + END chany_bottom_in[25] + PIN chany_bottom_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 94.15 0 94.45 0.8 ; + END + END chany_bottom_in[26] + PIN chany_bottom_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 91.24 0 91.38 0.485 ; + END + END chany_bottom_in[27] + PIN chany_bottom_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 78.51 0 78.81 0.8 ; + END + END chany_bottom_in[28] + PIN chany_bottom_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.16 0 69.3 0.485 ; + END + END chany_bottom_in[29] + PIN bottom_left_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.44 10.88 8.58 11.365 ; + END + END bottom_left_grid_pin_44_[0] + PIN bottom_left_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.2 10.88 11.34 11.365 ; + END + END bottom_left_grid_pin_45_[0] + PIN bottom_left_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 30.36 5.63 31.16 5.93 ; + END + END bottom_left_grid_pin_46_[0] + PIN bottom_left_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.94 10.88 20.08 11.365 ; + END + END bottom_left_grid_pin_47_[0] + PIN bottom_left_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 30.36 6.22 30.955 6.36 ; + END + END bottom_left_grid_pin_48_[0] + PIN bottom_left_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.1 10.88 18.24 11.365 ; + END + END bottom_left_grid_pin_49_[0] + PIN bottom_left_grid_pin_50_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.72 10.88 16.86 11.365 ; + END + END bottom_left_grid_pin_50_[0] + PIN bottom_left_grid_pin_51_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.8 10.88 15.94 11.365 ; + END + END bottom_left_grid_pin_51_[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 49.83 0.8 50.13 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 50.42 0.595 50.56 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 69.46 0.595 69.6 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 79.66 0.595 79.8 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 30.79 0.8 31.09 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 47.7 0.595 47.84 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 52.55 0.8 52.85 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 45.75 0.8 46.05 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 51.19 0.8 51.49 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 53.14 0.595 53.28 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.31 0.8 40.61 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.39 0.8 44.69 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.03 0.8 43.33 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.98 0.595 45.12 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 74.9 0.595 75.04 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 29 0.595 29.14 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 77.62 0.595 77.76 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 82.38 0.595 82.52 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 52.46 0.595 52.6 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 72.18 0.595 72.32 ; + END + END chanx_left_in[19] + PIN chanx_left_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.11 0.8 47.41 ; + END + END chanx_left_in[20] + PIN chanx_left_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 71.5 0.595 71.64 ; + END + END chanx_left_in[21] + PIN chanx_left_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 48.47 0.8 48.77 ; + END + END chanx_left_in[22] + PIN chanx_left_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 55.52 0.595 55.66 ; + END + END chanx_left_in[23] + PIN chanx_left_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 53.91 0.8 54.21 ; + END + END chanx_left_in[24] + PIN chanx_left_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 47.02 0.595 47.16 ; + END + END chanx_left_in[25] + PIN chanx_left_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 49.74 0.595 49.88 ; + END + END chanx_left_in[26] + PIN chanx_left_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 41.67 0.8 41.97 ; + END + END chanx_left_in[27] + PIN chanx_left_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 80.34 0.595 80.48 ; + END + END chanx_left_in[28] + PIN chanx_left_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.23 0.8 36.53 ; + END + END chanx_left_in[29] + PIN left_bottom_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.12 10.88 12.26 11.365 ; + END + END left_bottom_grid_pin_36_[0] + PIN left_bottom_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.6 10.88 6.74 11.365 ; + END + END left_bottom_grid_pin_37_[0] + PIN left_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.28 10.88 10.42 11.365 ; + END + END left_bottom_grid_pin_38_[0] + PIN left_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.36 10.88 9.5 11.365 ; + END + END left_bottom_grid_pin_39_[0] + PIN left_bottom_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.04 10.88 13.18 11.365 ; + END + END left_bottom_grid_pin_40_[0] + PIN left_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 10.88 14.1 11.365 ; + END + END left_bottom_grid_pin_41_[0] + PIN left_bottom_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.52 10.88 7.66 11.365 ; + END + END left_bottom_grid_pin_42_[0] + PIN left_bottom_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.88 10.88 15.02 11.365 ; + END + END left_bottom_grid_pin_43_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 71.5 134.32 71.64 ; + END + END ccff_head[0] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.12 97.435 81.26 97.92 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.2 97.435 80.34 97.92 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.48 97.435 42.62 97.92 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.64 97.435 86.78 97.92 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.92 97.435 72.06 97.92 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.1 97.435 41.24 97.92 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.88 97.435 84.02 97.92 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.3 97.435 73.44 97.92 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.7 97.435 68.84 97.92 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.18 97.435 63.32 97.92 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.8 97.435 61.94 97.92 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.92 97.435 49.06 97.92 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 58.27 97.12 58.57 97.92 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.36 97.435 78.5 97.92 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.32 97.435 44.46 97.92 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 101.36 97.435 101.5 97.92 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.28 97.435 79.42 97.92 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.62 97.435 46.76 97.92 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.86 97.435 67 97.92 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 72.07 97.12 72.37 97.92 ; + END + END chany_top_out[19] + PIN chany_top_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48 97.435 48.14 97.92 ; + END + END chany_top_out[20] + PIN chany_top_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.08 97.435 93.22 97.92 ; + END + END chany_top_out[21] + PIN chany_top_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.88 97.435 61.02 97.92 ; + END + END chany_top_out[22] + PIN chany_top_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.88 97.435 38.02 97.92 ; + END + END chany_top_out[23] + PIN chany_top_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.52 97.435 76.66 97.92 ; + END + END chany_top_out[24] + PIN chany_top_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.78 97.435 67.92 97.92 ; + END + END chany_top_out[25] + PIN chany_top_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 97.435 37.1 97.92 ; + END + END chany_top_out[26] + PIN chany_top_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.02 97.435 65.16 97.92 ; + END + END chany_top_out[27] + PIN chany_top_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.62 97.435 69.76 97.92 ; + END + END chany_top_out[28] + PIN chany_top_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.1 97.435 64.24 97.92 ; + END + END chany_top_out[29] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 56.2 134.32 56.34 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 36.82 134.32 36.96 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 27.98 134.32 28.12 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 38.86 134.32 39 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 76.94 134.32 77.08 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 31.04 134.32 31.18 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 55.52 134.32 55.66 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 55.27 134.32 55.57 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 57.99 134.32 58.29 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 56.63 134.32 56.93 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 37.59 134.32 37.89 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 59.35 134.32 59.65 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 31.72 134.32 31.86 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 77.62 134.32 77.76 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 32.15 134.32 32.45 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 33.51 134.32 33.81 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 74.22 134.32 74.36 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 72.18 134.32 72.32 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 39.54 134.32 39.68 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 25.35 134.32 25.65 ; + END + END chanx_right_out[19] + PIN chanx_right_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 28.07 134.32 28.37 ; + END + END chanx_right_out[20] + PIN chanx_right_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 34.87 134.32 35.17 ; + END + END chanx_right_out[21] + PIN chanx_right_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 25.94 134.32 26.08 ; + END + END chanx_right_out[22] + PIN chanx_right_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 22.54 134.32 22.68 ; + END + END chanx_right_out[23] + PIN chanx_right_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 30.79 134.32 31.09 ; + END + END chanx_right_out[24] + PIN chanx_right_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 23.22 134.32 23.36 ; + END + END chanx_right_out[25] + PIN chanx_right_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 38.95 134.32 39.25 ; + END + END chanx_right_out[26] + PIN chanx_right_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 36.23 134.32 36.53 ; + END + END chanx_right_out[27] + PIN chanx_right_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 25.26 134.32 25.4 ; + END + END chanx_right_out[28] + PIN chanx_right_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 33.76 134.32 33.9 ; + END + END chanx_right_out[29] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.14 0 75.28 0.485 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.7 0 45.84 0.485 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.48 0 42.62 0.485 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.38 0 72.52 0.485 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 86.79 0 87.09 0.8 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.56 0 41.7 0.485 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.14 0 52.28 0.485 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 101.36 0 101.5 0.485 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.64 0 40.78 0.485 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.22 0 74.36 0.485 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.98 0 77.12 0.485 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.64 0 86.78 0.485 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.72 0 62.86 0.485 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 72.99 0 73.29 0.8 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 0 64.7 0.485 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.2 0 57.34 0.485 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 92.16 0 92.3 0.485 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 61.03 0 61.33 0.8 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.64 0 63.78 0.485 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.4 0 66.54 0.485 ; + END + END chany_bottom_out[19] + PIN chany_bottom_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.06 0 76.2 0.485 ; + END + END chany_bottom_out[20] + PIN chany_bottom_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.3 0 73.44 0.485 ; + END + END chany_bottom_out[21] + PIN chany_bottom_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.8 0 84.94 0.485 ; + END + END chany_bottom_out[22] + PIN chany_bottom_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.8 0 61.94 0.485 ; + END + END chany_bottom_out[23] + PIN chany_bottom_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.28 0 56.42 0.485 ; + END + END chany_bottom_out[24] + PIN chany_bottom_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.32 0 67.46 0.485 ; + END + END chany_bottom_out[25] + PIN chany_bottom_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 88.48 0 88.62 0.485 ; + END + END chany_bottom_out[26] + PIN chany_bottom_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.2 0 80.34 0.485 ; + END + END chany_bottom_out[27] + PIN chany_bottom_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.9 0 78.04 0.485 ; + END + END chany_bottom_out[28] + PIN chany_bottom_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 90.32 0 90.46 0.485 ; + END + END chany_bottom_out[29] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.04 0.595 31.18 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 28.07 0.8 28.37 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 39.54 0.595 39.68 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.82 0.595 36.96 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 25.94 0.595 26.08 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 32.15 0.8 32.45 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 38.86 0.595 39 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 26.71 0.8 27.01 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 34.44 0.595 34.58 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.3 0.595 44.44 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.51 0.8 33.81 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 29.43 0.8 29.73 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.72 0.595 31.86 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 76.94 0.595 77.08 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 25.35 0.8 25.65 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 41.58 0.595 41.72 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 56.63 0.8 56.93 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 42.26 0.595 42.4 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 28.32 0.595 28.46 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 83.06 0.595 83.2 ; + END + END chanx_left_out[19] + PIN chanx_left_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.14 0.595 36.28 ; + END + END chanx_left_out[20] + PIN chanx_left_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 37.59 0.8 37.89 ; + END + END chanx_left_out[21] + PIN chanx_left_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 25.26 0.595 25.4 ; + END + END chanx_left_out[22] + PIN chanx_left_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 74.22 0.595 74.36 ; + END + END chanx_left_out[23] + PIN chanx_left_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 68.78 0.595 68.92 ; + END + END chanx_left_out[24] + PIN chanx_left_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 55.27 0.8 55.57 ; + END + END chanx_left_out[25] + PIN chanx_left_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 38.95 0.8 39.25 ; + END + END chanx_left_out[26] + PIN chanx_left_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 34.87 0.8 35.17 ; + END + END chanx_left_out[27] + PIN chanx_left_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 33.76 0.595 33.9 ; + END + END chanx_left_out[28] + PIN chanx_left_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 22.54 0.595 22.68 ; + END + END chanx_left_out[29] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 56.2 0.595 56.34 ; + END + END ccff_tail[0] + PIN Test_en_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.12 0 81.26 0.485 ; + END + END Test_en_S_in + PIN Test_en_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.96 97.435 83.1 97.92 ; + END + END Test_en_N_out + PIN pReset_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.88 0 61.02 0.485 ; + END + END pReset_S_in + PIN pReset_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 15.4 134.32 15.54 ; + END + END pReset_E_in + PIN pReset_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 22.63 0.8 22.93 ; + END + END pReset_W_in + PIN pReset_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 34.66 97.435 34.8 97.92 ; + END + END pReset_N_out + PIN pReset_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 20.16 0.595 20.3 ; + END + END pReset_W_out + PIN pReset_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 47.02 134.32 47.16 ; + END + END pReset_E_out + PIN Reset_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.04 0 82.18 0.485 ; + END + END Reset_S_in + PIN Reset_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.68 97.435 74.82 97.92 ; + END + END Reset_N_out + PIN prog_clk_0_N_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 33.74 97.435 33.88 97.92 ; + END + END prog_clk_0_N_in + PIN prog_clk_1_N_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71 97.435 71.14 97.92 ; + END + END prog_clk_1_N_in + PIN prog_clk_1_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.46 0 71.6 0.485 ; + END + END prog_clk_1_S_in + PIN prog_clk_1_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 22.63 134.32 22.93 ; + END + END prog_clk_1_E_out + PIN prog_clk_1_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 23.99 0.8 24.29 ; + END + END prog_clk_1_W_out + PIN prog_clk_2_N_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.76 97.435 96.9 97.92 ; + END + END prog_clk_2_N_in + PIN prog_clk_2_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 60.96 134.32 61.1 ; + END + END prog_clk_2_E_in + PIN prog_clk_2_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 96.91 0 97.21 0.8 ; + END + END prog_clk_2_S_in + PIN prog_clk_2_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 58.24 0.595 58.38 ; + END + END prog_clk_2_W_in + PIN prog_clk_2_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 60.96 0.595 61.1 ; + END + END prog_clk_2_W_out + PIN prog_clk_2_S_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94.92 0 95.06 0.485 ; + END + END prog_clk_2_S_out + PIN prog_clk_2_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 95.84 97.435 95.98 97.92 ; + END + END prog_clk_2_N_out + PIN prog_clk_2_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 58.24 134.32 58.38 ; + END + END prog_clk_2_E_out + PIN prog_clk_3_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 58.92 0.595 59.06 ; + END + END prog_clk_3_W_in + PIN prog_clk_3_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 61.64 134.32 61.78 ; + END + END prog_clk_3_E_in + PIN prog_clk_3_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.76 0 96.9 0.485 ; + END + END prog_clk_3_S_in + PIN prog_clk_3_N_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 96.91 97.12 97.21 97.92 ; + END + END prog_clk_3_N_in + PIN prog_clk_3_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 58.92 134.32 59.06 ; + END + END prog_clk_3_E_out + PIN prog_clk_3_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 61.64 0.595 61.78 ; + END + END prog_clk_3_W_out + PIN prog_clk_3_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 90.78 97.435 90.92 97.92 ; + END + END prog_clk_3_N_out + PIN prog_clk_3_S_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 95.84 0 95.98 0.485 ; + END + END prog_clk_3_S_out + PIN clk_1_N_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 92.16 97.435 92.3 97.92 ; + END + END clk_1_N_in + PIN clk_1_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.54 0 70.68 0.485 ; + END + END clk_1_S_in + PIN clk_1_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 23.99 134.32 24.29 ; + END + END clk_1_E_out + PIN clk_1_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 23.56 0.595 23.7 ; + END + END clk_1_W_out + PIN clk_2_N_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 87.71 97.12 88.01 97.92 ; + END + END clk_2_N_in + PIN clk_2_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 63.68 134.32 63.82 ; + END + END clk_2_E_in + PIN clk_2_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.96 0 83.1 0.485 ; + END + END clk_2_S_in + PIN clk_2_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 64.36 0.595 64.5 ; + END + END clk_2_W_in + PIN clk_2_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 63.68 0.595 63.82 ; + END + END clk_2_W_out + PIN clk_2_S_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 97.68 0 97.82 0.485 ; + END + END clk_2_S_out + PIN clk_2_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 97.68 97.435 97.82 97.92 ; + END + END clk_2_N_out + PIN clk_2_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 66.06 134.32 66.2 ; + END + END clk_2_E_out + PIN clk_3_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 66.06 0.595 66.2 ; + END + END clk_3_W_in + PIN clk_3_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 66.74 134.32 66.88 ; + END + END clk_3_E_in + PIN clk_3_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 83.11 0 83.41 0.8 ; + END + END clk_3_S_in + PIN clk_3_N_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 88.48 97.435 88.62 97.92 ; + END + END clk_3_N_in + PIN clk_3_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 64.36 134.32 64.5 ; + END + END clk_3_E_out + PIN clk_3_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 66.74 0.595 66.88 ; + END + END clk_3_W_out + PIN clk_3_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 98.6 97.435 98.74 97.92 ; + END + END clk_3_N_out + PIN clk_3_S_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 98.6 0 98.74 0.485 ; + END + END clk_3_S_out + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 26.96 3.2 30.16 ; + RECT 131.12 26.96 134.32 30.16 ; + RECT 0 67.76 3.2 70.96 ; + RECT 131.12 67.76 134.32 70.96 ; + LAYER met4 ; + RECT 44.78 0 45.38 0.6 ; + RECT 74.22 0 74.82 0.6 ; + RECT 13.5 10.88 14.1 11.48 ; + RECT 120.22 10.88 120.82 11.48 ; + RECT 13.5 86.44 14.1 87.04 ; + RECT 120.22 86.44 120.82 87.04 ; + RECT 44.78 97.32 45.38 97.92 ; + RECT 74.22 97.32 74.82 97.92 ; + LAYER met1 ; + RECT 30.36 2.48 30.84 2.96 ; + RECT 103.48 2.48 103.96 2.96 ; + RECT 30.36 7.92 30.84 8.4 ; + RECT 103.48 7.92 103.96 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 133.84 13.36 134.32 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 133.84 18.8 134.32 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 133.84 24.24 134.32 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 133.84 29.68 134.32 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 133.84 35.12 134.32 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 133.84 40.56 134.32 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 133.84 46 134.32 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 133.84 51.44 134.32 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 133.84 56.88 134.32 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 133.84 62.32 134.32 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 133.84 67.76 134.32 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 133.84 73.2 134.32 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 133.84 78.64 134.32 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 133.84 84.08 134.32 84.56 ; + RECT 30.36 89.52 30.84 90 ; + RECT 103.48 89.52 103.96 90 ; + RECT 30.36 94.96 30.84 95.44 ; + RECT 103.48 94.96 103.96 95.44 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 47.36 3.2 50.56 ; + RECT 131.12 47.36 134.32 50.56 ; + LAYER met4 ; + RECT 59.5 0 60.1 0.6 ; + RECT 88.94 0 89.54 0.6 ; + RECT 59.5 97.32 60.1 97.92 ; + RECT 88.94 97.32 89.54 97.92 ; + LAYER met1 ; + RECT 30.36 -0.24 30.84 0.24 ; + RECT 103.48 -0.24 103.96 0.24 ; + RECT 30.36 5.2 30.84 5.68 ; + RECT 103.48 5.2 103.96 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 133.84 10.64 134.32 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 133.84 16.08 134.32 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 133.84 21.52 134.32 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 133.84 26.96 134.32 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 133.84 32.4 134.32 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 133.84 37.84 134.32 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 133.84 43.28 134.32 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 133.84 48.72 134.32 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 133.84 54.16 134.32 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 133.84 59.6 134.32 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 133.84 65.04 134.32 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 133.84 70.48 134.32 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 133.84 75.92 134.32 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 133.84 81.36 134.32 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 133.84 86.8 134.32 87.28 ; + RECT 30.36 92.24 30.84 92.72 ; + RECT 103.48 92.24 103.96 92.72 ; + RECT 30.36 97.68 30.84 98.16 ; + RECT 103.48 97.68 103.96 98.16 ; + END + END VSS + OBS + LAYER met2 ; + RECT 89.1 97.615 89.38 97.985 ; + RECT 59.66 97.615 59.94 97.985 ; + POLYGON 75.28 97.82 75.28 93.26 75.14 93.26 75.14 97.68 75.1 97.68 75.1 97.82 ; + POLYGON 31.65 97.765 31.65 97.395 31.58 97.395 31.58 87.31 31.44 87.31 31.44 97.395 31.37 97.395 31.37 97.765 ; + RECT 98.08 96.91 98.34 97.23 ; + RECT 72.32 96.91 72.58 97.23 ; + RECT 41.96 96.91 42.22 97.23 ; + POLYGON 125.95 86.885 125.95 86.515 125.88 86.515 125.88 83.91 125.74 83.91 125.74 86.515 125.67 86.515 125.67 86.885 ; + POLYGON 26.59 86.885 26.59 86.515 26.52 86.515 26.52 71.67 26.38 71.67 26.38 86.515 26.31 86.515 26.31 86.885 ; + POLYGON 16.01 86.885 16.01 86.515 15.94 86.515 15.94 78.3 15.8 78.3 15.8 86.515 15.73 86.515 15.73 86.885 ; + RECT 17.12 86.03 17.38 86.35 ; + POLYGON 24.22 38.66 24.22 11.405 24.29 11.405 24.29 11.035 24.01 11.035 24.01 11.405 24.08 11.405 24.08 38.66 ; + POLYGON 73.9 17.24 73.9 0.24 73.94 0.24 73.94 0.1 73.76 0.1 73.76 17.24 ; + POLYGON 82.64 15.88 82.64 0.24 82.68 0.24 82.68 0.1 82.5 0.1 82.5 15.88 ; + POLYGON 30.66 15.37 30.66 1.77 31.58 1.77 31.58 1.63 30.52 1.63 30.52 15.37 ; + POLYGON 103.8 11.46 103.8 5.71 102.28 5.71 102.28 5.85 103.66 5.85 103.66 11.46 ; + RECT 89.8 0.69 90.06 1.01 ; + RECT 56.68 0.69 56.94 1.01 ; + RECT 41.93 0.72 42.25 0.98 ; + RECT 64.96 0.35 65.22 0.67 ; + RECT 89.1 -0.065 89.38 0.305 ; + RECT 59.66 -0.065 59.94 0.305 ; + RECT 96.26 0 96.48 0.14 ; + POLYGON 103.68 97.64 103.68 86.76 134.04 86.76 134.04 11.16 125.24 11.16 125.24 11.645 124.54 11.645 124.54 11.16 124.32 11.16 124.32 11.645 123.62 11.645 123.62 11.16 121.56 11.16 121.56 11.645 120.86 11.645 120.86 11.16 103.68 11.16 103.68 0.28 101.78 0.28 101.78 0.765 101.08 0.765 101.08 0.28 100.86 0.28 100.86 0.765 100.16 0.765 100.16 0.28 99.94 0.28 99.94 0.765 99.24 0.765 99.24 0.28 99.02 0.28 99.02 0.765 98.32 0.765 98.32 0.28 98.1 0.28 98.1 0.765 97.4 0.765 97.4 0.28 97.18 0.28 97.18 0.765 96.48 0.765 96.48 0.28 96.26 0.28 96.26 0.765 95.56 0.765 95.56 0.28 95.34 0.28 95.34 0.765 94.64 0.765 94.64 0.28 94.42 0.28 94.42 0.765 93.72 0.765 93.72 0.28 93.5 0.28 93.5 0.765 92.8 0.765 92.8 0.28 92.58 0.28 92.58 0.765 91.88 0.765 91.88 0.28 91.66 0.28 91.66 0.765 90.96 0.765 90.96 0.28 90.74 0.28 90.74 0.765 90.04 0.765 90.04 0.28 88.9 0.28 88.9 0.765 88.2 0.765 88.2 0.28 87.98 0.28 87.98 0.765 87.28 0.765 87.28 0.28 87.06 0.28 87.06 0.765 86.36 0.765 86.36 0.28 86.14 0.28 86.14 0.765 85.44 0.765 85.44 0.28 85.22 0.28 85.22 0.765 84.52 0.765 84.52 0.28 84.3 0.28 84.3 0.765 83.6 0.765 83.6 0.28 83.38 0.28 83.38 0.765 82.68 0.765 82.68 0.28 82.46 0.28 82.46 0.765 81.76 0.765 81.76 0.28 81.54 0.28 81.54 0.765 80.84 0.765 80.84 0.28 80.62 0.28 80.62 0.765 79.92 0.765 79.92 0.28 79.24 0.28 79.24 0.765 78.54 0.765 78.54 0.28 78.32 0.28 78.32 0.765 77.62 0.765 77.62 0.28 77.4 0.28 77.4 0.765 76.7 0.765 76.7 0.28 76.48 0.28 76.48 0.765 75.78 0.765 75.78 0.28 75.56 0.28 75.56 0.765 74.86 0.765 74.86 0.28 74.64 0.28 74.64 0.765 73.94 0.765 73.94 0.28 73.72 0.28 73.72 0.765 73.02 0.765 73.02 0.28 72.8 0.28 72.8 0.765 72.1 0.765 72.1 0.28 71.88 0.28 71.88 0.765 71.18 0.765 71.18 0.28 70.96 0.28 70.96 0.765 70.26 0.765 70.26 0.28 69.58 0.28 69.58 0.765 68.88 0.765 68.88 0.28 68.66 0.28 68.66 0.765 67.96 0.765 67.96 0.28 67.74 0.28 67.74 0.765 67.04 0.765 67.04 0.28 66.82 0.28 66.82 0.765 66.12 0.765 66.12 0.28 65.9 0.28 65.9 0.765 65.2 0.765 65.2 0.28 64.98 0.28 64.98 0.765 64.28 0.765 64.28 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 63.14 0.28 63.14 0.765 62.44 0.765 62.44 0.28 62.22 0.28 62.22 0.765 61.52 0.765 61.52 0.28 61.3 0.28 61.3 0.765 60.6 0.765 60.6 0.28 59.46 0.28 59.46 0.765 58.76 0.765 58.76 0.28 58.54 0.28 58.54 0.765 57.84 0.765 57.84 0.28 57.62 0.28 57.62 0.765 56.92 0.765 56.92 0.28 56.7 0.28 56.7 0.765 56 0.765 56 0.28 55.78 0.28 55.78 0.765 55.08 0.765 55.08 0.28 52.56 0.28 52.56 0.765 51.86 0.765 51.86 0.28 46.12 0.28 46.12 0.765 45.42 0.765 45.42 0.28 45.2 0.28 45.2 0.765 44.5 0.765 44.5 0.28 42.9 0.28 42.9 0.765 42.2 0.765 42.2 0.28 41.98 0.28 41.98 0.765 41.28 0.765 41.28 0.28 41.06 0.28 41.06 0.765 40.36 0.765 40.36 0.28 30.64 0.28 30.64 11.16 20.36 11.16 20.36 11.645 19.66 11.645 19.66 11.16 18.52 11.16 18.52 11.645 17.82 11.645 17.82 11.16 17.14 11.16 17.14 11.645 16.44 11.645 16.44 11.16 16.22 11.16 16.22 11.645 15.52 11.645 15.52 11.16 15.3 11.16 15.3 11.645 14.6 11.645 14.6 11.16 14.38 11.16 14.38 11.645 13.68 11.645 13.68 11.16 13.46 11.16 13.46 11.645 12.76 11.645 12.76 11.16 12.54 11.16 12.54 11.645 11.84 11.645 11.84 11.16 11.62 11.16 11.62 11.645 10.92 11.645 10.92 11.16 10.7 11.16 10.7 11.645 10 11.645 10 11.16 9.78 11.16 9.78 11.645 9.08 11.645 9.08 11.16 8.86 11.16 8.86 11.645 8.16 11.645 8.16 11.16 7.94 11.16 7.94 11.645 7.24 11.645 7.24 11.16 7.02 11.16 7.02 11.645 6.32 11.645 6.32 11.16 0.28 11.16 0.28 86.76 9.54 86.76 9.54 86.275 10.24 86.275 10.24 86.76 13.68 86.76 13.68 86.275 14.38 86.275 14.38 86.76 17.36 86.76 17.36 86.275 18.06 86.275 18.06 86.76 18.28 86.76 18.28 86.275 18.98 86.275 18.98 86.76 30.64 86.76 30.64 97.64 33.46 97.64 33.46 97.155 34.16 97.155 34.16 97.64 34.38 97.64 34.38 97.155 35.08 97.155 35.08 97.64 36.68 97.64 36.68 97.155 37.38 97.155 37.38 97.64 37.6 97.64 37.6 97.155 38.3 97.155 38.3 97.64 40.82 97.64 40.82 97.155 41.52 97.155 41.52 97.64 42.2 97.64 42.2 97.155 42.9 97.155 42.9 97.64 44.04 97.64 44.04 97.155 44.74 97.155 44.74 97.64 46.34 97.64 46.34 97.155 47.04 97.155 47.04 97.64 47.72 97.64 47.72 97.155 48.42 97.155 48.42 97.64 48.64 97.64 48.64 97.155 49.34 97.155 49.34 97.64 51.4 97.64 51.4 97.155 52.1 97.155 52.1 97.64 57.84 97.64 57.84 97.155 58.54 97.155 58.54 97.64 58.76 97.64 58.76 97.155 59.46 97.155 59.46 97.64 60.6 97.64 60.6 97.155 61.3 97.155 61.3 97.64 61.52 97.64 61.52 97.155 62.22 97.155 62.22 97.64 62.9 97.64 62.9 97.155 63.6 97.155 63.6 97.64 63.82 97.64 63.82 97.155 64.52 97.155 64.52 97.64 64.74 97.64 64.74 97.155 65.44 97.155 65.44 97.64 65.66 97.64 65.66 97.155 66.36 97.155 66.36 97.64 66.58 97.64 66.58 97.155 67.28 97.155 67.28 97.64 67.5 97.64 67.5 97.155 68.2 97.155 68.2 97.64 68.42 97.64 68.42 97.155 69.12 97.155 69.12 97.64 69.34 97.64 69.34 97.155 70.04 97.155 70.04 97.64 70.72 97.64 70.72 97.155 71.42 97.155 71.42 97.64 71.64 97.64 71.64 97.155 72.34 97.155 72.34 97.64 73.02 97.64 73.02 97.155 73.72 97.155 73.72 97.64 74.4 97.64 74.4 97.155 75.1 97.155 75.1 97.64 75.32 97.64 75.32 97.155 76.02 97.155 76.02 97.64 76.24 97.64 76.24 97.155 76.94 97.155 76.94 97.64 77.16 97.64 77.16 97.155 77.86 97.155 77.86 97.64 78.08 97.64 78.08 97.155 78.78 97.155 78.78 97.64 79 97.64 79 97.155 79.7 97.155 79.7 97.64 79.92 97.64 79.92 97.155 80.62 97.155 80.62 97.64 80.84 97.64 80.84 97.155 81.54 97.155 81.54 97.64 81.76 97.64 81.76 97.155 82.46 97.155 82.46 97.64 82.68 97.64 82.68 97.155 83.38 97.155 83.38 97.64 83.6 97.64 83.6 97.155 84.3 97.155 84.3 97.64 84.52 97.64 84.52 97.155 85.22 97.155 85.22 97.64 85.44 97.64 85.44 97.155 86.14 97.155 86.14 97.64 86.36 97.64 86.36 97.155 87.06 97.155 87.06 97.64 87.28 97.64 87.28 97.155 87.98 97.155 87.98 97.64 88.2 97.64 88.2 97.155 88.9 97.155 88.9 97.64 89.58 97.64 89.58 97.155 90.28 97.155 90.28 97.64 90.5 97.64 90.5 97.155 91.2 97.155 91.2 97.64 91.88 97.64 91.88 97.155 92.58 97.155 92.58 97.64 92.8 97.64 92.8 97.155 93.5 97.155 93.5 97.64 93.72 97.64 93.72 97.155 94.42 97.155 94.42 97.64 94.64 97.64 94.64 97.155 95.34 97.155 95.34 97.64 95.56 97.64 95.56 97.155 96.26 97.155 96.26 97.64 96.48 97.64 96.48 97.155 97.18 97.155 97.18 97.64 97.4 97.64 97.4 97.155 98.1 97.155 98.1 97.64 98.32 97.64 98.32 97.155 99.02 97.155 99.02 97.64 99.24 97.64 99.24 97.155 99.94 97.155 99.94 97.64 100.16 97.64 100.16 97.155 100.86 97.155 100.86 97.64 101.08 97.64 101.08 97.155 101.78 97.155 101.78 97.64 ; + LAYER met4 ; + POLYGON 87.105 97.745 87.105 97.415 87.09 97.415 87.09 48.47 86.79 48.47 86.79 97.415 86.775 97.415 86.775 97.745 ; + POLYGON 65.945 97.745 65.945 97.415 65.93 97.415 65.93 70.06 65.63 70.06 65.63 97.415 65.615 97.415 65.615 97.745 ; + POLYGON 50.305 97.745 50.305 97.415 50.29 97.415 50.29 95.39 49.99 95.39 49.99 97.415 49.975 97.415 49.975 97.745 ; + POLYGON 64.09 97.73 64.09 43.03 63.79 43.03 63.79 97.43 63.57 97.43 63.57 97.73 ; + POLYGON 31.89 95.69 31.89 95.39 30.97 95.39 30.97 77.71 30.67 77.71 30.67 95.69 ; + POLYGON 103.65 94.33 103.65 85.19 103.35 85.19 103.35 94.03 102.43 94.03 102.43 94.33 ; + POLYGON 64.09 41.29 64.09 0.505 64.105 0.505 64.105 0.175 63.775 0.175 63.775 0.505 63.79 0.505 63.79 41.29 ; + POLYGON 103.56 97.52 103.56 86.64 119.82 86.64 119.82 86.04 121.22 86.04 121.22 86.64 133.92 86.64 133.92 11.28 121.22 11.28 121.22 11.88 119.82 11.88 119.82 11.28 103.56 11.28 103.56 0.4 99.45 0.4 99.45 1.2 98.35 1.2 98.35 0.4 97.61 0.4 97.61 1.2 96.51 1.2 96.51 0.4 94.85 0.4 94.85 1.2 93.75 1.2 93.75 0.4 93.01 0.4 93.01 1.2 91.91 1.2 91.91 0.4 91.17 0.4 91.17 1.2 90.07 1.2 90.07 0.4 89.94 0.4 89.94 1 88.54 1 88.54 0.4 87.49 0.4 87.49 1.2 86.39 1.2 86.39 0.4 85.65 0.4 85.65 1.2 84.55 1.2 84.55 0.4 83.81 0.4 83.81 1.2 82.71 1.2 82.71 0.4 81.05 0.4 81.05 1.2 79.95 1.2 79.95 0.4 79.21 0.4 79.21 1.2 78.11 1.2 78.11 0.4 77.37 0.4 77.37 1.2 76.27 1.2 76.27 0.4 75.22 0.4 75.22 1 73.82 1 73.82 0.4 73.69 0.4 73.69 1.2 72.59 1.2 72.59 0.4 71.85 0.4 71.85 1.2 70.75 1.2 70.75 0.4 69.09 0.4 69.09 1.2 67.99 1.2 67.99 0.4 67.25 0.4 67.25 1.2 66.15 1.2 66.15 0.4 65.41 0.4 65.41 1.2 64.31 1.2 64.31 0.4 63.57 0.4 63.57 1.2 62.47 1.2 62.47 0.4 61.73 0.4 61.73 1.2 60.63 1.2 60.63 0.4 60.5 0.4 60.5 1 59.1 1 59.1 0.4 58.97 0.4 58.97 1.2 57.87 1.2 57.87 0.4 45.78 0.4 45.78 1 44.38 1 44.38 0.4 30.76 0.4 30.76 11.28 14.5 11.28 14.5 11.88 13.1 11.88 13.1 11.28 0.4 11.28 0.4 86.64 13.1 86.64 13.1 86.04 14.5 86.04 14.5 86.64 30.76 86.64 30.76 97.52 44.38 97.52 44.38 96.92 45.78 96.92 45.78 97.52 57.87 97.52 57.87 96.72 58.97 96.72 58.97 97.52 59.1 97.52 59.1 96.92 60.5 96.92 60.5 97.52 60.63 97.52 60.63 96.72 61.73 96.72 61.73 97.52 62.47 97.52 62.47 96.72 63.57 96.72 63.57 97.52 64.31 97.52 64.31 96.72 65.41 96.72 65.41 97.52 66.15 97.52 66.15 96.72 67.25 96.72 67.25 97.52 67.99 97.52 67.99 96.72 69.09 96.72 69.09 97.52 69.83 97.52 69.83 96.72 70.93 96.72 70.93 97.52 71.67 97.52 71.67 96.72 72.77 96.72 72.77 97.52 73.82 97.52 73.82 96.92 75.22 96.92 75.22 97.52 76.27 97.52 76.27 96.72 77.37 96.72 77.37 97.52 78.11 97.52 78.11 96.72 79.21 96.72 79.21 97.52 79.95 97.52 79.95 96.72 81.05 96.72 81.05 97.52 81.79 97.52 81.79 96.72 82.89 96.72 82.89 97.52 83.63 97.52 83.63 96.72 84.73 96.72 84.73 97.52 85.47 97.52 85.47 96.72 86.57 96.72 86.57 97.52 87.31 97.52 87.31 96.72 88.41 96.72 88.41 97.52 88.54 97.52 88.54 96.92 89.94 96.92 89.94 97.52 90.07 97.52 90.07 96.72 91.17 96.72 91.17 97.52 91.91 97.52 91.91 96.72 93.01 96.72 93.01 97.52 93.75 97.52 93.75 96.72 94.85 96.72 94.85 97.52 96.51 97.52 96.51 96.72 97.61 96.72 97.61 97.52 98.35 97.52 98.35 96.72 99.45 96.72 99.45 97.52 ; + LAYER met1 ; + POLYGON 103.2 98.16 103.2 97.68 89.4 97.68 89.4 97.67 89.08 97.67 89.08 97.68 59.96 97.68 59.96 97.67 59.64 97.67 59.64 97.68 31.12 97.68 31.12 98.16 ; + POLYGON 37.1 90.68 37.1 90.54 30.52 90.54 30.52 90.6 31.235 90.6 31.235 90.68 ; + RECT 72.36 86.8 133.56 87.28 ; + RECT 0.76 86.8 71.16 87.28 ; + POLYGON 3.98 48.52 3.98 48.38 0.76 48.38 0.76 48.12 0.62 48.12 0.62 48.52 ; + POLYGON 133.795 37.64 133.795 37.24 133.655 37.24 133.655 37.5 128.5 37.5 128.5 37.64 ; + RECT 72.36 10.64 133.56 11.12 ; + RECT 0.76 10.64 71.16 11.12 ; + POLYGON 89.4 0.25 89.4 0.24 103.2 0.24 103.2 -0.24 31.12 -0.24 31.12 0.24 59.64 0.24 59.64 0.25 59.96 0.25 59.96 0.24 89.08 0.24 89.08 0.25 ; + POLYGON 103.2 97.64 103.2 97.4 103.68 97.4 103.68 95.72 103.2 95.72 103.2 94.68 103.68 94.68 103.68 93 103.2 93 103.2 91.96 103.68 91.96 103.68 90.28 103.2 90.28 103.2 89.24 103.68 89.24 103.68 86.76 133.56 86.76 133.56 86.52 134.04 86.52 134.04 84.84 133.56 84.84 133.56 83.8 134.04 83.8 134.04 82.12 133.56 82.12 133.56 81.08 134.04 81.08 134.04 80.08 133.445 80.08 133.445 79.38 133.56 79.38 133.56 78.36 134.04 78.36 134.04 78.04 133.445 78.04 133.445 76.66 133.56 76.66 133.56 75.64 134.04 75.64 134.04 75.32 133.445 75.32 133.445 73.94 133.56 73.94 133.56 72.92 134.04 72.92 134.04 72.6 133.445 72.6 133.445 71.22 133.56 71.22 133.56 70.2 134.04 70.2 134.04 69.88 133.445 69.88 133.445 68.5 133.56 68.5 133.56 67.48 134.04 67.48 134.04 67.16 133.445 67.16 133.445 65.78 133.56 65.78 133.56 64.78 133.445 64.78 133.445 63.4 134.04 63.4 134.04 63.08 133.56 63.08 133.56 62.06 133.445 62.06 133.445 60.68 134.04 60.68 134.04 60.36 133.56 60.36 133.56 59.34 133.445 59.34 133.445 57.96 134.04 57.96 134.04 57.64 133.56 57.64 133.56 56.62 133.445 56.62 133.445 55.24 134.04 55.24 134.04 54.92 133.56 54.92 133.56 53.88 134.04 53.88 134.04 53.56 133.445 53.56 133.445 52.18 133.56 52.18 133.56 51.16 134.04 51.16 134.04 50.84 133.445 50.84 133.445 49.46 133.56 49.46 133.56 48.44 134.04 48.44 134.04 48.12 133.445 48.12 133.445 46.74 133.56 46.74 133.56 45.72 134.04 45.72 134.04 44.72 133.445 44.72 133.445 44.02 133.56 44.02 133.56 43 134.04 43 134.04 42.68 133.445 42.68 133.445 41.3 133.56 41.3 133.56 40.28 134.04 40.28 134.04 39.96 133.445 39.96 133.445 38.58 133.56 38.58 133.56 37.56 134.04 37.56 134.04 37.24 133.445 37.24 133.445 35.86 133.56 35.86 133.56 34.86 133.445 34.86 133.445 33.48 134.04 33.48 134.04 33.16 133.56 33.16 133.56 32.14 133.445 32.14 133.445 30.76 134.04 30.76 134.04 30.44 133.56 30.44 133.56 29.42 133.445 29.42 133.445 28.72 134.04 28.72 134.04 28.4 133.445 28.4 133.445 27.7 133.56 27.7 133.56 26.68 134.04 26.68 134.04 26.36 133.445 26.36 133.445 24.98 133.56 24.98 133.56 23.96 134.04 23.96 134.04 23.64 133.445 23.64 133.445 22.26 133.56 22.26 133.56 21.24 134.04 21.24 134.04 19.56 133.56 19.56 133.56 18.52 134.04 18.52 134.04 16.84 133.56 16.84 133.56 15.82 133.445 15.82 133.445 15.12 134.04 15.12 134.04 14.8 133.445 14.8 133.445 14.1 133.56 14.1 133.56 13.1 133.445 13.1 133.445 12.4 134.04 12.4 134.04 11.4 133.56 11.4 133.56 11.16 103.68 11.16 103.68 8.68 103.2 8.68 103.2 7.64 103.68 7.64 103.68 7.32 103.085 7.32 103.085 5.94 103.2 5.94 103.2 4.92 103.68 4.92 103.68 3.24 103.2 3.24 103.2 2.22 103.085 2.22 103.085 1.52 103.68 1.52 103.68 0.52 103.2 0.52 103.2 0.28 31.12 0.28 31.12 0.52 30.64 0.52 30.64 2.2 31.12 2.2 31.12 3.24 30.64 3.24 30.64 4.92 31.12 4.92 31.12 5.94 31.235 5.94 31.235 6.64 30.64 6.64 30.64 7.64 31.12 7.64 31.12 8.68 30.64 8.68 30.64 11.16 0.76 11.16 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 19.88 0.875 19.88 0.875 20.58 0.28 20.58 0.28 21.24 0.76 21.24 0.76 22.26 0.875 22.26 0.875 22.96 0.28 22.96 0.28 23.28 0.875 23.28 0.875 23.98 0.76 23.98 0.76 24.98 0.875 24.98 0.875 26.36 0.28 26.36 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 28.04 0.875 28.04 0.875 29.42 0.76 29.42 0.76 30.44 0.28 30.44 0.28 30.76 0.875 30.76 0.875 32.14 0.76 32.14 0.76 33.16 0.28 33.16 0.28 33.48 0.875 33.48 0.875 34.86 0.76 34.86 0.76 35.86 0.875 35.86 0.875 37.24 0.28 37.24 0.28 37.56 0.76 37.56 0.76 38.58 0.875 38.58 0.875 39.96 0.28 39.96 0.28 40.28 0.76 40.28 0.76 41.3 0.875 41.3 0.875 42.68 0.28 42.68 0.28 43 0.76 43 0.76 44.02 0.875 44.02 0.875 45.4 0.28 45.4 0.28 45.72 0.76 45.72 0.76 46.74 0.875 46.74 0.875 48.12 0.28 48.12 0.28 48.44 0.76 48.44 0.76 49.46 0.875 49.46 0.875 50.84 0.28 50.84 0.28 51.16 0.76 51.16 0.76 52.18 0.875 52.18 0.875 53.56 0.28 53.56 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 55.24 0.875 55.24 0.875 56.62 0.76 56.62 0.76 57.64 0.28 57.64 0.28 57.96 0.875 57.96 0.875 59.34 0.76 59.34 0.76 60.36 0.28 60.36 0.28 60.68 0.875 60.68 0.875 62.06 0.76 62.06 0.76 63.08 0.28 63.08 0.28 63.4 0.875 63.4 0.875 64.78 0.76 64.78 0.76 65.78 0.875 65.78 0.875 67.16 0.28 67.16 0.28 67.48 0.76 67.48 0.76 68.5 0.875 68.5 0.875 69.88 0.28 69.88 0.28 70.2 0.76 70.2 0.76 71.22 0.875 71.22 0.875 72.6 0.28 72.6 0.28 72.92 0.76 72.92 0.76 73.94 0.875 73.94 0.875 75.32 0.28 75.32 0.28 75.64 0.76 75.64 0.76 76.66 0.875 76.66 0.875 78.04 0.28 78.04 0.28 78.36 0.76 78.36 0.76 79.38 0.875 79.38 0.875 80.76 0.28 80.76 0.28 81.08 0.76 81.08 0.76 82.1 0.875 82.1 0.875 83.48 0.28 83.48 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 86.76 30.64 86.76 30.64 88.56 31.235 88.56 31.235 89.26 31.12 89.26 31.12 90.28 30.64 90.28 30.64 90.6 31.235 90.6 31.235 91.98 31.12 91.98 31.12 93 30.64 93 30.64 94.68 31.12 94.68 31.12 95.72 30.64 95.72 30.64 97.4 31.12 97.4 31.12 97.64 ; + LAYER met3 ; + POLYGON 89.405 97.965 89.405 97.96 89.62 97.96 89.62 97.64 89.405 97.64 89.405 97.635 89.075 97.635 89.075 97.64 88.86 97.64 88.86 97.96 89.075 97.96 89.075 97.965 ; + POLYGON 59.965 97.965 59.965 97.96 60.18 97.96 60.18 97.64 59.965 97.64 59.965 97.635 59.635 97.635 59.635 97.64 59.42 97.64 59.42 97.96 59.635 97.96 59.635 97.965 ; + POLYGON 96.995 97.745 96.995 97.415 96.665 97.415 96.665 97.43 96.075 97.43 96.075 97.415 95.745 97.415 95.745 97.745 96.075 97.745 96.075 97.73 96.665 97.73 96.665 97.745 ; + POLYGON 31.675 97.745 31.675 97.73 49.95 97.73 49.95 97.74 50.33 97.74 50.33 97.42 49.95 97.42 49.95 97.43 31.675 97.43 31.675 97.415 31.345 97.415 31.345 97.745 ; + POLYGON 87.13 97.74 87.13 97.42 86.75 97.42 86.75 97.43 70.57 97.43 70.57 97.42 70.19 97.42 70.19 97.74 70.57 97.74 70.57 97.73 86.75 97.73 86.75 97.74 ; + POLYGON 65.97 97.74 65.97 97.42 65.59 97.42 65.59 97.43 61.37 97.43 61.37 97.42 60.99 97.42 60.99 97.74 61.37 97.74 61.37 97.73 65.59 97.73 65.59 97.74 ; + RECT 31.55 91.3 31.93 91.62 ; + POLYGON 125.975 86.865 125.975 86.535 125.645 86.535 125.645 86.55 90.24 86.55 90.24 86.85 125.645 86.85 125.645 86.865 ; + POLYGON 26.615 86.865 26.615 86.85 31.66 86.85 31.66 86.55 26.615 86.55 26.615 86.535 26.285 86.535 26.285 86.865 ; + POLYGON 16.035 86.865 16.035 86.535 15.705 86.535 15.705 86.55 14.195 86.55 14.195 86.535 13.865 86.535 13.865 86.865 14.195 86.865 14.195 86.85 15.705 86.85 15.705 86.865 ; + POLYGON 133.12 34.49 133.12 34.47 133.67 34.47 133.67 34.19 114.62 34.19 114.62 34.49 ; + POLYGON 1.315 26.345 1.315 26.34 1.57 26.34 1.57 26.02 1.315 26.02 1.315 26.015 0.985 26.015 0.985 26.02 0.615 26.02 0.615 26.34 0.985 26.34 0.985 26.345 ; + POLYGON 133.67 26.33 133.67 26.05 133.12 26.05 133.12 26.03 110.94 26.03 110.94 26.33 ; + POLYGON 1.315 24.985 1.315 24.97 12.34 24.97 12.34 24.67 1.315 24.67 1.315 24.655 0.985 24.655 0.985 24.985 ; + POLYGON 114 12.05 114 11.07 102.2 11.07 102.2 11.37 113.7 11.37 113.7 12.05 ; + POLYGON 24.315 11.385 24.315 11.37 48.22 11.37 48.22 11.07 24.315 11.07 24.315 11.055 23.985 11.055 23.985 11.07 18.335 11.07 18.335 11.055 18.005 11.055 18.005 11.385 18.335 11.385 18.335 11.37 23.985 11.37 23.985 11.385 ; + RECT 31.55 6.3 31.93 6.62 ; + POLYGON 31.675 5.265 31.675 5.25 51.44 5.25 51.44 4.95 31.675 4.95 31.675 4.935 31.345 4.935 31.345 5.265 ; + POLYGON 65.01 1.85 65.01 0.5 65.05 0.5 65.05 0.18 64.67 0.18 64.67 0.5 64.71 0.5 64.71 1.85 ; + POLYGON 62.955 0.505 62.955 0.49 63.75 0.49 63.75 0.5 64.13 0.5 64.13 0.18 63.75 0.18 63.75 0.19 62.955 0.19 62.955 0.175 62.625 0.175 62.625 0.505 ; + POLYGON 89.405 0.285 89.405 0.28 89.62 0.28 89.62 -0.04 89.405 -0.04 89.405 -0.045 89.075 -0.045 89.075 -0.04 88.86 -0.04 88.86 0.28 89.075 0.28 89.075 0.285 ; + POLYGON 59.965 0.285 59.965 0.28 60.18 0.28 60.18 -0.04 59.965 -0.04 59.965 -0.045 59.635 -0.045 59.635 -0.04 59.42 -0.04 59.42 0.28 59.635 0.28 59.635 0.285 ; + POLYGON 103.56 97.52 103.56 86.64 133.92 86.64 133.92 62.77 133.12 62.77 133.12 61.67 133.92 61.67 133.92 61.41 133.12 61.41 133.12 60.31 133.92 60.31 133.92 60.05 133.12 60.05 133.12 58.95 133.92 58.95 133.92 58.69 133.12 58.69 133.12 57.59 133.92 57.59 133.92 57.33 133.12 57.33 133.12 56.23 133.92 56.23 133.92 55.97 133.12 55.97 133.12 54.87 133.92 54.87 133.92 54.61 133.12 54.61 133.12 53.51 133.92 53.51 133.92 53.25 133.12 53.25 133.12 52.15 133.92 52.15 133.92 51.89 133.12 51.89 133.12 50.79 133.92 50.79 133.92 50.53 133.12 50.53 133.12 49.43 133.92 49.43 133.92 49.17 133.12 49.17 133.12 48.07 133.92 48.07 133.92 47.81 133.12 47.81 133.12 46.71 133.92 46.71 133.92 46.45 133.12 46.45 133.12 45.35 133.92 45.35 133.92 45.09 133.12 45.09 133.12 43.99 133.92 43.99 133.92 43.73 133.12 43.73 133.12 42.63 133.92 42.63 133.92 42.37 133.12 42.37 133.12 41.27 133.92 41.27 133.92 41.01 133.12 41.01 133.12 39.91 133.92 39.91 133.92 39.65 133.12 39.65 133.12 38.55 133.92 38.55 133.92 38.29 133.12 38.29 133.12 37.19 133.92 37.19 133.92 36.93 133.12 36.93 133.12 35.83 133.92 35.83 133.92 35.57 133.12 35.57 133.12 34.47 133.92 34.47 133.92 34.21 133.12 34.21 133.12 33.11 133.92 33.11 133.92 32.85 133.12 32.85 133.12 31.75 133.92 31.75 133.92 31.49 133.12 31.49 133.12 30.39 133.92 30.39 133.92 30.13 133.12 30.13 133.12 29.03 133.92 29.03 133.92 28.77 133.12 28.77 133.12 27.67 133.92 27.67 133.92 27.41 133.12 27.41 133.12 26.31 133.92 26.31 133.92 26.05 133.12 26.05 133.12 24.95 133.92 24.95 133.92 24.69 133.12 24.69 133.12 23.59 133.92 23.59 133.92 23.33 133.12 23.33 133.12 22.23 133.92 22.23 133.92 11.28 103.56 11.28 103.56 0.4 30.76 0.4 30.76 5.23 31.56 5.23 31.56 6.33 30.76 6.33 30.76 11.28 0.4 11.28 0.4 22.23 1.2 22.23 1.2 23.33 0.4 23.33 0.4 23.59 1.2 23.59 1.2 24.69 0.4 24.69 0.4 24.95 1.2 24.95 1.2 26.05 0.4 26.05 0.4 26.31 1.2 26.31 1.2 27.41 0.4 27.41 0.4 27.67 1.2 27.67 1.2 28.77 0.4 28.77 0.4 29.03 1.2 29.03 1.2 30.13 0.4 30.13 0.4 30.39 1.2 30.39 1.2 31.49 0.4 31.49 0.4 31.75 1.2 31.75 1.2 32.85 0.4 32.85 0.4 33.11 1.2 33.11 1.2 34.21 0.4 34.21 0.4 34.47 1.2 34.47 1.2 35.57 0.4 35.57 0.4 35.83 1.2 35.83 1.2 36.93 0.4 36.93 0.4 37.19 1.2 37.19 1.2 38.29 0.4 38.29 0.4 38.55 1.2 38.55 1.2 39.65 0.4 39.65 0.4 39.91 1.2 39.91 1.2 41.01 0.4 41.01 0.4 41.27 1.2 41.27 1.2 42.37 0.4 42.37 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 48.07 1.2 48.07 1.2 49.17 0.4 49.17 0.4 49.43 1.2 49.43 1.2 50.53 0.4 50.53 0.4 50.79 1.2 50.79 1.2 51.89 0.4 51.89 0.4 52.15 1.2 52.15 1.2 53.25 0.4 53.25 0.4 53.51 1.2 53.51 1.2 54.61 0.4 54.61 0.4 54.87 1.2 54.87 1.2 55.97 0.4 55.97 0.4 56.23 1.2 56.23 1.2 57.33 0.4 57.33 0.4 86.64 30.76 86.64 30.76 91.59 31.56 91.59 31.56 92.69 30.76 92.69 30.76 97.52 ; + LAYER met5 ; + POLYGON 102.36 96.32 102.36 85.44 132.72 85.44 132.72 72.56 129.52 72.56 129.52 66.16 132.72 66.16 132.72 52.16 129.52 52.16 129.52 45.76 132.72 45.76 132.72 31.76 129.52 31.76 129.52 25.36 132.72 25.36 132.72 12.48 102.36 12.48 102.36 1.6 31.96 1.6 31.96 12.48 1.6 12.48 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 85.44 31.96 85.44 31.96 96.32 ; + LAYER li1 ; + POLYGON 103.96 98.005 103.96 97.835 100.265 97.835 100.265 97.035 99.935 97.035 99.935 97.835 99.425 97.835 99.425 97.355 99.095 97.355 99.095 97.835 98.585 97.835 98.585 97.355 98.255 97.355 98.255 97.835 97.745 97.835 97.745 97.355 97.415 97.355 97.415 97.835 96.905 97.835 96.905 97.355 96.575 97.355 96.575 97.835 96.065 97.835 96.065 97.355 95.735 97.355 95.735 97.835 94.705 97.835 94.705 97.355 94.375 97.355 94.375 97.835 93.865 97.835 93.865 97.355 93.535 97.355 93.535 97.835 93.025 97.835 93.025 97.355 92.695 97.355 92.695 97.835 92.185 97.835 92.185 97.355 91.855 97.355 91.855 97.835 91.345 97.835 91.345 97.355 91.015 97.355 91.015 97.835 90.505 97.835 90.505 97.035 90.175 97.035 90.175 97.835 89.225 97.835 89.225 97.035 88.895 97.035 88.895 97.835 88.385 97.835 88.385 97.355 88.055 97.355 88.055 97.835 87.545 97.835 87.545 97.355 87.215 97.355 87.215 97.835 86.705 97.835 86.705 97.355 86.375 97.355 86.375 97.835 85.865 97.835 85.865 97.355 85.535 97.355 85.535 97.835 85.025 97.835 85.025 97.355 84.695 97.355 84.695 97.835 83.705 97.835 83.705 97.035 83.375 97.035 83.375 97.835 82.865 97.835 82.865 97.355 82.535 97.355 82.535 97.835 82.025 97.835 82.025 97.355 81.695 97.355 81.695 97.835 81.185 97.835 81.185 97.355 80.855 97.355 80.855 97.835 80.345 97.835 80.345 97.355 80.015 97.355 80.015 97.835 79.505 97.835 79.505 97.355 79.175 97.355 79.175 97.835 77.485 97.835 77.485 97.375 77.23 97.375 77.23 97.835 76.56 97.835 76.56 97.375 76.39 97.375 76.39 97.835 75.72 97.835 75.72 97.375 75.55 97.375 75.55 97.835 74.88 97.835 74.88 97.375 74.71 97.375 74.71 97.835 74.04 97.835 74.04 97.375 73.735 97.375 73.735 97.835 73.165 97.835 73.165 97.355 72.995 97.355 72.995 97.835 72.325 97.835 72.325 97.355 72.155 97.355 72.155 97.835 71.565 97.835 71.565 97.355 71.235 97.355 71.235 97.835 70.725 97.835 70.725 97.355 70.395 97.355 70.395 97.835 69.885 97.835 69.885 97.035 69.555 97.035 69.555 97.835 67.565 97.835 67.565 97.355 67.235 97.355 67.235 97.835 66.725 97.835 66.725 97.355 66.395 97.355 66.395 97.835 65.885 97.835 65.885 97.355 65.555 97.355 65.555 97.835 65.045 97.835 65.045 97.355 64.715 97.355 64.715 97.835 64.205 97.835 64.205 97.355 63.875 97.355 63.875 97.835 63.365 97.835 63.365 97.035 63.035 97.035 63.035 97.835 62.305 97.835 62.305 97.375 62.05 97.375 62.05 97.835 61.38 97.835 61.38 97.375 61.21 97.375 61.21 97.835 60.54 97.835 60.54 97.375 60.37 97.375 60.37 97.835 59.7 97.835 59.7 97.375 59.53 97.375 59.53 97.835 58.86 97.835 58.86 97.375 58.555 97.375 58.555 97.835 56.945 97.835 56.945 97.035 56.615 97.035 56.615 97.835 56.105 97.835 56.105 97.355 55.775 97.355 55.775 97.835 55.265 97.835 55.265 97.355 54.935 97.355 54.935 97.835 54.345 97.835 54.345 97.355 54.175 97.355 54.175 97.835 53.505 97.835 53.505 97.355 53.335 97.355 53.335 97.835 51.465 97.835 51.465 97.375 51.16 97.375 51.16 97.835 49.675 97.835 49.675 97.395 49.485 97.395 49.485 97.835 47.585 97.835 47.585 97.375 47.255 97.375 47.255 97.835 44.655 97.835 44.655 97.475 44.325 97.475 44.325 97.835 43.625 97.835 43.625 97.455 43.295 97.455 43.295 97.835 41.885 97.835 41.885 97.355 41.715 97.355 41.715 97.835 41.045 97.835 41.045 97.355 40.875 97.355 40.875 97.835 40.285 97.835 40.285 97.355 39.955 97.355 39.955 97.835 39.445 97.835 39.445 97.355 39.115 97.355 39.115 97.835 38.605 97.835 38.605 97.035 38.275 97.035 38.275 97.835 37.585 97.835 37.585 97.375 37.28 97.375 37.28 97.835 36.61 97.835 36.61 97.375 36.44 97.375 36.44 97.835 35.77 97.835 35.77 97.375 35.6 97.375 35.6 97.835 34.93 97.835 34.93 97.375 34.76 97.375 34.76 97.835 34.09 97.835 34.09 97.375 33.835 97.375 33.835 97.835 30.36 97.835 30.36 98.005 ; + RECT 103.04 95.115 103.96 95.285 ; + RECT 30.36 95.115 32.2 95.285 ; + RECT 103.04 92.395 103.96 92.565 ; + RECT 30.36 92.395 32.2 92.565 ; + RECT 103.04 89.675 103.96 89.845 ; + RECT 30.36 89.675 32.2 89.845 ; + POLYGON 134.32 87.125 134.32 86.955 130.085 86.955 130.085 86.155 129.755 86.155 129.755 86.955 129.245 86.955 129.245 86.475 128.915 86.475 128.915 86.955 128.405 86.955 128.405 86.475 128.075 86.475 128.075 86.955 127.485 86.955 127.485 86.475 127.315 86.475 127.315 86.955 126.645 86.955 126.645 86.475 126.475 86.475 126.475 86.955 125.565 86.955 125.565 86.155 125.235 86.155 125.235 86.955 124.725 86.955 124.725 86.475 124.395 86.475 124.395 86.955 123.885 86.955 123.885 86.475 123.555 86.475 123.555 86.955 123.045 86.955 123.045 86.475 122.715 86.475 122.715 86.955 122.205 86.955 122.205 86.475 121.875 86.475 121.875 86.955 121.365 86.955 121.365 86.475 121.035 86.475 121.035 86.955 120.005 86.955 120.005 86.495 119.7 86.495 119.7 86.955 118.215 86.955 118.215 86.515 118.025 86.515 118.025 86.955 116.125 86.955 116.125 86.495 115.795 86.495 115.795 86.955 113.195 86.955 113.195 86.595 112.865 86.595 112.865 86.955 112.165 86.955 112.165 86.575 111.835 86.575 111.835 86.955 110.805 86.955 110.805 86.495 110.5 86.495 110.5 86.955 109.015 86.955 109.015 86.515 108.825 86.515 108.825 86.955 106.925 86.955 106.925 86.495 106.595 86.495 106.595 86.955 103.995 86.955 103.995 86.595 103.665 86.595 103.665 86.955 102.965 86.955 102.965 86.575 102.635 86.575 102.635 86.955 102.12 86.955 102.12 87.125 ; + POLYGON 32.2 87.125 32.2 86.955 31.685 86.955 31.685 86.495 31.38 86.495 31.38 86.955 29.895 86.955 29.895 86.515 29.705 86.515 29.705 86.955 27.805 86.955 27.805 86.495 27.475 86.495 27.475 86.955 24.875 86.955 24.875 86.595 24.545 86.595 24.545 86.955 23.845 86.955 23.845 86.575 23.515 86.575 23.515 86.955 22.17 86.955 22.17 86.135 21.94 86.135 21.94 86.955 21.105 86.955 21.105 86.555 20.775 86.555 20.775 86.955 18.815 86.955 18.815 86.42 18.305 86.42 18.305 86.955 16.965 86.955 16.965 86.495 16.66 86.495 16.66 86.955 15.175 86.955 15.175 86.515 14.985 86.515 14.985 86.955 13.085 86.955 13.085 86.495 12.755 86.495 12.755 86.955 10.155 86.955 10.155 86.595 9.825 86.595 9.825 86.955 9.125 86.955 9.125 86.575 8.795 86.575 8.795 86.955 7.805 86.955 7.805 86.155 7.475 86.155 7.475 86.955 6.965 86.955 6.965 86.475 6.635 86.475 6.635 86.955 6.125 86.955 6.125 86.475 5.795 86.475 5.795 86.955 5.285 86.955 5.285 86.475 4.955 86.475 4.955 86.955 4.445 86.955 4.445 86.475 4.115 86.475 4.115 86.955 3.605 86.955 3.605 86.475 3.275 86.475 3.275 86.955 0 86.955 0 87.125 ; + RECT 133.4 84.235 134.32 84.405 ; + RECT 0 84.235 1.84 84.405 ; + RECT 133.4 81.515 134.32 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 133.4 78.795 134.32 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 133.4 76.075 134.32 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 133.4 73.355 134.32 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 133.4 70.635 134.32 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 133.4 67.915 134.32 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 133.4 65.195 134.32 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 133.4 62.475 134.32 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 133.4 59.755 134.32 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 133.4 57.035 134.32 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 133.4 54.315 134.32 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 133.4 51.595 134.32 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 133.4 48.875 134.32 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 133.4 46.155 134.32 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 133.4 43.435 134.32 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 133.4 40.715 134.32 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 133.4 37.995 134.32 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 133.4 35.275 134.32 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 133.4 32.555 134.32 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 132.48 29.835 134.32 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 132.48 27.115 134.32 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 133.4 24.395 134.32 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 133.4 21.675 134.32 21.845 ; + RECT 0 21.675 1.84 21.845 ; + RECT 133.4 18.955 134.32 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 133.4 16.235 134.32 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 133.4 13.515 134.32 13.685 ; + RECT 0 13.515 1.84 13.685 ; + POLYGON 8.42 11.785 8.42 10.965 9.565 10.965 9.565 11.5 10.075 11.5 10.075 10.965 12.035 10.965 12.035 11.365 12.365 11.365 12.365 10.965 13.395 10.965 13.395 11.365 13.725 11.365 13.725 10.965 15.685 10.965 15.685 11.5 16.195 11.5 16.195 10.965 17.535 10.965 17.535 11.345 17.865 11.345 17.865 10.965 18.565 10.965 18.565 11.325 18.895 11.325 18.895 10.965 21.495 10.965 21.495 11.425 21.825 11.425 21.825 10.965 23.725 10.965 23.725 11.405 23.915 11.405 23.915 10.965 25.4 10.965 25.4 11.425 25.705 11.425 25.705 10.965 26.745 10.965 26.745 11.345 27.075 11.345 27.075 10.965 28.115 10.965 28.115 11.345 28.445 11.345 28.445 10.965 29.145 10.965 29.145 11.325 29.475 11.325 29.475 10.965 32.075 10.965 32.075 11.425 32.405 11.425 32.405 10.965 34.305 10.965 34.305 11.405 34.495 11.405 34.495 10.965 35.98 10.965 35.98 11.425 36.285 11.425 36.285 10.965 36.8 10.965 36.8 10.795 0 10.795 0 10.965 3.315 10.965 3.315 11.765 3.645 11.765 3.645 10.965 4.155 10.965 4.155 11.445 4.485 11.445 4.485 10.965 4.995 10.965 4.995 11.445 5.325 11.445 5.325 10.965 5.915 10.965 5.915 11.445 6.085 11.445 6.085 10.965 6.755 10.965 6.755 11.445 6.925 11.445 6.925 10.965 8.19 10.965 8.19 11.785 ; + POLYGON 118.635 11.5 118.635 10.965 120.595 10.965 120.595 11.365 120.925 11.365 120.925 10.965 122.415 10.965 122.415 11.345 122.745 11.345 122.745 10.965 123.445 10.965 123.445 11.325 123.775 11.325 123.775 10.965 126.375 10.965 126.375 11.425 126.705 11.425 126.705 10.965 128.605 10.965 128.605 11.405 128.795 11.405 128.795 10.965 130.28 10.965 130.28 11.425 130.585 11.425 130.585 10.965 134.32 10.965 134.32 10.795 102.58 10.795 102.58 10.965 103.405 10.965 103.405 11.5 103.915 11.5 103.915 10.965 105.875 10.965 105.875 11.365 106.205 11.365 106.205 10.965 107.235 10.965 107.235 11.345 107.565 11.345 107.565 10.965 108.265 10.965 108.265 11.325 108.595 11.325 108.595 10.965 111.195 10.965 111.195 11.425 111.525 11.425 111.525 10.965 113.425 10.965 113.425 11.405 113.615 11.405 113.615 10.965 115.1 10.965 115.1 11.425 115.405 11.425 115.405 10.965 116.445 10.965 116.445 11.345 116.775 11.345 116.775 10.965 118.125 10.965 118.125 11.5 ; + RECT 100.28 8.075 103.96 8.245 ; + RECT 30.36 8.075 32.2 8.245 ; + RECT 100.28 5.355 103.96 5.525 ; + RECT 30.36 5.355 32.2 5.525 ; + RECT 102.12 2.635 103.96 2.805 ; + RECT 30.36 2.635 34.04 2.805 ; + POLYGON 97.965 0.885 97.965 0.085 103.96 0.085 103.96 -0.085 30.36 -0.085 30.36 0.085 34.515 0.085 34.515 0.885 34.845 0.885 34.845 0.085 35.355 0.085 35.355 0.565 35.685 0.565 35.685 0.085 36.195 0.085 36.195 0.565 36.525 0.565 36.525 0.085 37.035 0.085 37.035 0.565 37.365 0.565 37.365 0.085 37.875 0.085 37.875 0.565 38.205 0.565 38.205 0.085 38.715 0.085 38.715 0.565 39.045 0.565 39.045 0.085 40.075 0.085 40.075 0.485 40.405 0.485 40.405 0.085 42.365 0.085 42.365 0.62 42.875 0.62 42.875 0.085 44.215 0.085 44.215 0.465 44.545 0.465 44.545 0.085 45.245 0.085 45.245 0.445 45.575 0.445 45.575 0.085 48.175 0.085 48.175 0.545 48.505 0.545 48.505 0.085 50.405 0.085 50.405 0.525 50.595 0.525 50.595 0.085 52.08 0.085 52.08 0.545 52.385 0.545 52.385 0.085 53.425 0.085 53.425 0.465 53.755 0.465 53.755 0.085 54.755 0.085 54.755 0.885 55.085 0.885 55.085 0.085 55.595 0.085 55.595 0.565 55.925 0.565 55.925 0.085 56.435 0.085 56.435 0.565 56.765 0.565 56.765 0.085 57.275 0.085 57.275 0.565 57.605 0.565 57.605 0.085 58.115 0.085 58.115 0.565 58.445 0.565 58.445 0.085 58.955 0.085 58.955 0.565 59.285 0.565 59.285 0.085 60.325 0.085 60.325 0.565 60.565 0.565 60.565 0.085 61.155 0.085 61.155 0.565 61.485 0.565 61.485 0.085 61.995 0.085 61.995 0.885 62.325 0.885 62.325 0.085 62.815 0.085 62.815 0.545 63.07 0.545 63.07 0.085 63.74 0.085 63.74 0.545 63.91 0.545 63.91 0.085 64.58 0.085 64.58 0.545 64.75 0.545 64.75 0.085 65.42 0.085 65.42 0.545 65.59 0.545 65.59 0.085 66.26 0.085 66.26 0.545 66.565 0.545 66.565 0.085 67.215 0.085 67.215 0.565 67.545 0.565 67.545 0.085 68.055 0.085 68.055 0.565 68.385 0.565 68.385 0.085 68.895 0.085 68.895 0.565 69.225 0.565 69.225 0.085 69.735 0.085 69.735 0.565 70.065 0.565 70.065 0.085 70.575 0.085 70.575 0.565 70.905 0.565 70.905 0.085 71.415 0.085 71.415 0.885 71.745 0.885 71.745 0.085 72.735 0.085 72.735 0.565 73.065 0.565 73.065 0.085 73.575 0.085 73.575 0.565 73.905 0.565 73.905 0.085 74.415 0.085 74.415 0.565 74.745 0.565 74.745 0.085 75.255 0.085 75.255 0.565 75.585 0.565 75.585 0.085 76.095 0.085 76.095 0.565 76.425 0.565 76.425 0.085 76.935 0.085 76.935 0.885 77.265 0.885 77.265 0.085 78.255 0.085 78.255 0.565 78.585 0.565 78.585 0.085 79.095 0.085 79.095 0.565 79.425 0.565 79.425 0.085 79.935 0.085 79.935 0.565 80.265 0.565 80.265 0.085 80.775 0.085 80.775 0.565 81.105 0.565 81.105 0.085 81.615 0.085 81.615 0.565 81.945 0.565 81.945 0.085 82.455 0.085 82.455 0.885 82.785 0.885 82.785 0.085 83.395 0.085 83.395 0.545 83.7 0.545 83.7 0.085 84.37 0.085 84.37 0.545 84.54 0.545 84.54 0.085 85.21 0.085 85.21 0.545 85.38 0.545 85.38 0.085 86.05 0.085 86.05 0.545 86.22 0.545 86.22 0.085 86.89 0.085 86.89 0.545 87.145 0.545 87.145 0.085 87.875 0.085 87.875 0.885 88.205 0.885 88.205 0.085 88.715 0.085 88.715 0.565 89.045 0.565 89.045 0.085 89.555 0.085 89.555 0.565 89.885 0.565 89.885 0.085 90.395 0.085 90.395 0.565 90.725 0.565 90.725 0.085 91.235 0.085 91.235 0.565 91.565 0.565 91.565 0.085 92.075 0.085 92.075 0.565 92.405 0.565 92.405 0.085 93.435 0.085 93.435 0.565 93.765 0.565 93.765 0.085 94.275 0.085 94.275 0.565 94.605 0.565 94.605 0.085 95.115 0.085 95.115 0.565 95.445 0.565 95.445 0.085 95.955 0.085 95.955 0.565 96.285 0.565 96.285 0.085 96.795 0.085 96.795 0.565 97.125 0.565 97.125 0.085 97.635 0.085 97.635 0.885 ; + POLYGON 103.79 97.75 103.79 86.87 134.15 86.87 134.15 11.05 103.79 11.05 103.79 0.17 30.53 0.17 30.53 11.05 0.17 11.05 0.17 86.87 30.53 86.87 30.53 97.75 ; + LAYER via ; + RECT 89.165 97.725 89.315 97.875 ; + RECT 59.725 97.725 59.875 97.875 ; + RECT 80.195 97.335 80.345 97.485 ; + RECT 61.795 97.335 61.945 97.485 ; + RECT 123.895 11.315 124.045 11.465 ; + RECT 75.135 0.435 75.285 0.585 ; + RECT 68.235 0.435 68.385 0.585 ; + RECT 57.195 0.435 57.345 0.585 ; + RECT 89.165 0.045 89.315 0.195 ; + RECT 59.725 0.045 59.875 0.195 ; + LAYER via2 ; + RECT 89.14 97.7 89.34 97.9 ; + RECT 59.7 97.7 59.9 97.9 ; + RECT 96.73 97.48 96.93 97.68 ; + RECT 95.81 97.48 96.01 97.68 ; + RECT 31.41 97.48 31.61 97.68 ; + RECT 125.71 86.6 125.91 86.8 ; + RECT 26.35 86.6 26.55 86.8 ; + RECT 15.77 86.6 15.97 86.8 ; + RECT 13.93 86.6 14.13 86.8 ; + RECT 133.07 62.12 133.27 62.32 ; + RECT 1.05 52.6 1.25 52.8 ; + RECT 133.07 45.8 133.27 46 ; + RECT 1.05 44.44 1.25 44.64 ; + RECT 133.07 41.72 133.27 41.92 ; + RECT 24.05 11.12 24.25 11.32 ; + RECT 18.07 11.12 18.27 11.32 ; + RECT 62.69 0.24 62.89 0.44 ; + RECT 89.14 0.02 89.34 0.22 ; + RECT 59.7 0.02 59.9 0.22 ; + LAYER via3 ; + RECT 89.14 97.7 89.34 97.9 ; + RECT 59.7 97.7 59.9 97.9 ; + RECT 86.84 97.48 87.04 97.68 ; + RECT 70.28 97.48 70.48 97.68 ; + RECT 65.68 97.48 65.88 97.68 ; + RECT 61.08 97.48 61.28 97.68 ; + RECT 50.04 97.48 50.24 97.68 ; + RECT 92.36 0.92 92.56 1.12 ; + RECT 78.56 0.92 78.76 1.12 ; + RECT 64.76 0.24 64.96 0.44 ; + RECT 63.84 0.24 64.04 0.44 ; + RECT 89.14 0.02 89.34 0.22 ; + RECT 59.7 0.02 59.9 0.22 ; + LAYER OVERLAP ; + POLYGON 30.36 0 30.36 10.88 0 10.88 0 87.04 30.36 87.04 30.36 97.92 103.96 97.92 103.96 87.04 134.32 87.04 134.32 10.88 103.96 10.88 103.96 0 ; + END +END sb_1__1_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_1__2__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_1__2__icv_in_design.lef new file mode 100644 index 0000000..55b78f1 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_1__2__icv_in_design.lef @@ -0,0 +1,2337 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_1__2_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 134.32 BY 87.04 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.32 86.555 67.46 87.04 ; + END + END pReset[0] + PIN chanx_right_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 43.03 134.32 43.33 ; + END + END chanx_right_in[0] + PIN chanx_right_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 77.28 134.32 77.42 ; + END + END chanx_right_in[1] + PIN chanx_right_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 61.3 134.32 61.44 ; + END + END chanx_right_in[2] + PIN chanx_right_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 50.42 134.32 50.56 ; + END + END chanx_right_in[3] + PIN chanx_right_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 55.27 134.32 55.57 ; + END + END chanx_right_in[4] + PIN chanx_right_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 53.48 134.32 53.62 ; + END + END chanx_right_in[5] + PIN chanx_right_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 56.63 134.32 56.93 ; + END + END chanx_right_in[6] + PIN chanx_right_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 18.12 134.32 18.26 ; + END + END chanx_right_in[7] + PIN chanx_right_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 36.23 134.32 36.53 ; + END + END chanx_right_in[8] + PIN chanx_right_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 52.46 134.32 52.6 ; + END + END chanx_right_in[9] + PIN chanx_right_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 32.15 134.32 32.45 ; + END + END chanx_right_in[10] + PIN chanx_right_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 34.87 134.32 35.17 ; + END + END chanx_right_in[11] + PIN chanx_right_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 36.14 134.32 36.28 ; + END + END chanx_right_in[12] + PIN chanx_right_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 49.74 134.32 49.88 ; + END + END chanx_right_in[13] + PIN chanx_right_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 60.62 134.32 60.76 ; + END + END chanx_right_in[14] + PIN chanx_right_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 33.51 134.32 33.81 ; + END + END chanx_right_in[15] + PIN chanx_right_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 53.91 134.32 54.21 ; + END + END chanx_right_in[16] + PIN chanx_right_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 23.56 134.32 23.7 ; + END + END chanx_right_in[17] + PIN chanx_right_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 31.72 134.32 31.86 ; + END + END chanx_right_in[18] + PIN chanx_right_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 55.86 134.32 56 ; + END + END chanx_right_in[19] + PIN chanx_right_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 68.78 134.32 68.92 ; + END + END chanx_right_in[20] + PIN chanx_right_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 37.16 134.32 37.3 ; + END + END chanx_right_in[21] + PIN chanx_right_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 52.55 134.32 52.85 ; + END + END chanx_right_in[22] + PIN chanx_right_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 33.76 134.32 33.9 ; + END + END chanx_right_in[23] + PIN chanx_right_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 57.9 134.32 58.04 ; + END + END chanx_right_in[24] + PIN chanx_right_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 45.75 134.32 46.05 ; + END + END chanx_right_in[25] + PIN chanx_right_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 34.44 134.32 34.58 ; + END + END chanx_right_in[26] + PIN chanx_right_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 71.5 134.32 71.64 ; + END + END chanx_right_in[27] + PIN chanx_right_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 41.58 134.32 41.72 ; + END + END chanx_right_in[28] + PIN chanx_right_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 69.46 134.32 69.6 ; + END + END chanx_right_in[29] + PIN right_top_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 42.26 134.32 42.4 ; + END + END right_top_grid_pin_1_[0] + PIN right_bottom_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 129.88 10.88 130.02 11.365 ; + END + END right_bottom_grid_pin_36_[0] + PIN right_bottom_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 12.68 134.32 12.82 ; + END + END right_bottom_grid_pin_37_[0] + PIN right_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 121.14 10.88 121.28 11.365 ; + END + END right_bottom_grid_pin_38_[0] + PIN right_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 103.16 5.63 103.96 5.93 ; + END + END right_bottom_grid_pin_39_[0] + PIN right_bottom_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 123.9 10.88 124.04 11.365 ; + END + END right_bottom_grid_pin_40_[0] + PIN right_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 1.8 103.96 1.94 ; + END + END right_bottom_grid_pin_41_[0] + PIN right_bottom_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 117.92 10.88 118.06 11.365 ; + END + END right_bottom_grid_pin_42_[0] + PIN right_bottom_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 6.22 103.96 6.36 ; + END + END right_bottom_grid_pin_43_[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 82.19 0 82.49 0.8 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.36 0 55.5 0.485 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 68.39 0 68.69 0.8 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94 0 94.14 0.485 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 80.35 0 80.65 0.8 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 98.75 0 99.05 0.8 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.82 0 78.96 0.485 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 66.55 0 66.85 0.8 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 76.67 0 76.97 0.8 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 84.95 0 85.25 0.8 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 92.31 0 92.61 0.8 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 0 58.26 0.485 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.08 0 93.22 0.485 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 71.15 0 71.45 0.8 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.88 0 84.02 0.485 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 99.52 0 99.66 0.485 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 100.44 0 100.58 0.485 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 64.71 0 65.01 0.8 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.24 0 68.38 0.485 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 85.72 0 85.86 0.485 ; + END + END chany_bottom_in[19] + PIN chany_bottom_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 44.78 0 44.92 0.485 ; + END + END chany_bottom_in[20] + PIN chany_bottom_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 62.87 0 63.17 0.8 ; + END + END chany_bottom_in[21] + PIN chany_bottom_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.04 0 59.18 0.485 ; + END + END chany_bottom_in[22] + PIN chany_bottom_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.48 0 65.62 0.485 ; + END + END chany_bottom_in[23] + PIN chany_bottom_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 90.47 0 90.77 0.8 ; + END + END chany_bottom_in[24] + PIN chany_bottom_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 87.56 0 87.7 0.485 ; + END + END chany_bottom_in[25] + PIN chany_bottom_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 94.15 0 94.45 0.8 ; + END + END chany_bottom_in[26] + PIN chany_bottom_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 91.24 0 91.38 0.485 ; + END + END chany_bottom_in[27] + PIN chany_bottom_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 78.51 0 78.81 0.8 ; + END + END chany_bottom_in[28] + PIN chany_bottom_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.16 0 69.3 0.485 ; + END + END chany_bottom_in[29] + PIN bottom_left_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.44 10.88 8.58 11.365 ; + END + END bottom_left_grid_pin_44_[0] + PIN bottom_left_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.2 10.88 11.34 11.365 ; + END + END bottom_left_grid_pin_45_[0] + PIN bottom_left_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.84 10.88 3.98 11.365 ; + END + END bottom_left_grid_pin_46_[0] + PIN bottom_left_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.94 10.88 20.08 11.365 ; + END + END bottom_left_grid_pin_47_[0] + PIN bottom_left_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.02 10.88 19.16 11.365 ; + END + END bottom_left_grid_pin_48_[0] + PIN bottom_left_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.1 10.88 18.24 11.365 ; + END + END bottom_left_grid_pin_49_[0] + PIN bottom_left_grid_pin_50_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.72 10.88 16.86 11.365 ; + END + END bottom_left_grid_pin_50_[0] + PIN bottom_left_grid_pin_51_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.8 10.88 15.94 11.365 ; + END + END bottom_left_grid_pin_51_[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 38.86 0.595 39 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 24.67 0.8 24.97 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.71 0.8 44.01 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 20.84 0.595 20.98 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 27.39 0.8 27.69 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 23.56 0.595 23.7 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 34.44 0.595 34.58 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 26.03 0.8 26.33 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 22.88 0.595 23.02 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 63.34 0.595 63.48 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 57.9 0.595 58.04 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.3 0.595 44.44 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 35.55 0.8 35.85 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 42.26 0.595 42.4 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 55.18 0.595 55.32 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 50.42 0.595 50.56 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 61.3 0.595 61.44 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.72 0.595 31.86 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 47.02 0.595 47.16 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 31.47 0.8 31.77 ; + END + END chanx_left_in[19] + PIN chanx_left_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.99 0.8 41.29 ; + END + END chanx_left_in[20] + PIN chanx_left_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 34.19 0.8 34.49 ; + END + END chanx_left_in[21] + PIN chanx_left_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 28.32 0.595 28.46 ; + END + END chanx_left_in[22] + PIN chanx_left_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.82 0.595 36.96 ; + END + END chanx_left_in[23] + PIN chanx_left_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 33.76 0.595 33.9 ; + END + END chanx_left_in[24] + PIN chanx_left_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 52.46 0.595 52.6 ; + END + END chanx_left_in[25] + PIN chanx_left_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 58.58 0.595 58.72 ; + END + END chanx_left_in[26] + PIN chanx_left_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 60.62 0.595 60.76 ; + END + END chanx_left_in[27] + PIN chanx_left_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 53.23 0.8 53.53 ; + END + END chanx_left_in[28] + PIN chanx_left_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.14 0.595 36.28 ; + END + END chanx_left_in[29] + PIN left_top_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 51.87 0.8 52.17 ; + END + END left_top_grid_pin_1_[0] + PIN left_bottom_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.12 10.88 12.26 11.365 ; + END + END left_bottom_grid_pin_36_[0] + PIN left_bottom_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.6 10.88 6.74 11.365 ; + END + END left_bottom_grid_pin_37_[0] + PIN left_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.28 10.88 10.42 11.365 ; + END + END left_bottom_grid_pin_38_[0] + PIN left_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.36 10.88 9.5 11.365 ; + END + END left_bottom_grid_pin_39_[0] + PIN left_bottom_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 30.36 5.63 31.16 5.93 ; + END + END left_bottom_grid_pin_40_[0] + PIN left_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 10.88 14.1 11.365 ; + END + END left_bottom_grid_pin_41_[0] + PIN left_bottom_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.52 10.88 7.66 11.365 ; + END + END left_bottom_grid_pin_42_[0] + PIN left_bottom_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.88 10.88 15.02 11.365 ; + END + END left_bottom_grid_pin_43_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 17.44 134.32 17.58 ; + END + END ccff_head[0] + PIN chanx_right_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 47.11 134.32 47.41 ; + END + END chanx_right_out[0] + PIN chanx_right_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 44.98 134.32 45.12 ; + END + END chanx_right_out[1] + PIN chanx_right_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 47.7 134.32 47.84 ; + END + END chanx_right_out[2] + PIN chanx_right_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 48.47 134.32 48.77 ; + END + END chanx_right_out[3] + PIN chanx_right_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 23.99 134.32 24.29 ; + END + END chanx_right_out[4] + PIN chanx_right_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 38.95 134.32 39.25 ; + END + END chanx_right_out[5] + PIN chanx_right_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 25.35 134.32 25.65 ; + END + END chanx_right_out[6] + PIN chanx_right_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 16.51 134.32 16.81 ; + END + END chanx_right_out[7] + PIN chanx_right_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 30.7 134.32 30.84 ; + END + END chanx_right_out[8] + PIN chanx_right_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 38.86 134.32 39 ; + END + END chanx_right_out[9] + PIN chanx_right_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 26.71 134.32 27.01 ; + END + END chanx_right_out[10] + PIN chanx_right_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 25.94 134.32 26.08 ; + END + END chanx_right_out[11] + PIN chanx_right_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 29 134.32 29.14 ; + END + END chanx_right_out[12] + PIN chanx_right_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 22.63 134.32 22.93 ; + END + END chanx_right_out[13] + PIN chanx_right_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 41.67 134.32 41.97 ; + END + END chanx_right_out[14] + PIN chanx_right_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 40.31 134.32 40.61 ; + END + END chanx_right_out[15] + PIN chanx_right_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 17.87 134.32 18.17 ; + END + END chanx_right_out[16] + PIN chanx_right_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 28.32 134.32 28.46 ; + END + END chanx_right_out[17] + PIN chanx_right_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 44.39 134.32 44.69 ; + END + END chanx_right_out[18] + PIN chanx_right_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 20.59 134.32 20.89 ; + END + END chanx_right_out[19] + PIN chanx_right_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 28.07 134.32 28.37 ; + END + END chanx_right_out[20] + PIN chanx_right_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 37.59 134.32 37.89 ; + END + END chanx_right_out[21] + PIN chanx_right_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 44.3 134.32 44.44 ; + END + END chanx_right_out[22] + PIN chanx_right_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 30.79 134.32 31.09 ; + END + END chanx_right_out[23] + PIN chanx_right_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 51.19 134.32 51.49 ; + END + END chanx_right_out[24] + PIN chanx_right_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 49.83 134.32 50.13 ; + END + END chanx_right_out[25] + PIN chanx_right_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 58.58 134.32 58.72 ; + END + END chanx_right_out[26] + PIN chanx_right_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 55.18 134.32 55.32 ; + END + END chanx_right_out[27] + PIN chanx_right_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 19.23 134.32 19.53 ; + END + END chanx_right_out[28] + PIN chanx_right_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 133.52 29.43 134.32 29.73 ; + END + END chanx_right_out[29] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.14 0 75.28 0.485 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.7 0 45.84 0.485 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 42.48 0 42.62 0.485 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.38 0 72.52 0.485 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 86.79 0 87.09 0.8 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.56 0 41.7 0.485 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.14 0 52.28 0.485 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 101.36 0 101.5 0.485 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.64 0 40.78 0.485 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.22 0 74.36 0.485 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.98 0 77.12 0.485 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.64 0 86.78 0.485 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.72 0 62.86 0.485 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 95.99 0 96.29 0.8 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 0 64.7 0.485 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.2 0 57.34 0.485 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 92.16 0 92.3 0.485 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 61.03 0 61.33 0.8 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.64 0 63.78 0.485 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.4 0 66.54 0.485 ; + END + END chany_bottom_out[19] + PIN chany_bottom_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.06 0 76.2 0.485 ; + END + END chany_bottom_out[20] + PIN chany_bottom_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.3 0 73.44 0.485 ; + END + END chany_bottom_out[21] + PIN chany_bottom_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.8 0 84.94 0.485 ; + END + END chany_bottom_out[22] + PIN chany_bottom_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.8 0 61.94 0.485 ; + END + END chany_bottom_out[23] + PIN chany_bottom_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.28 0 56.42 0.485 ; + END + END chany_bottom_out[24] + PIN chany_bottom_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.32 0 67.46 0.485 ; + END + END chany_bottom_out[25] + PIN chany_bottom_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 88.48 0 88.62 0.485 ; + END + END chany_bottom_out[26] + PIN chany_bottom_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.2 0 80.34 0.485 ; + END + END chany_bottom_out[27] + PIN chany_bottom_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.9 0 78.04 0.485 ; + END + END chany_bottom_out[28] + PIN chany_bottom_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 90.32 0 90.46 0.485 ; + END + END chany_bottom_out[29] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 53.48 0.595 53.62 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 48.04 0.595 48.18 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 56.2 0.595 56.34 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.79 0.8 48.09 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 50.51 0.8 50.81 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 49.15 0.8 49.45 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.91 0.8 37.21 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 18.12 0.595 18.26 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 30.11 0.8 30.41 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 28.75 0.8 29.05 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 38.27 0.8 38.57 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 32.83 0.8 33.13 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 25.6 0.595 25.74 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 15.4 0.595 15.54 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 46.43 0.8 46.73 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 45.07 0.8 45.37 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 14.72 0.595 14.86 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 26.28 0.595 26.42 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 64.02 0.595 64.16 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 18.55 0.8 18.85 ; + END + END chanx_left_out[19] + PIN chanx_left_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 41.58 0.595 41.72 ; + END + END chanx_left_out[20] + PIN chanx_left_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 39.54 0.595 39.68 ; + END + END chanx_left_out[21] + PIN chanx_left_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 23.31 0.8 23.61 ; + END + END chanx_left_out[22] + PIN chanx_left_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.04 0.595 31.18 ; + END + END chanx_left_out[23] + PIN chanx_left_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.35 0.8 42.65 ; + END + END chanx_left_out[24] + PIN chanx_left_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.98 0.595 45.12 ; + END + END chanx_left_out[25] + PIN chanx_left_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 39.63 0.8 39.93 ; + END + END chanx_left_out[26] + PIN chanx_left_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 49.74 0.595 49.88 ; + END + END chanx_left_out[27] + PIN chanx_left_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 17.19 0.8 17.49 ; + END + END chanx_left_out[28] + PIN chanx_left_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 29 0.595 29.14 ; + END + END chanx_left_out[29] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 21.95 0.8 22.25 ; + END + END ccff_tail[0] + PIN SC_IN_BOT + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 19.91 0.8 20.21 ; + END + END SC_IN_BOT + PIN SC_OUT_BOT + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 22.54 134.32 22.68 ; + END + END SC_OUT_BOT + PIN pReset_S_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.88 0 61.02 0.485 ; + END + END pReset_S_in + PIN pReset_E_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 39.88 134.32 40.02 ; + END + END pReset_E_in + PIN pReset_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 17.44 0.595 17.58 ; + END + END pReset_W_in + PIN pReset_W_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 15.15 0.8 15.45 ; + END + END pReset_W_out + PIN pReset_E_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 133.725 47.02 134.32 47.16 ; + END + END pReset_E_out + PIN prog_clk_0_S_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 43.4 0 43.54 0.485 ; + END + END prog_clk_0_S_in + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 26.96 3.2 30.16 ; + RECT 131.12 26.96 134.32 30.16 ; + RECT 0 67.76 3.2 70.96 ; + RECT 131.12 67.76 134.32 70.96 ; + LAYER met4 ; + RECT 44.78 0 45.38 0.6 ; + RECT 74.22 0 74.82 0.6 ; + RECT 13.5 10.88 14.1 11.48 ; + RECT 120.22 10.88 120.82 11.48 ; + RECT 13.5 86.44 14.1 87.04 ; + RECT 44.78 86.44 45.38 87.04 ; + RECT 74.22 86.44 74.82 87.04 ; + RECT 120.22 86.44 120.82 87.04 ; + LAYER met1 ; + RECT 30.36 2.48 30.84 2.96 ; + RECT 103.48 2.48 103.96 2.96 ; + RECT 30.36 7.92 30.84 8.4 ; + RECT 103.48 7.92 103.96 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 133.84 13.36 134.32 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 133.84 18.8 134.32 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 133.84 24.24 134.32 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 133.84 29.68 134.32 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 133.84 35.12 134.32 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 133.84 40.56 134.32 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 133.84 46 134.32 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 133.84 51.44 134.32 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 133.84 56.88 134.32 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 133.84 62.32 134.32 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 133.84 67.76 134.32 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 133.84 73.2 134.32 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 133.84 78.64 134.32 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 133.84 84.08 134.32 84.56 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 47.36 3.2 50.56 ; + RECT 131.12 47.36 134.32 50.56 ; + LAYER met4 ; + RECT 59.5 0 60.1 0.6 ; + RECT 88.94 0 89.54 0.6 ; + RECT 59.5 86.44 60.1 87.04 ; + RECT 88.94 86.44 89.54 87.04 ; + LAYER met1 ; + RECT 30.36 -0.24 30.84 0.24 ; + RECT 103.48 -0.24 103.96 0.24 ; + RECT 30.36 5.2 30.84 5.68 ; + RECT 103.48 5.2 103.96 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 133.84 10.64 134.32 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 133.84 16.08 134.32 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 133.84 21.52 134.32 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 133.84 26.96 134.32 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 133.84 32.4 134.32 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 133.84 37.84 134.32 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 133.84 43.28 134.32 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 133.84 48.72 134.32 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 133.84 54.16 134.32 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 133.84 59.6 134.32 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 133.84 65.04 134.32 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 133.84 70.48 134.32 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 133.84 75.92 134.32 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 133.84 81.36 134.32 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 133.84 86.8 134.32 87.28 ; + END + END VSS + OBS + LAYER met2 ; + RECT 89.1 86.735 89.38 87.105 ; + RECT 59.66 86.735 59.94 87.105 ; + POLYGON 44.46 20.64 44.46 0.24 44.5 0.24 44.5 0.1 44.32 0.1 44.32 20.64 ; + POLYGON 64.24 17.58 64.24 0.525 64.31 0.525 64.31 0.155 64.03 0.155 64.03 0.525 64.1 0.525 64.1 17.58 ; + POLYGON 118.52 13.33 118.52 11.405 118.59 11.405 118.59 11.035 118.31 11.035 118.31 11.405 118.38 11.405 118.38 13.33 ; + RECT 121.54 11.57 121.8 11.89 ; + RECT 9.76 11.23 10.02 11.55 ; + POLYGON 42.16 3.81 42.16 0.24 42.2 0.24 42.2 0.1 42.02 0.1 42.02 3.81 ; + RECT 91.64 0.69 91.9 1.01 ; + RECT 75.54 0.69 75.8 1.01 ; + RECT 89.1 -0.065 89.38 0.305 ; + RECT 59.66 -0.065 59.94 0.305 ; + POLYGON 134.04 86.76 134.04 11.16 130.3 11.16 130.3 11.645 129.6 11.645 129.6 11.16 124.32 11.16 124.32 11.645 123.62 11.645 123.62 11.16 121.56 11.16 121.56 11.645 120.86 11.645 120.86 11.16 118.34 11.16 118.34 11.645 117.64 11.645 117.64 11.16 103.68 11.16 103.68 0.28 101.78 0.28 101.78 0.765 101.08 0.765 101.08 0.28 100.86 0.28 100.86 0.765 100.16 0.765 100.16 0.28 99.94 0.28 99.94 0.765 99.24 0.765 99.24 0.28 94.42 0.28 94.42 0.765 93.72 0.765 93.72 0.28 93.5 0.28 93.5 0.765 92.8 0.765 92.8 0.28 92.58 0.28 92.58 0.765 91.88 0.765 91.88 0.28 91.66 0.28 91.66 0.765 90.96 0.765 90.96 0.28 90.74 0.28 90.74 0.765 90.04 0.765 90.04 0.28 88.9 0.28 88.9 0.765 88.2 0.765 88.2 0.28 87.98 0.28 87.98 0.765 87.28 0.765 87.28 0.28 87.06 0.28 87.06 0.765 86.36 0.765 86.36 0.28 86.14 0.28 86.14 0.765 85.44 0.765 85.44 0.28 85.22 0.28 85.22 0.765 84.52 0.765 84.52 0.28 84.3 0.28 84.3 0.765 83.6 0.765 83.6 0.28 80.62 0.28 80.62 0.765 79.92 0.765 79.92 0.28 79.24 0.28 79.24 0.765 78.54 0.765 78.54 0.28 78.32 0.28 78.32 0.765 77.62 0.765 77.62 0.28 77.4 0.28 77.4 0.765 76.7 0.765 76.7 0.28 76.48 0.28 76.48 0.765 75.78 0.765 75.78 0.28 75.56 0.28 75.56 0.765 74.86 0.765 74.86 0.28 74.64 0.28 74.64 0.765 73.94 0.765 73.94 0.28 73.72 0.28 73.72 0.765 73.02 0.765 73.02 0.28 72.8 0.28 72.8 0.765 72.1 0.765 72.1 0.28 69.58 0.28 69.58 0.765 68.88 0.765 68.88 0.28 68.66 0.28 68.66 0.765 67.96 0.765 67.96 0.28 67.74 0.28 67.74 0.765 67.04 0.765 67.04 0.28 66.82 0.28 66.82 0.765 66.12 0.765 66.12 0.28 65.9 0.28 65.9 0.765 65.2 0.765 65.2 0.28 64.98 0.28 64.98 0.765 64.28 0.765 64.28 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 63.14 0.28 63.14 0.765 62.44 0.765 62.44 0.28 62.22 0.28 62.22 0.765 61.52 0.765 61.52 0.28 61.3 0.28 61.3 0.765 60.6 0.765 60.6 0.28 59.46 0.28 59.46 0.765 58.76 0.765 58.76 0.28 58.54 0.28 58.54 0.765 57.84 0.765 57.84 0.28 57.62 0.28 57.62 0.765 56.92 0.765 56.92 0.28 56.7 0.28 56.7 0.765 56 0.765 56 0.28 55.78 0.28 55.78 0.765 55.08 0.765 55.08 0.28 52.56 0.28 52.56 0.765 51.86 0.765 51.86 0.28 46.12 0.28 46.12 0.765 45.42 0.765 45.42 0.28 45.2 0.28 45.2 0.765 44.5 0.765 44.5 0.28 43.82 0.28 43.82 0.765 43.12 0.765 43.12 0.28 42.9 0.28 42.9 0.765 42.2 0.765 42.2 0.28 41.98 0.28 41.98 0.765 41.28 0.765 41.28 0.28 41.06 0.28 41.06 0.765 40.36 0.765 40.36 0.28 30.64 0.28 30.64 11.16 20.36 11.16 20.36 11.645 19.66 11.645 19.66 11.16 19.44 11.16 19.44 11.645 18.74 11.645 18.74 11.16 18.52 11.16 18.52 11.645 17.82 11.645 17.82 11.16 17.14 11.16 17.14 11.645 16.44 11.645 16.44 11.16 16.22 11.16 16.22 11.645 15.52 11.645 15.52 11.16 15.3 11.16 15.3 11.645 14.6 11.645 14.6 11.16 14.38 11.16 14.38 11.645 13.68 11.645 13.68 11.16 12.54 11.16 12.54 11.645 11.84 11.645 11.84 11.16 11.62 11.16 11.62 11.645 10.92 11.645 10.92 11.16 10.7 11.16 10.7 11.645 10 11.645 10 11.16 9.78 11.16 9.78 11.645 9.08 11.645 9.08 11.16 8.86 11.16 8.86 11.645 8.16 11.645 8.16 11.16 7.94 11.16 7.94 11.645 7.24 11.645 7.24 11.16 7.02 11.16 7.02 11.645 6.32 11.645 6.32 11.16 4.26 11.16 4.26 11.645 3.56 11.645 3.56 11.16 0.28 11.16 0.28 86.76 67.04 86.76 67.04 86.275 67.74 86.275 67.74 86.76 ; + LAYER met3 ; + POLYGON 89.405 87.085 89.405 87.08 89.62 87.08 89.62 86.76 89.405 86.76 89.405 86.755 89.075 86.755 89.075 86.76 88.86 86.76 88.86 87.08 89.075 87.08 89.075 87.085 ; + POLYGON 59.965 87.085 59.965 87.08 60.18 87.08 60.18 86.76 59.965 86.76 59.965 86.755 59.635 86.755 59.635 86.76 59.42 86.76 59.42 87.08 59.635 87.08 59.635 87.085 ; + POLYGON 133.12 45.37 133.12 45.35 133.67 45.35 133.67 45.07 118.99 45.07 118.99 45.37 ; + POLYGON 1.315 33.825 1.315 33.81 2.45 33.81 2.45 33.51 1.315 33.51 1.315 33.495 0.985 33.495 0.985 33.825 ; + POLYGON 124.135 11.385 124.135 11.055 123.805 11.055 123.805 11.07 118.615 11.07 118.615 11.055 118.285 11.055 118.285 11.385 118.615 11.385 118.615 11.37 123.805 11.37 123.805 11.385 ; + POLYGON 9.595 11.385 9.595 11.37 37.64 11.37 37.64 11.07 9.595 11.07 9.595 11.055 9.265 11.055 9.265 11.385 ; + POLYGON 103.69 11.38 103.69 11.06 103.31 11.06 103.31 11.07 95.76 11.07 95.76 11.37 103.31 11.37 103.31 11.38 ; + POLYGON 61.33 1.17 61.33 0.5 61.37 0.5 61.37 0.18 60.99 0.18 60.99 0.5 61.03 0.5 61.03 1.17 ; + POLYGON 64.335 0.505 64.335 0.49 64.67 0.49 64.67 0.5 65.05 0.5 65.05 0.18 64.67 0.18 64.67 0.19 64.335 0.19 64.335 0.175 64.005 0.175 64.005 0.505 ; + POLYGON 89.405 0.285 89.405 0.28 89.62 0.28 89.62 -0.04 89.405 -0.04 89.405 -0.045 89.075 -0.045 89.075 -0.04 88.86 -0.04 88.86 0.28 89.075 0.28 89.075 0.285 ; + POLYGON 59.965 0.285 59.965 0.28 60.18 0.28 60.18 -0.04 59.965 -0.04 59.965 -0.045 59.635 -0.045 59.635 -0.04 59.42 -0.04 59.42 0.28 59.635 0.28 59.635 0.285 ; + POLYGON 133.92 86.64 133.92 57.33 133.12 57.33 133.12 56.23 133.92 56.23 133.92 55.97 133.12 55.97 133.12 54.87 133.92 54.87 133.92 54.61 133.12 54.61 133.12 53.51 133.92 53.51 133.92 53.25 133.12 53.25 133.12 52.15 133.92 52.15 133.92 51.89 133.12 51.89 133.12 50.79 133.92 50.79 133.92 50.53 133.12 50.53 133.12 49.43 133.92 49.43 133.92 49.17 133.12 49.17 133.12 48.07 133.92 48.07 133.92 47.81 133.12 47.81 133.12 46.71 133.92 46.71 133.92 46.45 133.12 46.45 133.12 45.35 133.92 45.35 133.92 45.09 133.12 45.09 133.12 43.99 133.92 43.99 133.92 43.73 133.12 43.73 133.12 42.63 133.92 42.63 133.92 42.37 133.12 42.37 133.12 41.27 133.92 41.27 133.92 41.01 133.12 41.01 133.12 39.91 133.92 39.91 133.92 39.65 133.12 39.65 133.12 38.55 133.92 38.55 133.92 38.29 133.12 38.29 133.12 37.19 133.92 37.19 133.92 36.93 133.12 36.93 133.12 35.83 133.92 35.83 133.92 35.57 133.12 35.57 133.12 34.47 133.92 34.47 133.92 34.21 133.12 34.21 133.12 33.11 133.92 33.11 133.92 32.85 133.12 32.85 133.12 31.75 133.92 31.75 133.92 31.49 133.12 31.49 133.12 30.39 133.92 30.39 133.92 30.13 133.12 30.13 133.12 29.03 133.92 29.03 133.92 28.77 133.12 28.77 133.12 27.67 133.92 27.67 133.92 27.41 133.12 27.41 133.12 26.31 133.92 26.31 133.92 26.05 133.12 26.05 133.12 24.95 133.92 24.95 133.92 24.69 133.12 24.69 133.12 23.59 133.92 23.59 133.92 23.33 133.12 23.33 133.12 22.23 133.92 22.23 133.92 21.29 133.12 21.29 133.12 20.19 133.92 20.19 133.92 19.93 133.12 19.93 133.12 18.83 133.92 18.83 133.92 18.57 133.12 18.57 133.12 17.47 133.92 17.47 133.92 17.21 133.12 17.21 133.12 16.11 133.92 16.11 133.92 11.28 103.56 11.28 103.56 6.33 102.76 6.33 102.76 5.23 103.56 5.23 103.56 0.4 30.76 0.4 30.76 5.23 31.56 5.23 31.56 6.33 30.76 6.33 30.76 11.28 0.4 11.28 0.4 14.75 1.2 14.75 1.2 15.85 0.4 15.85 0.4 16.79 1.2 16.79 1.2 17.89 0.4 17.89 0.4 18.15 1.2 18.15 1.2 19.25 0.4 19.25 0.4 19.51 1.2 19.51 1.2 20.61 0.4 20.61 0.4 21.55 1.2 21.55 1.2 22.65 0.4 22.65 0.4 22.91 1.2 22.91 1.2 24.01 0.4 24.01 0.4 24.27 1.2 24.27 1.2 25.37 0.4 25.37 0.4 25.63 1.2 25.63 1.2 26.73 0.4 26.73 0.4 26.99 1.2 26.99 1.2 28.09 0.4 28.09 0.4 28.35 1.2 28.35 1.2 29.45 0.4 29.45 0.4 29.71 1.2 29.71 1.2 30.81 0.4 30.81 0.4 31.07 1.2 31.07 1.2 32.17 0.4 32.17 0.4 32.43 1.2 32.43 1.2 33.53 0.4 33.53 0.4 33.79 1.2 33.79 1.2 34.89 0.4 34.89 0.4 35.15 1.2 35.15 1.2 36.25 0.4 36.25 0.4 36.51 1.2 36.51 1.2 37.61 0.4 37.61 0.4 37.87 1.2 37.87 1.2 38.97 0.4 38.97 0.4 39.23 1.2 39.23 1.2 40.33 0.4 40.33 0.4 40.59 1.2 40.59 1.2 41.69 0.4 41.69 0.4 41.95 1.2 41.95 1.2 43.05 0.4 43.05 0.4 43.31 1.2 43.31 1.2 44.41 0.4 44.41 0.4 44.67 1.2 44.67 1.2 45.77 0.4 45.77 0.4 46.03 1.2 46.03 1.2 47.13 0.4 47.13 0.4 47.39 1.2 47.39 1.2 48.49 0.4 48.49 0.4 48.75 1.2 48.75 1.2 49.85 0.4 49.85 0.4 50.11 1.2 50.11 1.2 51.21 0.4 51.21 0.4 51.47 1.2 51.47 1.2 52.57 0.4 52.57 0.4 52.83 1.2 52.83 1.2 53.93 0.4 53.93 0.4 86.64 ; + LAYER met1 ; + POLYGON 133.56 87.28 133.56 86.8 89.4 86.8 89.4 86.79 89.08 86.79 89.08 86.8 59.96 86.8 59.96 86.79 59.64 86.79 59.64 86.8 0.76 86.8 0.76 87.28 ; + POLYGON 4.44 59.4 4.44 59.26 0.665 59.26 0.665 59 0.525 59 0.525 59.4 ; + POLYGON 0.665 28.04 0.665 27.78 6.74 27.78 6.74 27.64 0.525 27.64 0.525 28.04 ; + RECT 72.36 10.64 133.56 11.12 ; + RECT 0.76 10.64 71.16 11.12 ; + POLYGON 89.4 0.25 89.4 0.24 103.2 0.24 103.2 -0.24 31.12 -0.24 31.12 0.24 59.64 0.24 59.64 0.25 59.96 0.25 59.96 0.24 89.08 0.24 89.08 0.25 ; + POLYGON 133.56 86.76 133.56 86.52 134.04 86.52 134.04 84.84 133.56 84.84 133.56 83.8 134.04 83.8 134.04 82.12 133.56 82.12 133.56 81.08 134.04 81.08 134.04 79.4 133.56 79.4 133.56 78.36 134.04 78.36 134.04 77.7 133.445 77.7 133.445 77 134.04 77 134.04 76.68 133.56 76.68 133.56 75.64 134.04 75.64 134.04 73.96 133.56 73.96 133.56 72.92 134.04 72.92 134.04 71.92 133.445 71.92 133.445 71.22 133.56 71.22 133.56 70.2 134.04 70.2 134.04 69.88 133.445 69.88 133.445 68.5 133.56 68.5 133.56 67.48 134.04 67.48 134.04 65.8 133.56 65.8 133.56 64.76 134.04 64.76 134.04 63.08 133.56 63.08 133.56 62.04 134.04 62.04 134.04 61.72 133.445 61.72 133.445 60.34 133.56 60.34 133.56 59.32 134.04 59.32 134.04 59 133.445 59 133.445 57.62 133.56 57.62 133.56 56.6 134.04 56.6 134.04 56.28 133.445 56.28 133.445 54.9 133.56 54.9 133.56 53.9 133.445 53.9 133.445 53.2 134.04 53.2 134.04 52.88 133.445 52.88 133.445 52.18 133.56 52.18 133.56 51.16 134.04 51.16 134.04 50.84 133.445 50.84 133.445 49.46 133.56 49.46 133.56 48.44 134.04 48.44 134.04 48.12 133.445 48.12 133.445 46.74 133.56 46.74 133.56 45.72 134.04 45.72 134.04 45.4 133.445 45.4 133.445 44.02 133.56 44.02 133.56 43 134.04 43 134.04 42.68 133.445 42.68 133.445 41.3 133.56 41.3 133.56 40.3 133.445 40.3 133.445 39.6 134.04 39.6 134.04 39.28 133.445 39.28 133.445 38.58 133.56 38.58 133.56 37.58 133.445 37.58 133.445 36.88 134.04 36.88 134.04 36.56 133.445 36.56 133.445 35.86 133.56 35.86 133.56 34.86 133.445 34.86 133.445 33.48 134.04 33.48 134.04 33.16 133.56 33.16 133.56 32.14 133.445 32.14 133.445 31.44 134.04 31.44 134.04 31.12 133.445 31.12 133.445 30.42 133.56 30.42 133.56 29.42 133.445 29.42 133.445 28.04 134.04 28.04 134.04 27.72 133.56 27.72 133.56 26.68 134.04 26.68 134.04 26.36 133.445 26.36 133.445 25.66 134.04 25.66 134.04 25 133.56 25 133.56 23.98 133.445 23.98 133.445 23.28 134.04 23.28 134.04 22.96 133.445 22.96 133.445 22.26 133.56 22.26 133.56 21.24 134.04 21.24 134.04 19.56 133.56 19.56 133.56 18.54 133.445 18.54 133.445 17.16 134.04 17.16 134.04 16.84 133.56 16.84 133.56 15.8 134.04 15.8 134.04 14.12 133.56 14.12 133.56 13.1 133.445 13.1 133.445 12.4 134.04 12.4 134.04 11.4 133.56 11.4 133.56 11.16 103.68 11.16 103.68 8.68 103.2 8.68 103.2 7.64 103.68 7.64 103.68 6.64 103.085 6.64 103.085 5.94 103.2 5.94 103.2 4.92 103.68 4.92 103.68 3.24 103.2 3.24 103.2 2.22 103.085 2.22 103.085 1.52 103.68 1.52 103.68 0.52 103.2 0.52 103.2 0.28 31.12 0.28 31.12 0.52 30.64 0.52 30.64 2.2 31.12 2.2 31.12 3.24 30.64 3.24 30.64 4.92 31.12 4.92 31.12 5.96 30.64 5.96 30.64 7.64 31.12 7.64 31.12 8.68 30.64 8.68 30.64 11.16 0.76 11.16 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 14.44 0.875 14.44 0.875 15.82 0.76 15.82 0.76 16.84 0.28 16.84 0.28 17.16 0.875 17.16 0.875 18.54 0.76 18.54 0.76 19.56 0.28 19.56 0.28 20.56 0.875 20.56 0.875 21.26 0.76 21.26 0.76 22.28 0.28 22.28 0.28 22.6 0.875 22.6 0.875 23.98 0.76 23.98 0.76 25 0.28 25 0.28 25.32 0.875 25.32 0.875 26.7 0.76 26.7 0.76 27.72 0.28 27.72 0.28 28.04 0.875 28.04 0.875 29.42 0.76 29.42 0.76 30.44 0.28 30.44 0.28 30.76 0.875 30.76 0.875 32.14 0.76 32.14 0.76 33.16 0.28 33.16 0.28 33.48 0.875 33.48 0.875 34.86 0.76 34.86 0.76 35.86 0.875 35.86 0.875 37.24 0.28 37.24 0.28 37.56 0.76 37.56 0.76 38.58 0.875 38.58 0.875 39.96 0.28 39.96 0.28 40.28 0.76 40.28 0.76 41.3 0.875 41.3 0.875 42.68 0.28 42.68 0.28 43 0.76 43 0.76 44.02 0.875 44.02 0.875 45.4 0.28 45.4 0.28 45.72 0.76 45.72 0.76 46.74 0.875 46.74 0.875 47.44 0.28 47.44 0.28 47.76 0.875 47.76 0.875 48.46 0.76 48.46 0.76 49.46 0.875 49.46 0.875 50.84 0.28 50.84 0.28 51.16 0.76 51.16 0.76 52.18 0.875 52.18 0.875 52.88 0.28 52.88 0.28 53.2 0.875 53.2 0.875 53.9 0.76 53.9 0.76 54.9 0.875 54.9 0.875 55.6 0.28 55.6 0.28 55.92 0.875 55.92 0.875 56.62 0.76 56.62 0.76 57.62 0.875 57.62 0.875 59 0.28 59 0.28 59.32 0.76 59.32 0.76 60.34 0.875 60.34 0.875 61.72 0.28 61.72 0.28 62.04 0.76 62.04 0.76 63.06 0.875 63.06 0.875 64.44 0.28 64.44 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 86.76 ; + LAYER met4 ; + POLYGON 103.65 13.41 103.65 11.385 103.665 11.385 103.665 11.055 103.335 11.055 103.335 11.385 103.35 11.385 103.35 13.41 ; + POLYGON 133.92 86.64 133.92 11.28 121.22 11.28 121.22 11.88 119.82 11.88 119.82 11.28 103.56 11.28 103.56 0.4 99.45 0.4 99.45 1.2 98.35 1.2 98.35 0.4 96.69 0.4 96.69 1.2 95.59 1.2 95.59 0.4 94.85 0.4 94.85 1.2 93.75 1.2 93.75 0.4 93.01 0.4 93.01 1.2 91.91 1.2 91.91 0.4 91.17 0.4 91.17 1.2 90.07 1.2 90.07 0.4 89.94 0.4 89.94 1 88.54 1 88.54 0.4 87.49 0.4 87.49 1.2 86.39 1.2 86.39 0.4 85.65 0.4 85.65 1.2 84.55 1.2 84.55 0.4 82.89 0.4 82.89 1.2 81.79 1.2 81.79 0.4 81.05 0.4 81.05 1.2 79.95 1.2 79.95 0.4 79.21 0.4 79.21 1.2 78.11 1.2 78.11 0.4 77.37 0.4 77.37 1.2 76.27 1.2 76.27 0.4 75.22 0.4 75.22 1 73.82 1 73.82 0.4 71.85 0.4 71.85 1.2 70.75 1.2 70.75 0.4 69.09 0.4 69.09 1.2 67.99 1.2 67.99 0.4 67.25 0.4 67.25 1.2 66.15 1.2 66.15 0.4 65.41 0.4 65.41 1.2 64.31 1.2 64.31 0.4 63.57 0.4 63.57 1.2 62.47 1.2 62.47 0.4 61.73 0.4 61.73 1.2 60.63 1.2 60.63 0.4 60.5 0.4 60.5 1 59.1 1 59.1 0.4 45.78 0.4 45.78 1 44.38 1 44.38 0.4 30.76 0.4 30.76 11.28 14.5 11.28 14.5 11.88 13.1 11.88 13.1 11.28 0.4 11.28 0.4 86.64 13.1 86.64 13.1 86.04 14.5 86.04 14.5 86.64 44.38 86.64 44.38 86.04 45.78 86.04 45.78 86.64 59.1 86.64 59.1 86.04 60.5 86.04 60.5 86.64 73.82 86.64 73.82 86.04 75.22 86.04 75.22 86.64 88.54 86.64 88.54 86.04 89.94 86.04 89.94 86.64 119.82 86.64 119.82 86.04 121.22 86.04 121.22 86.64 ; + LAYER met5 ; + POLYGON 132.72 85.44 132.72 72.56 129.52 72.56 129.52 66.16 132.72 66.16 132.72 52.16 129.52 52.16 129.52 45.76 132.72 45.76 132.72 31.76 129.52 31.76 129.52 25.36 132.72 25.36 132.72 12.48 102.36 12.48 102.36 1.6 31.96 1.6 31.96 12.48 1.6 12.48 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 85.44 ; + LAYER li1 ; + POLYGON 134.32 87.125 134.32 86.955 127.335 86.955 127.335 86.23 127.045 86.23 127.045 86.955 120.925 86.955 120.925 86.495 120.62 86.495 120.62 86.955 119.135 86.955 119.135 86.515 118.945 86.515 118.945 86.955 117.045 86.955 117.045 86.495 116.715 86.495 116.715 86.955 114.115 86.955 114.115 86.595 113.785 86.595 113.785 86.955 113.085 86.955 113.085 86.575 112.755 86.575 112.755 86.955 112.155 86.955 112.155 86.23 111.865 86.23 111.865 86.955 108.505 86.955 108.505 86.495 108.2 86.495 108.2 86.955 106.715 86.955 106.715 86.515 106.525 86.515 106.525 86.955 104.625 86.955 104.625 86.495 104.295 86.495 104.295 86.955 101.695 86.955 101.695 86.595 101.365 86.595 101.365 86.955 100.665 86.955 100.665 86.575 100.335 86.575 100.335 86.955 97.435 86.955 97.435 86.23 97.145 86.23 97.145 86.955 91.025 86.955 91.025 86.495 90.72 86.495 90.72 86.955 89.235 86.955 89.235 86.515 89.045 86.515 89.045 86.955 87.145 86.955 87.145 86.495 86.815 86.495 86.815 86.955 84.215 86.955 84.215 86.595 83.885 86.595 83.885 86.955 83.185 86.955 83.185 86.575 82.855 86.575 82.855 86.955 82.255 86.955 82.255 86.23 81.965 86.23 81.965 86.955 80.895 86.955 80.895 86.575 80.565 86.575 80.565 86.955 79.525 86.955 79.525 86.495 79.22 86.495 79.22 86.955 77.735 86.955 77.735 86.515 77.545 86.515 77.545 86.955 75.645 86.955 75.645 86.495 75.315 86.495 75.315 86.955 72.715 86.955 72.715 86.595 72.385 86.595 72.385 86.955 71.685 86.955 71.685 86.575 71.355 86.575 71.355 86.955 67.535 86.955 67.535 86.23 67.245 86.23 67.245 86.955 61.125 86.955 61.125 86.495 60.82 86.495 60.82 86.955 59.335 86.955 59.335 86.515 59.145 86.515 59.145 86.955 57.245 86.955 57.245 86.495 56.915 86.495 56.915 86.955 54.315 86.955 54.315 86.595 53.985 86.595 53.985 86.955 53.285 86.955 53.285 86.575 52.955 86.575 52.955 86.955 52.355 86.955 52.355 86.23 52.065 86.23 52.065 86.955 50.085 86.955 50.085 86.495 49.78 86.495 49.78 86.955 48.295 86.955 48.295 86.515 48.105 86.515 48.105 86.955 46.205 86.955 46.205 86.495 45.875 86.495 45.875 86.955 43.275 86.955 43.275 86.595 42.945 86.595 42.945 86.955 42.245 86.955 42.245 86.575 41.915 86.575 41.915 86.955 37.635 86.955 37.635 86.23 37.345 86.23 37.345 86.955 31.225 86.955 31.225 86.495 30.92 86.495 30.92 86.955 29.435 86.955 29.435 86.515 29.245 86.515 29.245 86.955 27.345 86.955 27.345 86.495 27.015 86.495 27.015 86.955 24.415 86.955 24.415 86.595 24.085 86.595 24.085 86.955 23.385 86.955 23.385 86.575 23.055 86.575 23.055 86.955 22.455 86.955 22.455 86.23 22.165 86.23 22.165 86.955 20.645 86.955 20.645 86.495 20.34 86.495 20.34 86.955 18.855 86.955 18.855 86.515 18.665 86.515 18.665 86.955 16.765 86.955 16.765 86.495 16.435 86.495 16.435 86.955 13.835 86.955 13.835 86.595 13.505 86.595 13.505 86.955 12.805 86.955 12.805 86.575 12.475 86.575 12.475 86.955 7.735 86.955 7.735 86.23 7.445 86.23 7.445 86.955 0 86.955 0 87.125 ; + RECT 133.4 84.235 134.32 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 133.4 81.515 134.32 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 133.4 78.795 134.32 78.965 ; + RECT 0 78.795 1.84 78.965 ; + RECT 133.4 76.075 134.32 76.245 ; + RECT 0 76.075 1.84 76.245 ; + RECT 133.4 73.355 134.32 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 133.4 70.635 134.32 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 132.48 67.915 134.32 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 132.48 65.195 134.32 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 133.4 62.475 134.32 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 133.4 59.755 134.32 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 133.4 57.035 134.32 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 133.4 54.315 134.32 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 133.4 51.595 134.32 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 133.4 48.875 134.32 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 133.4 46.155 134.32 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 133.4 43.435 134.32 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 133.4 40.715 134.32 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 133.4 37.995 134.32 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 133.4 35.275 134.32 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 133.4 32.555 134.32 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 133.4 29.835 134.32 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 133.4 27.115 134.32 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 133.4 24.395 134.32 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 133.4 21.675 134.32 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 133.4 18.955 134.32 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 133.4 16.235 134.32 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 133.4 13.515 134.32 13.685 ; + RECT 0 13.515 3.68 13.685 ; + POLYGON 29.07 11.785 29.07 10.965 32.2 10.965 32.2 10.795 0 10.795 0 10.965 4.665 10.965 4.665 11.345 4.995 11.345 4.995 10.965 7.445 10.965 7.445 11.69 7.735 11.69 7.735 10.965 12.935 10.965 12.935 11.345 13.265 11.345 13.265 10.965 13.965 10.965 13.965 11.325 14.295 11.325 14.295 10.965 16.895 10.965 16.895 11.425 17.225 11.425 17.225 10.965 19.125 10.965 19.125 11.405 19.315 11.405 19.315 10.965 20.8 10.965 20.8 11.425 21.105 11.425 21.105 10.965 22.165 10.965 22.165 11.69 22.455 11.69 22.455 10.965 22.805 10.965 22.805 11.625 23.145 11.625 23.145 10.965 24.745 10.965 24.745 11.5 25.255 11.5 25.255 10.965 27.215 10.965 27.215 11.365 27.545 11.365 27.545 10.965 28.84 10.965 28.84 11.785 ; + POLYGON 127.335 11.69 127.335 10.965 128.075 10.965 128.075 11.425 128.345 11.425 128.345 10.965 130.135 10.965 130.135 11.425 130.46 11.425 130.46 10.965 134.32 10.965 134.32 10.795 97.52 10.795 97.52 10.965 98.035 10.965 98.035 11.345 98.365 11.345 98.365 10.965 99.065 10.965 99.065 11.325 99.395 11.325 99.395 10.965 101.995 10.965 101.995 11.425 102.325 11.425 102.325 10.965 104.225 10.965 104.225 11.405 104.415 11.405 104.415 10.965 105.9 10.965 105.9 11.425 106.205 11.425 106.205 10.965 108.155 10.965 108.155 11.365 108.485 11.365 108.485 10.965 110.445 10.965 110.445 11.5 110.955 11.5 110.955 10.965 111.865 10.965 111.865 11.69 112.155 11.69 112.155 10.965 114.595 10.965 114.595 11.345 114.925 11.345 114.925 10.965 115.625 10.965 115.625 11.325 115.955 11.325 115.955 10.965 118.555 10.965 118.555 11.425 118.885 11.425 118.885 10.965 120.785 10.965 120.785 11.405 120.975 11.405 120.975 10.965 122.46 10.965 122.46 11.425 122.765 11.425 122.765 10.965 123.935 10.965 123.935 11.425 124.205 11.425 124.205 10.965 125.995 10.965 125.995 11.425 126.32 11.425 126.32 10.965 127.045 10.965 127.045 11.69 ; + RECT 100.28 8.075 103.96 8.245 ; + RECT 30.36 8.075 32.2 8.245 ; + RECT 103.04 5.355 103.96 5.525 ; + RECT 30.36 5.355 32.2 5.525 ; + RECT 103.04 2.635 103.96 2.805 ; + RECT 30.36 2.635 32.2 2.805 ; + POLYGON 89.205 0.885 89.205 0.085 89.715 0.085 89.715 0.565 90.045 0.565 90.045 0.085 90.555 0.085 90.555 0.565 90.885 0.565 90.885 0.085 91.475 0.085 91.475 0.565 91.645 0.565 91.645 0.085 92.315 0.085 92.315 0.565 92.485 0.565 92.485 0.085 93.175 0.085 93.175 0.545 93.43 0.545 93.43 0.085 94.1 0.085 94.1 0.545 94.27 0.545 94.27 0.085 94.94 0.085 94.94 0.545 95.11 0.545 95.11 0.085 95.78 0.085 95.78 0.545 95.95 0.545 95.95 0.085 96.62 0.085 96.62 0.545 96.925 0.545 96.925 0.085 97.145 0.085 97.145 0.81 97.435 0.81 97.435 0.085 103.96 0.085 103.96 -0.085 30.36 -0.085 30.36 0.085 33.255 0.085 33.255 0.545 33.56 0.545 33.56 0.085 34.23 0.085 34.23 0.545 34.4 0.545 34.4 0.085 35.07 0.085 35.07 0.545 35.24 0.545 35.24 0.085 35.91 0.085 35.91 0.545 36.08 0.545 36.08 0.085 36.75 0.085 36.75 0.545 37.005 0.545 37.005 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 38.155 0.085 38.155 0.565 38.325 0.565 38.325 0.085 38.995 0.085 38.995 0.565 39.165 0.565 39.165 0.085 39.755 0.085 39.755 0.565 40.085 0.565 40.085 0.085 40.595 0.085 40.595 0.565 40.925 0.565 40.925 0.085 41.435 0.085 41.435 0.885 41.765 0.885 41.765 0.085 42.295 0.085 42.295 0.565 42.465 0.565 42.465 0.085 43.135 0.085 43.135 0.565 43.305 0.565 43.305 0.085 43.895 0.085 43.895 0.565 44.225 0.565 44.225 0.085 44.735 0.085 44.735 0.565 45.065 0.565 45.065 0.085 45.575 0.085 45.575 0.885 45.905 0.885 45.905 0.085 46.135 0.085 46.135 0.545 46.44 0.545 46.44 0.085 47.11 0.085 47.11 0.545 47.28 0.545 47.28 0.085 47.95 0.085 47.95 0.545 48.12 0.545 48.12 0.085 48.79 0.085 48.79 0.545 48.96 0.545 48.96 0.085 49.63 0.085 49.63 0.545 49.885 0.545 49.885 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 53.955 0.085 53.955 0.545 54.26 0.545 54.26 0.085 54.93 0.085 54.93 0.545 55.1 0.545 55.1 0.085 55.77 0.085 55.77 0.545 55.94 0.545 55.94 0.085 56.61 0.085 56.61 0.545 56.78 0.545 56.78 0.085 57.45 0.085 57.45 0.545 57.705 0.545 57.705 0.085 58.055 0.085 58.055 0.885 58.385 0.885 58.385 0.085 58.895 0.085 58.895 0.565 59.225 0.565 59.225 0.085 59.735 0.085 59.735 0.565 60.065 0.565 60.065 0.085 60.655 0.085 60.655 0.565 60.825 0.565 60.825 0.085 61.495 0.085 61.495 0.565 61.665 0.565 61.665 0.085 62.195 0.085 62.195 0.885 62.525 0.885 62.525 0.085 63.035 0.085 63.035 0.565 63.365 0.565 63.365 0.085 63.875 0.085 63.875 0.565 64.205 0.565 64.205 0.085 64.795 0.085 64.795 0.565 64.965 0.565 64.965 0.085 65.635 0.085 65.635 0.565 65.805 0.565 65.805 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 69.555 0.085 69.555 0.885 69.885 0.885 69.885 0.085 70.395 0.085 70.395 0.565 70.725 0.565 70.725 0.085 71.235 0.085 71.235 0.565 71.565 0.565 71.565 0.085 72.155 0.085 72.155 0.565 72.325 0.565 72.325 0.085 72.995 0.085 72.995 0.565 73.165 0.565 73.165 0.085 73.695 0.085 73.695 0.885 74.025 0.885 74.025 0.085 74.535 0.085 74.535 0.565 74.865 0.565 74.865 0.085 75.375 0.085 75.375 0.565 75.705 0.565 75.705 0.085 76.295 0.085 76.295 0.565 76.465 0.565 76.465 0.085 77.135 0.085 77.135 0.565 77.305 0.565 77.305 0.085 77.995 0.085 77.995 0.545 78.25 0.545 78.25 0.085 78.92 0.085 78.92 0.545 79.09 0.545 79.09 0.085 79.76 0.085 79.76 0.545 79.93 0.545 79.93 0.085 80.6 0.085 80.6 0.545 80.77 0.545 80.77 0.085 81.44 0.085 81.44 0.545 81.745 0.545 81.745 0.085 81.965 0.085 81.965 0.81 82.255 0.81 82.255 0.085 82.435 0.085 82.435 0.885 82.765 0.885 82.765 0.085 83.275 0.085 83.275 0.565 83.605 0.565 83.605 0.085 84.115 0.085 84.115 0.565 84.445 0.565 84.445 0.085 85.035 0.085 85.035 0.565 85.205 0.565 85.205 0.085 85.875 0.085 85.875 0.565 86.045 0.565 86.045 0.085 88.875 0.085 88.875 0.885 ; + POLYGON 134.15 86.87 134.15 11.05 103.79 11.05 103.79 0.17 30.53 0.17 30.53 11.05 0.17 11.05 0.17 86.87 ; + LAYER via ; + RECT 89.165 86.845 89.315 86.995 ; + RECT 59.725 86.845 59.875 86.995 ; + RECT 63.635 0.435 63.785 0.585 ; + RECT 45.695 0.435 45.845 0.585 ; + RECT 89.165 0.045 89.315 0.195 ; + RECT 59.725 0.045 59.875 0.195 ; + LAYER via2 ; + RECT 89.14 86.82 89.34 87.02 ; + RECT 59.7 86.82 59.9 87.02 ; + RECT 1.05 47.84 1.25 48.04 ; + RECT 123.87 11.12 124.07 11.32 ; + RECT 118.35 11.12 118.55 11.32 ; + RECT 9.33 11.12 9.53 11.32 ; + RECT 64.07 0.24 64.27 0.44 ; + RECT 89.14 0.02 89.34 0.22 ; + RECT 59.7 0.02 59.9 0.22 ; + LAYER via3 ; + RECT 89.14 86.82 89.34 87.02 ; + RECT 59.7 86.82 59.9 87.02 ; + RECT 103.4 11.12 103.6 11.32 ; + RECT 80.4 0.92 80.6 1.12 ; + RECT 64.76 0.24 64.96 0.44 ; + RECT 61.08 0.24 61.28 0.44 ; + RECT 89.14 0.02 89.34 0.22 ; + RECT 59.7 0.02 59.9 0.22 ; + LAYER OVERLAP ; + POLYGON 30.36 0 30.36 10.88 0 10.88 0 87.04 134.32 87.04 134.32 10.88 103.96 10.88 103.96 0 ; + END +END sb_1__2_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_2__0__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_2__0__icv_in_design.lef new file mode 100644 index 0000000..8fbb31e --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_2__0__icv_in_design.lef @@ -0,0 +1,1740 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_2__0_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 103.96 BY 87.04 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.08 86.555 47.22 87.04 ; + END + END pReset[0] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94.92 86.555 95.06 87.04 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 61.03 86.24 61.33 87.04 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.64 86.555 40.78 87.04 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 95.84 86.555 95.98 87.04 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.92 86.555 49.06 87.04 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 62.87 86.24 63.17 87.04 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 98.6 86.555 98.74 87.04 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.1 86.555 64.24 87.04 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.16 86.555 69.3 87.04 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 92.62 86.555 92.76 87.04 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.84 86.555 49.98 87.04 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.18 86.555 63.32 87.04 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.82 86.555 78.96 87.04 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.42 86.555 83.56 87.04 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.24 86.555 68.38 87.04 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.9 86.555 78.04 87.04 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.66 86.555 80.8 87.04 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 99.52 86.555 99.66 87.04 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 85.26 86.555 85.4 87.04 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.4 86.555 66.54 87.04 ; + END + END chany_top_in[19] + PIN chany_top_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48 86.555 48.14 87.04 ; + END + END chany_top_in[20] + PIN chany_top_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.74 86.555 56.88 87.04 ; + END + END chany_top_in[21] + PIN chany_top_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.88 86.555 38.02 87.04 ; + END + END chany_top_in[22] + PIN chany_top_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.56 86.555 41.7 87.04 ; + END + END chany_top_in[23] + PIN chany_top_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 97.68 86.555 97.82 87.04 ; + END + END chany_top_in[24] + PIN chany_top_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.58 86.555 81.72 87.04 ; + END + END chany_top_in[25] + PIN chany_top_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 101.36 86.555 101.5 87.04 ; + END + END chany_top_in[26] + PIN chany_top_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 72.07 86.24 72.37 87.04 ; + END + END chany_top_in[27] + PIN chany_top_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 91.7 86.555 91.84 87.04 ; + END + END chany_top_in[28] + PIN chany_top_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 100.44 86.555 100.58 87.04 ; + END + END chany_top_in[29] + PIN top_left_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.66 75.675 11.8 76.16 ; + END + END top_left_grid_pin_44_[0] + PIN top_left_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 75.675 14.1 76.16 ; + END + END top_left_grid_pin_45_[0] + PIN top_left_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.84 75.675 3.98 76.16 ; + END + END top_left_grid_pin_46_[0] + PIN top_left_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.82 75.675 9.96 76.16 ; + END + END top_left_grid_pin_47_[0] + PIN top_left_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.94 75.675 20.08 76.16 ; + END + END top_left_grid_pin_48_[0] + PIN top_left_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.56 75.675 18.7 76.16 ; + END + END top_left_grid_pin_49_[0] + PIN top_left_grid_pin_50_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 30.36 80 30.955 80.14 ; + END + END top_left_grid_pin_50_[0] + PIN top_left_grid_pin_51_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.64 75.675 17.78 76.16 ; + END + END top_left_grid_pin_51_[0] + PIN top_right_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 90.78 86.555 90.92 87.04 ; + END + END top_right_grid_pin_1_[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 20.84 0.595 20.98 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.72 0.595 31.86 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 63.68 0.595 63.82 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 29 0.595 29.14 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 42.6 0.595 42.74 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 12 0.595 12.14 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 30.79 0.8 31.09 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 37.59 0.8 37.89 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 32.15 0.8 32.45 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 61.64 0.595 61.78 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 38.95 0.8 39.25 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 41.67 0.8 41.97 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.51 0.8 33.81 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 58.58 0.595 58.72 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 69.46 0.595 69.6 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 66.15 0.8 66.45 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 71.5 0.595 71.64 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 72.18 0.595 72.32 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.23 0.8 36.53 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 53.14 0.595 53.28 ; + END + END chanx_left_in[19] + PIN chanx_left_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 34.87 0.8 35.17 ; + END + END chanx_left_in[20] + PIN chanx_left_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 60.96 0.595 61.1 ; + END + END chanx_left_in[21] + PIN chanx_left_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.31 0.8 40.61 ; + END + END chanx_left_in[22] + PIN chanx_left_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 34.44 0.595 34.58 ; + END + END chanx_left_in[23] + PIN chanx_left_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 26.28 0.595 26.42 ; + END + END chanx_left_in[24] + PIN chanx_left_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 67.51 0.8 67.81 ; + END + END chanx_left_in[25] + PIN chanx_left_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 22.88 0.595 23.02 ; + END + END chanx_left_in[26] + PIN chanx_left_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 49.74 0.595 49.88 ; + END + END chanx_left_in[27] + PIN chanx_left_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 68.78 0.595 68.92 ; + END + END chanx_left_in[28] + PIN chanx_left_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 67.08 0.595 67.22 ; + END + END chanx_left_in[29] + PIN left_bottom_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 4.52 0.595 4.66 ; + END + END left_bottom_grid_pin_1_[0] + PIN left_bottom_grid_pin_3_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 15.4 0.595 15.54 ; + END + END left_bottom_grid_pin_3_[0] + PIN left_bottom_grid_pin_5_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 3.84 0.595 3.98 ; + END + END left_bottom_grid_pin_5_[0] + PIN left_bottom_grid_pin_7_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 6.56 0.595 6.7 ; + END + END left_bottom_grid_pin_7_[0] + PIN left_bottom_grid_pin_9_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 8.94 0.595 9.08 ; + END + END left_bottom_grid_pin_9_[0] + PIN left_bottom_grid_pin_11_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 17.44 0.595 17.58 ; + END + END left_bottom_grid_pin_11_[0] + PIN left_bottom_grid_pin_13_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 7.24 0.595 7.38 ; + END + END left_bottom_grid_pin_13_[0] + PIN left_bottom_grid_pin_15_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 14.72 0.595 14.86 ; + END + END left_bottom_grid_pin_15_[0] + PIN left_bottom_grid_pin_17_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 12.68 0.595 12.82 ; + END + END left_bottom_grid_pin_17_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.18 86.555 86.32 87.04 ; + END + END ccff_head[0] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 89.86 86.555 90 87.04 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.34 86.555 84.48 87.04 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.5 86.555 82.64 87.04 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 88.02 86.555 88.16 87.04 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.76 86.555 50.9 87.04 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.34 86.555 61.48 87.04 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 87.1 86.555 87.24 87.04 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.82 86.555 55.96 87.04 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.9 86.555 55.04 87.04 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 86.555 58.26 87.04 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.52 86.555 53.66 87.04 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.3 86.555 73.44 87.04 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.02 86.555 65.16 87.04 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.76 86.555 96.9 87.04 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.74 86.555 79.88 87.04 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.98 86.555 77.12 87.04 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.6 86.555 52.74 87.04 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.22 86.555 74.36 87.04 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.26 86.555 62.4 87.04 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.32 86.555 67.46 87.04 ; + END + END chany_top_out[19] + PIN chany_top_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.08 86.555 70.22 87.04 ; + END + END chany_top_out[20] + PIN chany_top_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.04 86.555 59.18 87.04 ; + END + END chany_top_out[21] + PIN chany_top_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.86 86.555 44 87.04 ; + END + END chany_top_out[22] + PIN chany_top_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.38 86.555 72.52 87.04 ; + END + END chany_top_out[23] + PIN chany_top_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71 86.555 71.14 87.04 ; + END + END chany_top_out[24] + PIN chany_top_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.42 86.555 60.56 87.04 ; + END + END chany_top_out[25] + PIN chany_top_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.06 86.555 76.2 87.04 ; + END + END chany_top_out[26] + PIN chany_top_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.68 86.555 51.82 87.04 ; + END + END chany_top_out[27] + PIN chany_top_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.14 86.555 75.28 87.04 ; + END + END chany_top_out[28] + PIN chany_top_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94 86.555 94.14 87.04 ; + END + END chany_top_out[29] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 1.8 0.595 1.94 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 37.16 0.595 37.3 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 50.51 0.8 50.81 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 39.2 0.595 39.34 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.04 0.595 31.18 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.11 0.8 47.41 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.03 0.8 43.33 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 45.75 0.8 46.05 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 49.15 0.8 49.45 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 47.02 0.595 47.16 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 56.2 0.595 56.34 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 45.32 0.595 45.46 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 52.46 0.595 52.6 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 41.92 0.595 42.06 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.48 0.595 36.62 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 47.7 0.595 47.84 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 64.36 0.595 64.5 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 66.4 0.595 66.54 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 22.63 0.8 22.93 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 50.42 0.595 50.56 ; + END + END chanx_left_out[19] + PIN chanx_left_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 25.6 0.595 25.74 ; + END + END chanx_left_out[20] + PIN chanx_left_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 57.9 0.595 58.04 ; + END + END chanx_left_out[21] + PIN chanx_left_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.39 0.8 44.69 ; + END + END chanx_left_out[22] + PIN chanx_left_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.64 0.595 44.78 ; + END + END chanx_left_out[23] + PIN chanx_left_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 39.88 0.595 40.02 ; + END + END chanx_left_out[24] + PIN chanx_left_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 23.56 0.595 23.7 ; + END + END chanx_left_out[25] + PIN chanx_left_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 23.99 0.8 24.29 ; + END + END chanx_left_out[26] + PIN chanx_left_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 27.98 0.595 28.12 ; + END + END chanx_left_out[27] + PIN chanx_left_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 33.42 0.595 33.56 ; + END + END chanx_left_out[28] + PIN chanx_left_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 55.52 0.595 55.66 ; + END + END chanx_left_out[29] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 18.12 0.595 18.26 ; + END + END ccff_tail[0] + PIN pReset_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 19.82 0.595 19.96 ; + END + END pReset_W_in + PIN pReset_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 86.555 37.1 87.04 ; + END + END pReset_N_out + PIN prog_clk_0_N_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 32.82 86.555 32.96 87.04 ; + END + END prog_clk_0_N_in + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 16.08 3.2 19.28 ; + RECT 100.76 16.08 103.96 19.28 ; + RECT 0 56.88 3.2 60.08 ; + RECT 100.76 56.88 103.96 60.08 ; + LAYER met4 ; + RECT 13.5 0 14.1 0.6 ; + RECT 44.78 0 45.38 0.6 ; + RECT 74.22 0 74.82 0.6 ; + RECT 13.5 75.56 14.1 76.16 ; + RECT 44.78 86.44 45.38 87.04 ; + RECT 74.22 86.44 74.82 87.04 ; + LAYER met1 ; + RECT 0 2.48 0.48 2.96 ; + RECT 103.48 2.48 103.96 2.96 ; + RECT 0 7.92 0.48 8.4 ; + RECT 103.48 7.92 103.96 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 103.48 13.36 103.96 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 103.48 18.8 103.96 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 103.48 24.24 103.96 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 103.48 29.68 103.96 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 103.48 35.12 103.96 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 103.48 40.56 103.96 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 103.48 46 103.96 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 103.48 51.44 103.96 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 103.48 56.88 103.96 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 103.48 62.32 103.96 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 103.48 67.76 103.96 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 103.48 73.2 103.96 73.68 ; + RECT 30.36 78.64 30.84 79.12 ; + RECT 103.48 78.64 103.96 79.12 ; + RECT 30.36 84.08 30.84 84.56 ; + RECT 103.48 84.08 103.96 84.56 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 36.48 3.2 39.68 ; + RECT 100.76 36.48 103.96 39.68 ; + LAYER met4 ; + RECT 59.5 0 60.1 0.6 ; + RECT 88.94 0 89.54 0.6 ; + RECT 59.5 86.44 60.1 87.04 ; + RECT 88.94 86.44 89.54 87.04 ; + LAYER met1 ; + RECT 0 -0.24 0.48 0.24 ; + RECT 103.48 -0.24 103.96 0.24 ; + RECT 0 5.2 0.48 5.68 ; + RECT 103.48 5.2 103.96 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 103.48 10.64 103.96 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 103.48 16.08 103.96 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 103.48 21.52 103.96 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 103.48 26.96 103.96 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 103.48 32.4 103.96 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 103.48 37.84 103.96 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 103.48 43.28 103.96 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 103.48 48.72 103.96 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 103.48 54.16 103.96 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 103.48 59.6 103.96 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 103.48 65.04 103.96 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 103.48 70.48 103.96 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 103.48 75.92 103.96 76.4 ; + RECT 30.36 81.36 30.84 81.84 ; + RECT 103.48 81.36 103.96 81.84 ; + RECT 30.36 86.8 30.84 87.28 ; + RECT 103.48 86.8 103.96 87.28 ; + END + END VSS + OBS + LAYER met2 ; + RECT 89.1 86.735 89.38 87.105 ; + RECT 59.66 86.735 59.94 87.105 ; + POLYGON 73.94 86.94 73.94 86.8 73.9 86.8 73.9 82.38 73.76 82.38 73.76 86.94 ; + POLYGON 43.58 86.77 43.58 86.63 42.16 86.63 42.16 86.35 42.22 86.35 42.22 86.03 41.96 86.03 41.96 86.35 42.02 86.35 42.02 86.77 ; + POLYGON 9.57 76.005 9.57 75.635 9.56 75.635 9.56 75.49 9.3 75.49 9.3 75.635 9.29 75.635 9.29 76.005 ; + RECT 89.1 -0.065 89.38 0.305 ; + RECT 59.66 -0.065 59.94 0.305 ; + POLYGON 103.68 86.76 103.68 0.28 0.28 0.28 0.28 75.88 3.56 75.88 3.56 75.395 4.26 75.395 4.26 75.88 9.54 75.88 9.54 75.395 10.24 75.395 10.24 75.88 11.38 75.88 11.38 75.395 12.08 75.395 12.08 75.88 13.68 75.88 13.68 75.395 14.38 75.395 14.38 75.88 17.36 75.88 17.36 75.395 18.06 75.395 18.06 75.88 18.28 75.88 18.28 75.395 18.98 75.395 18.98 75.88 19.66 75.88 19.66 75.395 20.36 75.395 20.36 75.88 30.64 75.88 30.64 86.76 32.54 86.76 32.54 86.275 33.24 86.275 33.24 86.76 36.68 86.76 36.68 86.275 37.38 86.275 37.38 86.76 37.6 86.76 37.6 86.275 38.3 86.275 38.3 86.76 40.36 86.76 40.36 86.275 41.06 86.275 41.06 86.76 41.28 86.76 41.28 86.275 41.98 86.275 41.98 86.76 43.58 86.76 43.58 86.275 44.28 86.275 44.28 86.76 46.8 86.76 46.8 86.275 47.5 86.275 47.5 86.76 47.72 86.76 47.72 86.275 48.42 86.275 48.42 86.76 48.64 86.76 48.64 86.275 49.34 86.275 49.34 86.76 49.56 86.76 49.56 86.275 50.26 86.275 50.26 86.76 50.48 86.76 50.48 86.275 51.18 86.275 51.18 86.76 51.4 86.76 51.4 86.275 52.1 86.275 52.1 86.76 52.32 86.76 52.32 86.275 53.02 86.275 53.02 86.76 53.24 86.76 53.24 86.275 53.94 86.275 53.94 86.76 54.62 86.76 54.62 86.275 55.32 86.275 55.32 86.76 55.54 86.76 55.54 86.275 56.24 86.275 56.24 86.76 56.46 86.76 56.46 86.275 57.16 86.275 57.16 86.76 57.84 86.76 57.84 86.275 58.54 86.275 58.54 86.76 58.76 86.76 58.76 86.275 59.46 86.275 59.46 86.76 60.14 86.76 60.14 86.275 60.84 86.275 60.84 86.76 61.06 86.76 61.06 86.275 61.76 86.275 61.76 86.76 61.98 86.76 61.98 86.275 62.68 86.275 62.68 86.76 62.9 86.76 62.9 86.275 63.6 86.275 63.6 86.76 63.82 86.76 63.82 86.275 64.52 86.275 64.52 86.76 64.74 86.76 64.74 86.275 65.44 86.275 65.44 86.76 66.12 86.76 66.12 86.275 66.82 86.275 66.82 86.76 67.04 86.76 67.04 86.275 67.74 86.275 67.74 86.76 67.96 86.76 67.96 86.275 68.66 86.275 68.66 86.76 68.88 86.76 68.88 86.275 69.58 86.275 69.58 86.76 69.8 86.76 69.8 86.275 70.5 86.275 70.5 86.76 70.72 86.76 70.72 86.275 71.42 86.275 71.42 86.76 72.1 86.76 72.1 86.275 72.8 86.275 72.8 86.76 73.02 86.76 73.02 86.275 73.72 86.275 73.72 86.76 73.94 86.76 73.94 86.275 74.64 86.275 74.64 86.76 74.86 86.76 74.86 86.275 75.56 86.275 75.56 86.76 75.78 86.76 75.78 86.275 76.48 86.275 76.48 86.76 76.7 86.76 76.7 86.275 77.4 86.275 77.4 86.76 77.62 86.76 77.62 86.275 78.32 86.275 78.32 86.76 78.54 86.76 78.54 86.275 79.24 86.275 79.24 86.76 79.46 86.76 79.46 86.275 80.16 86.275 80.16 86.76 80.38 86.76 80.38 86.275 81.08 86.275 81.08 86.76 81.3 86.76 81.3 86.275 82 86.275 82 86.76 82.22 86.76 82.22 86.275 82.92 86.275 82.92 86.76 83.14 86.76 83.14 86.275 83.84 86.275 83.84 86.76 84.06 86.76 84.06 86.275 84.76 86.275 84.76 86.76 84.98 86.76 84.98 86.275 85.68 86.275 85.68 86.76 85.9 86.76 85.9 86.275 86.6 86.275 86.6 86.76 86.82 86.76 86.82 86.275 87.52 86.275 87.52 86.76 87.74 86.76 87.74 86.275 88.44 86.275 88.44 86.76 89.58 86.76 89.58 86.275 90.28 86.275 90.28 86.76 90.5 86.76 90.5 86.275 91.2 86.275 91.2 86.76 91.42 86.76 91.42 86.275 92.12 86.275 92.12 86.76 92.34 86.76 92.34 86.275 93.04 86.275 93.04 86.76 93.72 86.76 93.72 86.275 94.42 86.275 94.42 86.76 94.64 86.76 94.64 86.275 95.34 86.275 95.34 86.76 95.56 86.76 95.56 86.275 96.26 86.275 96.26 86.76 96.48 86.76 96.48 86.275 97.18 86.275 97.18 86.76 97.4 86.76 97.4 86.275 98.1 86.275 98.1 86.76 98.32 86.76 98.32 86.275 99.02 86.275 99.02 86.76 99.24 86.76 99.24 86.275 99.94 86.275 99.94 86.76 100.16 86.76 100.16 86.275 100.86 86.275 100.86 86.76 101.08 86.76 101.08 86.275 101.78 86.275 101.78 86.76 ; + LAYER met4 ; + POLYGON 71.465 86.865 71.465 86.535 71.45 86.535 71.45 70.91 71.15 70.91 71.15 86.535 71.135 86.535 71.135 86.865 ; + POLYGON 69.625 86.865 69.625 86.535 69.61 86.535 69.61 43.03 69.31 43.03 69.31 86.535 69.295 86.535 69.295 86.865 ; + POLYGON 31.89 78.01 31.89 77.71 30.97 77.71 30.97 69.55 30.67 69.55 30.67 78.01 ; + POLYGON 103.56 86.64 103.56 0.4 89.94 0.4 89.94 1 88.54 1 88.54 0.4 75.22 0.4 75.22 1 73.82 1 73.82 0.4 60.5 0.4 60.5 1 59.1 1 59.1 0.4 45.78 0.4 45.78 1 44.38 1 44.38 0.4 14.5 0.4 14.5 1 13.1 1 13.1 0.4 0.4 0.4 0.4 75.76 13.1 75.76 13.1 75.16 14.5 75.16 14.5 75.76 30.76 75.76 30.76 86.64 44.38 86.64 44.38 86.04 45.78 86.04 45.78 86.64 59.1 86.64 59.1 86.04 60.5 86.04 60.5 86.64 60.63 86.64 60.63 85.84 61.73 85.84 61.73 86.64 62.47 86.64 62.47 85.84 63.57 85.84 63.57 86.64 71.67 86.64 71.67 85.84 72.77 85.84 72.77 86.64 73.82 86.64 73.82 86.04 75.22 86.04 75.22 86.64 88.54 86.64 88.54 86.04 89.94 86.04 89.94 86.64 ; + LAYER met1 ; + POLYGON 103.2 87.28 103.2 86.8 89.4 86.8 89.4 86.79 89.08 86.79 89.08 86.8 59.96 86.8 59.96 86.79 59.64 86.79 59.64 86.8 31.12 86.8 31.12 87.28 ; + RECT 0.76 75.92 71.16 76.4 ; + POLYGON 89.4 0.25 89.4 0.24 103.2 0.24 103.2 -0.24 0.76 -0.24 0.76 0.24 59.64 0.24 59.64 0.25 59.96 0.25 59.96 0.24 89.08 0.24 89.08 0.25 ; + POLYGON 103.2 86.76 103.2 86.52 103.68 86.52 103.68 84.84 103.2 84.84 103.2 83.8 103.68 83.8 103.68 82.12 103.2 82.12 103.2 81.08 103.68 81.08 103.68 79.4 103.2 79.4 103.2 78.36 103.68 78.36 103.68 76.68 103.2 76.68 103.2 75.64 103.68 75.64 103.68 73.96 103.2 73.96 103.2 72.92 103.68 72.92 103.68 71.24 103.2 71.24 103.2 70.2 103.68 70.2 103.68 68.52 103.2 68.52 103.2 67.48 103.68 67.48 103.68 65.8 103.2 65.8 103.2 64.76 103.68 64.76 103.68 63.08 103.2 63.08 103.2 62.04 103.68 62.04 103.68 60.36 103.2 60.36 103.2 59.32 103.68 59.32 103.68 57.64 103.2 57.64 103.2 56.6 103.68 56.6 103.68 54.92 103.2 54.92 103.2 53.88 103.68 53.88 103.68 52.2 103.2 52.2 103.2 51.16 103.68 51.16 103.68 49.48 103.2 49.48 103.2 48.44 103.68 48.44 103.68 46.76 103.2 46.76 103.2 45.72 103.68 45.72 103.68 44.04 103.2 44.04 103.2 43 103.68 43 103.68 41.32 103.2 41.32 103.2 40.28 103.68 40.28 103.68 38.6 103.2 38.6 103.2 37.56 103.68 37.56 103.68 35.88 103.2 35.88 103.2 34.84 103.68 34.84 103.68 33.16 103.2 33.16 103.2 32.12 103.68 32.12 103.68 30.44 103.2 30.44 103.2 29.4 103.68 29.4 103.68 27.72 103.2 27.72 103.2 26.68 103.68 26.68 103.68 25 103.2 25 103.2 23.96 103.68 23.96 103.68 22.28 103.2 22.28 103.2 21.24 103.68 21.24 103.68 19.56 103.2 19.56 103.2 18.52 103.68 18.52 103.68 16.84 103.2 16.84 103.2 15.8 103.68 15.8 103.68 14.12 103.2 14.12 103.2 13.08 103.68 13.08 103.68 11.4 103.2 11.4 103.2 10.36 103.68 10.36 103.68 8.68 103.2 8.68 103.2 7.64 103.68 7.64 103.68 5.96 103.2 5.96 103.2 4.92 103.68 4.92 103.68 3.24 103.2 3.24 103.2 2.2 103.68 2.2 103.68 0.52 103.2 0.52 103.2 0.28 0.76 0.28 0.76 0.52 0.28 0.52 0.28 1.52 0.875 1.52 0.875 2.22 0.76 2.22 0.76 3.24 0.28 3.24 0.28 3.56 0.875 3.56 0.875 4.94 0.76 4.94 0.76 5.96 0.28 5.96 0.28 6.28 0.875 6.28 0.875 7.66 0.76 7.66 0.76 8.66 0.875 8.66 0.875 9.36 0.28 9.36 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 11.72 0.875 11.72 0.875 13.1 0.76 13.1 0.76 14.12 0.28 14.12 0.28 14.44 0.875 14.44 0.875 15.82 0.76 15.82 0.76 16.84 0.28 16.84 0.28 17.16 0.875 17.16 0.875 18.54 0.76 18.54 0.76 19.54 0.875 19.54 0.875 20.24 0.28 20.24 0.28 20.56 0.875 20.56 0.875 21.26 0.76 21.26 0.76 22.28 0.28 22.28 0.28 22.6 0.875 22.6 0.875 23.98 0.76 23.98 0.76 25 0.28 25 0.28 25.32 0.875 25.32 0.875 26.7 0.76 26.7 0.76 27.7 0.875 27.7 0.875 28.4 0.28 28.4 0.28 28.72 0.875 28.72 0.875 29.42 0.76 29.42 0.76 30.44 0.28 30.44 0.28 30.76 0.875 30.76 0.875 32.14 0.76 32.14 0.76 33.14 0.875 33.14 0.875 33.84 0.28 33.84 0.28 34.16 0.875 34.16 0.875 34.86 0.76 34.86 0.76 35.88 0.28 35.88 0.28 36.2 0.875 36.2 0.875 37.58 0.76 37.58 0.76 38.6 0.28 38.6 0.28 38.92 0.875 38.92 0.875 40.3 0.76 40.3 0.76 41.32 0.28 41.32 0.28 41.64 0.875 41.64 0.875 43.02 0.76 43.02 0.76 44.04 0.28 44.04 0.28 44.36 0.875 44.36 0.875 45.74 0.76 45.74 0.76 46.74 0.875 46.74 0.875 48.12 0.28 48.12 0.28 48.44 0.76 48.44 0.76 49.46 0.875 49.46 0.875 50.84 0.28 50.84 0.28 51.16 0.76 51.16 0.76 52.18 0.875 52.18 0.875 53.56 0.28 53.56 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 55.24 0.875 55.24 0.875 56.62 0.76 56.62 0.76 57.62 0.875 57.62 0.875 59 0.28 59 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 60.68 0.875 60.68 0.875 62.06 0.76 62.06 0.76 63.08 0.28 63.08 0.28 63.4 0.875 63.4 0.875 64.78 0.76 64.78 0.76 65.8 0.28 65.8 0.28 66.12 0.875 66.12 0.875 67.5 0.76 67.5 0.76 68.5 0.875 68.5 0.875 69.88 0.28 69.88 0.28 70.2 0.76 70.2 0.76 71.22 0.875 71.22 0.875 72.6 0.28 72.6 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 75.88 30.64 75.88 30.64 78.36 31.12 78.36 31.12 79.4 30.64 79.4 30.64 79.72 31.235 79.72 31.235 80.42 30.64 80.42 30.64 81.08 31.12 81.08 31.12 82.12 30.64 82.12 30.64 83.8 31.12 83.8 31.12 84.84 30.64 84.84 30.64 86.52 31.12 86.52 31.12 86.76 ; + LAYER met3 ; + POLYGON 89.405 87.085 89.405 87.08 89.62 87.08 89.62 86.76 89.405 86.76 89.405 86.755 89.075 86.755 89.075 86.76 88.86 86.76 88.86 87.08 89.075 87.08 89.075 87.085 ; + POLYGON 59.965 87.085 59.965 87.08 60.18 87.08 60.18 86.76 59.965 86.76 59.965 86.755 59.635 86.755 59.635 86.76 59.42 86.76 59.42 87.08 59.635 87.08 59.635 87.085 ; + POLYGON 75.375 86.865 75.375 86.535 75.045 86.535 75.045 86.55 71.49 86.55 71.49 86.54 71.11 86.54 71.11 86.86 71.49 86.86 71.49 86.85 75.045 86.85 75.045 86.865 ; + POLYGON 69.395 86.865 69.395 86.86 69.65 86.86 69.65 86.54 69.395 86.54 69.395 86.535 69.065 86.535 69.065 86.54 68.695 86.54 68.695 86.86 69.065 86.86 69.065 86.865 ; + POLYGON 9.595 75.985 9.595 75.97 43.62 75.97 43.62 75.67 9.595 75.67 9.595 75.655 9.265 75.655 9.265 75.985 ; + POLYGON 27.52 44.01 27.52 43.71 0.65 43.71 0.65 43.99 1.2 43.99 1.2 44.01 ; + POLYGON 89.405 0.285 89.405 0.28 89.62 0.28 89.62 -0.04 89.405 -0.04 89.405 -0.045 89.075 -0.045 89.075 -0.04 88.86 -0.04 88.86 0.28 89.075 0.28 89.075 0.285 ; + POLYGON 59.965 0.285 59.965 0.28 60.18 0.28 60.18 -0.04 59.965 -0.04 59.965 -0.045 59.635 -0.045 59.635 -0.04 59.42 -0.04 59.42 0.28 59.635 0.28 59.635 0.285 ; + POLYGON 103.56 86.64 103.56 0.4 0.4 0.4 0.4 22.23 1.2 22.23 1.2 23.33 0.4 23.33 0.4 23.59 1.2 23.59 1.2 24.69 0.4 24.69 0.4 30.39 1.2 30.39 1.2 31.49 0.4 31.49 0.4 31.75 1.2 31.75 1.2 32.85 0.4 32.85 0.4 33.11 1.2 33.11 1.2 34.21 0.4 34.21 0.4 34.47 1.2 34.47 1.2 35.57 0.4 35.57 0.4 35.83 1.2 35.83 1.2 36.93 0.4 36.93 0.4 37.19 1.2 37.19 1.2 38.29 0.4 38.29 0.4 38.55 1.2 38.55 1.2 39.65 0.4 39.65 0.4 39.91 1.2 39.91 1.2 41.01 0.4 41.01 0.4 41.27 1.2 41.27 1.2 42.37 0.4 42.37 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 48.75 1.2 48.75 1.2 49.85 0.4 49.85 0.4 50.11 1.2 50.11 1.2 51.21 0.4 51.21 0.4 65.75 1.2 65.75 1.2 66.85 0.4 66.85 0.4 67.11 1.2 67.11 1.2 68.21 0.4 68.21 0.4 75.76 30.76 75.76 30.76 86.64 ; + LAYER met5 ; + POLYGON 102.36 85.44 102.36 61.68 99.16 61.68 99.16 55.28 102.36 55.28 102.36 41.28 99.16 41.28 99.16 34.88 102.36 34.88 102.36 20.88 99.16 20.88 99.16 14.48 102.36 14.48 102.36 1.6 1.6 1.6 1.6 14.48 4.8 14.48 4.8 20.88 1.6 20.88 1.6 34.88 4.8 34.88 4.8 41.28 1.6 41.28 1.6 55.28 4.8 55.28 4.8 61.68 1.6 61.68 1.6 74.56 31.96 74.56 31.96 85.44 ; + LAYER li1 ; + POLYGON 103.96 87.125 103.96 86.955 97.435 86.955 97.435 86.23 97.145 86.23 97.145 86.955 96.625 86.955 96.625 86.475 96.455 86.475 96.455 86.955 95.785 86.955 95.785 86.475 95.615 86.475 95.615 86.955 95.025 86.955 95.025 86.475 94.695 86.475 94.695 86.955 94.185 86.955 94.185 86.475 93.855 86.475 93.855 86.955 93.345 86.955 93.345 86.155 93.015 86.155 93.015 86.955 92.79 86.955 92.79 86.495 92.525 86.495 92.525 86.955 91.735 86.955 91.735 86.495 91.565 86.495 91.565 86.955 90.895 86.955 90.895 86.495 90.725 86.495 90.725 86.955 90.135 86.955 90.135 86.49 89.885 86.49 89.885 86.955 89.06 86.955 89.06 86.495 88.735 86.495 88.735 86.955 86.945 86.955 86.945 86.495 86.675 86.495 86.675 86.955 85.38 86.955 85.38 86.495 85.055 86.495 85.055 86.955 83.265 86.955 83.265 86.495 82.995 86.495 82.995 86.955 82.255 86.955 82.255 86.23 81.965 86.23 81.965 86.955 81.24 86.955 81.24 86.495 80.915 86.495 80.915 86.955 79.125 86.955 79.125 86.495 78.855 86.495 78.855 86.955 78.105 86.955 78.105 86.155 77.775 86.155 77.775 86.955 77.265 86.955 77.265 86.475 76.935 86.475 76.935 86.955 76.425 86.955 76.425 86.475 76.095 86.475 76.095 86.955 75.505 86.955 75.505 86.475 75.335 86.475 75.335 86.955 74.665 86.955 74.665 86.475 74.495 86.475 74.495 86.955 73.965 86.955 73.965 86.155 73.635 86.155 73.635 86.955 73.125 86.955 73.125 86.475 72.795 86.475 72.795 86.955 72.285 86.955 72.285 86.475 71.955 86.475 71.955 86.955 71.365 86.955 71.365 86.475 71.195 86.475 71.195 86.955 70.525 86.955 70.525 86.475 70.355 86.475 70.355 86.955 67.535 86.955 67.535 86.23 67.245 86.23 67.245 86.955 66.055 86.955 66.055 86.49 65.805 86.49 65.805 86.955 65.215 86.955 65.215 86.495 65.045 86.495 65.045 86.955 64.375 86.955 64.375 86.495 64.205 86.495 64.205 86.955 63.415 86.955 63.415 86.495 63.15 86.495 63.15 86.955 62.89 86.955 62.89 86.495 62.625 86.495 62.625 86.955 61.835 86.955 61.835 86.495 61.665 86.495 61.665 86.955 60.995 86.955 60.995 86.495 60.825 86.495 60.825 86.955 60.235 86.955 60.235 86.49 59.985 86.49 59.985 86.955 59.705 86.955 59.705 86.155 59.375 86.155 59.375 86.955 58.865 86.955 58.865 86.475 58.535 86.475 58.535 86.955 58.025 86.955 58.025 86.475 57.695 86.475 57.695 86.955 57.105 86.955 57.105 86.475 56.935 86.475 56.935 86.955 56.265 86.955 56.265 86.475 56.095 86.475 56.095 86.955 55.475 86.955 55.475 86.49 55.225 86.49 55.225 86.955 54.635 86.955 54.635 86.495 54.465 86.495 54.465 86.955 53.795 86.955 53.795 86.495 53.625 86.495 53.625 86.955 52.835 86.955 52.835 86.495 52.57 86.495 52.57 86.955 52.355 86.955 52.355 86.23 52.065 86.23 52.065 86.955 50.415 86.955 50.415 86.49 50.165 86.49 50.165 86.955 49.575 86.955 49.575 86.495 49.405 86.495 49.405 86.955 48.735 86.955 48.735 86.495 48.565 86.495 48.565 86.955 47.775 86.955 47.775 86.495 47.51 86.495 47.51 86.955 42.805 86.955 42.805 86.475 42.635 86.475 42.635 86.955 41.965 86.955 41.965 86.475 41.795 86.475 41.795 86.955 41.205 86.955 41.205 86.475 40.875 86.475 40.875 86.955 40.365 86.955 40.365 86.475 40.035 86.475 40.035 86.955 39.525 86.955 39.525 86.155 39.195 86.155 39.195 86.955 37.635 86.955 37.635 86.23 37.345 86.23 37.345 86.955 30.36 86.955 30.36 87.125 ; + RECT 103.04 84.235 103.96 84.405 ; + RECT 30.36 84.235 34.04 84.405 ; + RECT 103.04 81.515 103.96 81.685 ; + RECT 30.36 81.515 34.04 81.685 ; + RECT 103.04 78.795 103.96 78.965 ; + RECT 30.36 78.795 34.04 78.965 ; + RECT 103.04 76.075 103.96 76.245 ; + POLYGON 34.04 76.245 34.04 76.075 28.925 76.075 28.925 75.675 28.595 75.675 28.595 76.075 26.635 76.075 26.635 75.54 26.125 75.54 26.125 76.075 22.455 76.075 22.455 75.35 22.165 75.35 22.165 76.075 21.565 76.075 21.565 75.615 21.26 75.615 21.26 76.075 19.775 76.075 19.775 75.635 19.585 75.635 19.585 76.075 17.685 76.075 17.685 75.615 17.355 75.615 17.355 76.075 14.755 76.075 14.755 75.715 14.425 75.715 14.425 76.075 13.725 76.075 13.725 75.695 13.395 75.695 13.395 76.075 7.735 76.075 7.735 75.35 7.445 75.35 7.445 76.075 6.845 76.075 6.845 75.675 6.515 75.675 6.515 76.075 4.555 76.075 4.555 75.54 4.045 75.54 4.045 76.075 0 76.075 0 76.245 ; + RECT 103.04 73.355 103.96 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 103.04 70.635 103.96 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 103.04 67.915 103.96 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 103.04 65.195 103.96 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 103.04 62.475 103.96 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 103.04 59.755 103.96 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 103.04 57.035 103.96 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 103.04 54.315 103.96 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 103.04 51.595 103.96 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 103.04 48.875 103.96 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 103.04 46.155 103.96 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 103.04 43.435 103.96 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 103.04 40.715 103.96 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 103.04 37.995 103.96 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 100.28 35.275 103.96 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 100.28 32.555 103.96 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 103.04 29.835 103.96 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 103.04 27.115 103.96 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 103.04 24.395 103.96 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 103.04 21.675 103.96 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 103.04 18.955 103.96 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 103.04 16.235 103.96 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 103.04 13.515 103.96 13.685 ; + RECT 0 13.515 1.84 13.685 ; + RECT 103.04 10.795 103.96 10.965 ; + RECT 0 10.795 1.84 10.965 ; + RECT 103.04 8.075 103.96 8.245 ; + RECT 0 8.075 1.84 8.245 ; + RECT 103.04 5.355 103.96 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 103.04 2.635 103.96 2.805 ; + RECT 0 2.635 3.68 2.805 ; + POLYGON 78.085 0.885 78.085 0.085 78.675 0.085 78.675 0.465 79.005 0.465 79.005 0.085 81.09 0.085 81.09 0.585 81.29 0.585 81.29 0.085 81.965 0.085 81.965 0.81 82.255 0.81 82.255 0.085 92.985 0.085 92.985 0.465 93.315 0.465 93.315 0.085 97.145 0.085 97.145 0.81 97.435 0.81 97.435 0.085 103.96 0.085 103.96 -0.085 0 -0.085 0 0.085 7.445 0.085 7.445 0.81 7.735 0.81 7.735 0.085 10.185 0.085 10.185 0.465 10.515 0.465 10.515 0.085 13.395 0.085 13.395 0.465 13.725 0.465 13.725 0.085 14.425 0.085 14.425 0.445 14.755 0.445 14.755 0.085 17.355 0.085 17.355 0.545 17.685 0.545 17.685 0.085 19.585 0.085 19.585 0.525 19.775 0.525 19.775 0.085 21.26 0.085 21.26 0.545 21.565 0.545 21.565 0.085 22.165 0.085 22.165 0.81 22.455 0.81 22.455 0.085 29.505 0.085 29.505 0.465 29.835 0.465 29.835 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 42.375 0.085 42.375 0.465 42.705 0.465 42.705 0.085 43.405 0.085 43.405 0.445 43.735 0.445 43.735 0.085 46.335 0.085 46.335 0.545 46.665 0.545 46.665 0.085 48.565 0.085 48.565 0.525 48.755 0.525 48.755 0.085 50.24 0.085 50.24 0.545 50.545 0.545 50.545 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 52.955 0.085 52.955 0.465 53.285 0.465 53.285 0.085 53.985 0.085 53.985 0.445 54.315 0.445 54.315 0.085 56.915 0.085 56.915 0.545 57.245 0.545 57.245 0.085 59.145 0.085 59.145 0.525 59.335 0.525 59.335 0.085 60.82 0.085 60.82 0.545 61.125 0.545 61.125 0.085 64.465 0.085 64.465 0.465 64.795 0.465 64.795 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 69.055 0.085 69.055 0.465 69.385 0.465 69.385 0.085 70.085 0.085 70.085 0.445 70.415 0.445 70.415 0.085 73.015 0.085 73.015 0.545 73.345 0.545 73.345 0.085 75.245 0.085 75.245 0.525 75.435 0.525 75.435 0.085 76.92 0.085 76.92 0.545 77.225 0.545 77.225 0.085 77.83 0.085 77.83 0.885 ; + POLYGON 103.79 86.87 103.79 0.17 0.17 0.17 0.17 75.99 30.53 75.99 30.53 86.87 ; + LAYER via ; + RECT 89.165 86.845 89.315 86.995 ; + RECT 59.725 86.845 59.875 86.995 ; + RECT 86.175 86.455 86.325 86.605 ; + RECT 70.995 86.455 71.145 86.605 ; + RECT 61.335 86.455 61.485 86.605 ; + RECT 89.165 0.045 89.315 0.195 ; + RECT 59.725 0.045 59.875 0.195 ; + LAYER via2 ; + RECT 89.14 86.82 89.34 87.02 ; + RECT 59.7 86.82 59.9 87.02 ; + RECT 75.11 86.6 75.31 86.8 ; + RECT 69.13 86.6 69.33 86.8 ; + RECT 9.33 75.72 9.53 75.92 ; + RECT 1.05 45.8 1.25 46 ; + RECT 89.14 0.02 89.34 0.22 ; + RECT 59.7 0.02 59.9 0.22 ; + LAYER via3 ; + RECT 89.14 86.82 89.34 87.02 ; + RECT 59.7 86.82 59.9 87.02 ; + RECT 71.2 86.6 71.4 86.8 ; + RECT 69.36 86.6 69.56 86.8 ; + RECT 89.14 0.02 89.34 0.22 ; + RECT 59.7 0.02 59.9 0.22 ; + LAYER OVERLAP ; + POLYGON 0 0 0 76.16 30.36 76.16 30.36 87.04 103.96 87.04 103.96 0 ; + END +END sb_2__0_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_2__1__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_2__1__icv_in_design.lef new file mode 100644 index 0000000..1b79987 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_2__1__icv_in_design.lef @@ -0,0 +1,2310 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_2__1_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 103.96 BY 97.92 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.08 97.435 47.22 97.92 ; + END + END pReset[0] + PIN chany_top_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94.92 97.435 95.06 97.92 ; + END + END chany_top_in[0] + PIN chany_top_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 61.03 97.12 61.33 97.92 ; + END + END chany_top_in[1] + PIN chany_top_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.64 97.435 40.78 97.92 ; + END + END chany_top_in[2] + PIN chany_top_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 95.84 97.435 95.98 97.92 ; + END + END chany_top_in[3] + PIN chany_top_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.92 97.435 49.06 97.92 ; + END + END chany_top_in[4] + PIN chany_top_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 62.87 97.12 63.17 97.92 ; + END + END chany_top_in[5] + PIN chany_top_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 98.6 97.435 98.74 97.92 ; + END + END chany_top_in[6] + PIN chany_top_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.1 97.435 64.24 97.92 ; + END + END chany_top_in[7] + PIN chany_top_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.16 97.435 69.3 97.92 ; + END + END chany_top_in[8] + PIN chany_top_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 92.62 97.435 92.76 97.92 ; + END + END chany_top_in[9] + PIN chany_top_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.84 97.435 49.98 97.92 ; + END + END chany_top_in[10] + PIN chany_top_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.18 97.435 63.32 97.92 ; + END + END chany_top_in[11] + PIN chany_top_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.82 97.435 78.96 97.92 ; + END + END chany_top_in[12] + PIN chany_top_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.42 97.435 83.56 97.92 ; + END + END chany_top_in[13] + PIN chany_top_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.24 97.435 68.38 97.92 ; + END + END chany_top_in[14] + PIN chany_top_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.9 97.435 78.04 97.92 ; + END + END chany_top_in[15] + PIN chany_top_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.66 97.435 80.8 97.92 ; + END + END chany_top_in[16] + PIN chany_top_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 99.52 97.435 99.66 97.92 ; + END + END chany_top_in[17] + PIN chany_top_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 85.26 97.435 85.4 97.92 ; + END + END chany_top_in[18] + PIN chany_top_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.4 97.435 66.54 97.92 ; + END + END chany_top_in[19] + PIN chany_top_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48 97.435 48.14 97.92 ; + END + END chany_top_in[20] + PIN chany_top_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.74 97.435 56.88 97.92 ; + END + END chany_top_in[21] + PIN chany_top_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 37.88 97.435 38.02 97.92 ; + END + END chany_top_in[22] + PIN chany_top_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.56 97.435 41.7 97.92 ; + END + END chany_top_in[23] + PIN chany_top_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 97.68 97.435 97.82 97.92 ; + END + END chany_top_in[24] + PIN chany_top_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.58 97.435 81.72 97.92 ; + END + END chany_top_in[25] + PIN chany_top_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 101.36 97.435 101.5 97.92 ; + END + END chany_top_in[26] + PIN chany_top_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 72.07 97.12 72.37 97.92 ; + END + END chany_top_in[27] + PIN chany_top_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 91.7 97.435 91.84 97.92 ; + END + END chany_top_in[28] + PIN chany_top_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 100.44 97.435 100.58 97.92 ; + END + END chany_top_in[29] + PIN top_left_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 30.36 91.56 30.955 91.7 ; + END + END top_left_grid_pin_44_[0] + PIN top_left_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 86.555 14.1 87.04 ; + END + END top_left_grid_pin_45_[0] + PIN top_left_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 30.36 91.99 31.16 92.29 ; + END + END top_left_grid_pin_46_[0] + PIN top_left_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.82 86.555 9.96 87.04 ; + END + END top_left_grid_pin_47_[0] + PIN top_left_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.94 86.555 20.08 87.04 ; + END + END top_left_grid_pin_48_[0] + PIN top_left_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.56 86.555 18.7 87.04 ; + END + END top_left_grid_pin_49_[0] + PIN top_left_grid_pin_50_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 30.36 90.88 30.955 91.02 ; + END + END top_left_grid_pin_50_[0] + PIN top_left_grid_pin_51_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 17.64 86.555 17.78 87.04 ; + END + END top_left_grid_pin_51_[0] + PIN top_right_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 90.78 97.435 90.92 97.92 ; + END + END top_right_grid_pin_1_[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 62.87 0 63.17 0.8 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 61.03 0 61.33 0.8 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 64.71 0 65.01 0.8 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.24 0 45.38 0.485 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.62 0 69.76 0.485 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.3 0 96.44 0.485 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.92 0 49.06 0.485 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 88.02 0 88.16 0.485 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.46 0 71.6 0.485 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.38 0 72.52 0.485 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.66 0 57.8 0.485 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.16 0 46.3 0.485 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.28 0 56.42 0.485 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.9 0 78.04 0.485 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.58 0 58.72 0.485 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 92.62 0 92.76 0.485 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 91.7 0 91.84 0.485 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 95.38 0 95.52 0.485 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.42 0 60.56 0.485 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.08 0 47.22 0.485 ; + END + END chany_bottom_in[19] + PIN chany_bottom_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.3 0 73.44 0.485 ; + END + END chany_bottom_in[20] + PIN chany_bottom_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.58 0 81.72 0.485 ; + END + END chany_bottom_in[21] + PIN chany_bottom_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.18 0 86.32 0.485 ; + END + END chany_bottom_in[22] + PIN chany_bottom_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.54 0 70.68 0.485 ; + END + END chany_bottom_in[23] + PIN chany_bottom_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.72 0 62.86 0.485 ; + END + END chany_bottom_in[24] + PIN chany_bottom_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.54 0 93.68 0.485 ; + END + END chany_bottom_in[25] + PIN chany_bottom_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.34 0 61.48 0.485 ; + END + END chany_bottom_in[26] + PIN chany_bottom_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.36 0 55.5 0.485 ; + END + END chany_bottom_in[27] + PIN chany_bottom_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 90.78 0 90.92 0.485 ; + END + END chany_bottom_in[28] + PIN chany_bottom_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 87.1 0 87.24 0.485 ; + END + END chany_bottom_in[29] + PIN bottom_right_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.7 0 68.84 0.485 ; + END + END bottom_right_grid_pin_1_[0] + PIN bottom_left_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.44 10.88 8.58 11.365 ; + END + END bottom_left_grid_pin_44_[0] + PIN bottom_left_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.2 10.88 11.34 11.365 ; + END + END bottom_left_grid_pin_45_[0] + PIN bottom_left_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.84 10.88 3.98 11.365 ; + END + END bottom_left_grid_pin_46_[0] + PIN bottom_left_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.94 10.88 20.08 11.365 ; + END + END bottom_left_grid_pin_47_[0] + PIN bottom_left_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.02 10.88 19.16 11.365 ; + END + END bottom_left_grid_pin_48_[0] + PIN bottom_left_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.1 10.88 18.24 11.365 ; + END + END bottom_left_grid_pin_49_[0] + PIN bottom_left_grid_pin_50_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.72 10.88 16.86 11.365 ; + END + END bottom_left_grid_pin_50_[0] + PIN bottom_left_grid_pin_51_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.8 10.88 15.94 11.365 ; + END + END bottom_left_grid_pin_51_[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 49.83 0.8 50.13 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 50.42 0.595 50.56 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 69.46 0.595 69.6 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 79.66 0.595 79.8 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 30.79 0.8 31.09 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 47.7 0.595 47.84 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 52.55 0.8 52.85 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 45.75 0.8 46.05 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 51.19 0.8 51.49 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 53.14 0.595 53.28 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.31 0.8 40.61 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 44.39 0.8 44.69 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.03 0.8 43.33 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.98 0.595 45.12 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 74.9 0.595 75.04 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 29 0.595 29.14 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 77.62 0.595 77.76 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 82.38 0.595 82.52 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 52.46 0.595 52.6 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 72.18 0.595 72.32 ; + END + END chanx_left_in[19] + PIN chanx_left_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.11 0.8 47.41 ; + END + END chanx_left_in[20] + PIN chanx_left_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 71.5 0.595 71.64 ; + END + END chanx_left_in[21] + PIN chanx_left_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 48.47 0.8 48.77 ; + END + END chanx_left_in[22] + PIN chanx_left_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 55.52 0.595 55.66 ; + END + END chanx_left_in[23] + PIN chanx_left_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 53.91 0.8 54.21 ; + END + END chanx_left_in[24] + PIN chanx_left_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 47.02 0.595 47.16 ; + END + END chanx_left_in[25] + PIN chanx_left_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 49.74 0.595 49.88 ; + END + END chanx_left_in[26] + PIN chanx_left_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 41.67 0.8 41.97 ; + END + END chanx_left_in[27] + PIN chanx_left_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 80.34 0.595 80.48 ; + END + END chanx_left_in[28] + PIN chanx_left_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.23 0.8 36.53 ; + END + END chanx_left_in[29] + PIN left_bottom_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 30.36 5.63 31.16 5.93 ; + END + END left_bottom_grid_pin_36_[0] + PIN left_bottom_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 6.6 10.88 6.74 11.365 ; + END + END left_bottom_grid_pin_37_[0] + PIN left_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 30.36 6.22 30.955 6.36 ; + END + END left_bottom_grid_pin_38_[0] + PIN left_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.36 10.88 9.5 11.365 ; + END + END left_bottom_grid_pin_39_[0] + PIN left_bottom_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.04 10.88 13.18 11.365 ; + END + END left_bottom_grid_pin_40_[0] + PIN left_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 10.88 14.1 11.365 ; + END + END left_bottom_grid_pin_41_[0] + PIN left_bottom_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 7.52 10.88 7.66 11.365 ; + END + END left_bottom_grid_pin_42_[0] + PIN left_bottom_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.88 10.88 15.02 11.365 ; + END + END left_bottom_grid_pin_43_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.18 97.435 86.32 97.92 ; + END + END ccff_head[0] + PIN chany_top_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 89.86 97.435 90 97.92 ; + END + END chany_top_out[0] + PIN chany_top_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.34 97.435 84.48 97.92 ; + END + END chany_top_out[1] + PIN chany_top_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.5 97.435 82.64 97.92 ; + END + END chany_top_out[2] + PIN chany_top_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 88.02 97.435 88.16 97.92 ; + END + END chany_top_out[3] + PIN chany_top_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.76 97.435 50.9 97.92 ; + END + END chany_top_out[4] + PIN chany_top_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.34 97.435 61.48 97.92 ; + END + END chany_top_out[5] + PIN chany_top_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 87.1 97.435 87.24 97.92 ; + END + END chany_top_out[6] + PIN chany_top_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.82 97.435 55.96 97.92 ; + END + END chany_top_out[7] + PIN chany_top_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.9 97.435 55.04 97.92 ; + END + END chany_top_out[8] + PIN chany_top_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.12 97.435 58.26 97.92 ; + END + END chany_top_out[9] + PIN chany_top_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.52 97.435 53.66 97.92 ; + END + END chany_top_out[10] + PIN chany_top_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.3 97.435 73.44 97.92 ; + END + END chany_top_out[11] + PIN chany_top_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.02 97.435 65.16 97.92 ; + END + END chany_top_out[12] + PIN chany_top_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.76 97.435 96.9 97.92 ; + END + END chany_top_out[13] + PIN chany_top_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.74 97.435 79.88 97.92 ; + END + END chany_top_out[14] + PIN chany_top_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.98 97.435 77.12 97.92 ; + END + END chany_top_out[15] + PIN chany_top_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.6 97.435 52.74 97.92 ; + END + END chany_top_out[16] + PIN chany_top_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.22 97.435 74.36 97.92 ; + END + END chany_top_out[17] + PIN chany_top_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.26 97.435 62.4 97.92 ; + END + END chany_top_out[18] + PIN chany_top_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.32 97.435 67.46 97.92 ; + END + END chany_top_out[19] + PIN chany_top_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.08 97.435 70.22 97.92 ; + END + END chany_top_out[20] + PIN chany_top_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 59.04 97.435 59.18 97.92 ; + END + END chany_top_out[21] + PIN chany_top_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 43.86 97.435 44 97.92 ; + END + END chany_top_out[22] + PIN chany_top_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.38 97.435 72.52 97.92 ; + END + END chany_top_out[23] + PIN chany_top_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71 97.435 71.14 97.92 ; + END + END chany_top_out[24] + PIN chany_top_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.42 97.435 60.56 97.92 ; + END + END chany_top_out[25] + PIN chany_top_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.06 97.435 76.2 97.92 ; + END + END chany_top_out[26] + PIN chany_top_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.68 97.435 51.82 97.92 ; + END + END chany_top_out[27] + PIN chany_top_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.14 97.435 75.28 97.92 ; + END + END chany_top_out[28] + PIN chany_top_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94 97.435 94.14 97.92 ; + END + END chany_top_out[29] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 0 37.1 0.485 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.04 0 36.18 0.485 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.12 0 35.26 0.485 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.1 0 41.24 0.485 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.68 0 51.82 0.485 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.18 0 40.32 0.485 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.34 0 84.48 0.485 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.76 0 50.9 0.485 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 85.26 0 85.4 0.485 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.78 0 67.92 0.485 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.82 0 78.96 0.485 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.98 0 77.12 0.485 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.84 0 49.98 0.485 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.66 0 80.8 0.485 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.5 0 82.64 0.485 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.22 0 74.36 0.485 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.6 0 52.74 0.485 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.06 0 76.2 0.485 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.52 0 53.66 0.485 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.42 0 83.56 0.485 ; + END + END chany_bottom_out[19] + PIN chany_bottom_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.94 0 66.08 0.485 ; + END + END chany_bottom_out[20] + PIN chany_bottom_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 89.86 0 90 0.485 ; + END + END chany_bottom_out[21] + PIN chany_bottom_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.86 0 67 0.485 ; + END + END chany_bottom_out[22] + PIN chany_bottom_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 0 64.7 0.485 ; + END + END chany_bottom_out[23] + PIN chany_bottom_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.64 0 63.78 0.485 ; + END + END chany_bottom_out[24] + PIN chany_bottom_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48 0 48.14 0.485 ; + END + END chany_bottom_out[25] + PIN chany_bottom_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.74 0 79.88 0.485 ; + END + END chany_bottom_out[26] + PIN chany_bottom_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.44 0 54.58 0.485 ; + END + END chany_bottom_out[27] + PIN chany_bottom_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.14 0 75.28 0.485 ; + END + END chany_bottom_out[28] + PIN chany_bottom_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94.46 0 94.6 0.485 ; + END + END chany_bottom_out[29] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.04 0.595 31.18 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 28.07 0.8 28.37 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 39.54 0.595 39.68 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.82 0.595 36.96 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 25.94 0.595 26.08 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 32.15 0.8 32.45 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 38.86 0.595 39 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 26.71 0.8 27.01 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 34.44 0.595 34.58 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.3 0.595 44.44 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 33.51 0.8 33.81 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 29.43 0.8 29.73 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.72 0.595 31.86 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 76.94 0.595 77.08 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 25.35 0.8 25.65 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 41.58 0.595 41.72 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 56.63 0.8 56.93 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 42.26 0.595 42.4 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 28.32 0.595 28.46 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 83.06 0.595 83.2 ; + END + END chanx_left_out[19] + PIN chanx_left_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.14 0.595 36.28 ; + END + END chanx_left_out[20] + PIN chanx_left_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 37.59 0.8 37.89 ; + END + END chanx_left_out[21] + PIN chanx_left_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 25.26 0.595 25.4 ; + END + END chanx_left_out[22] + PIN chanx_left_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 74.22 0.595 74.36 ; + END + END chanx_left_out[23] + PIN chanx_left_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 68.78 0.595 68.92 ; + END + END chanx_left_out[24] + PIN chanx_left_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 55.27 0.8 55.57 ; + END + END chanx_left_out[25] + PIN chanx_left_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 38.95 0.8 39.25 ; + END + END chanx_left_out[26] + PIN chanx_left_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 34.87 0.8 35.17 ; + END + END chanx_left_out[27] + PIN chanx_left_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 33.76 0.595 33.9 ; + END + END chanx_left_out[28] + PIN chanx_left_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 22.54 0.595 22.68 ; + END + END chanx_left_out[29] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 56.2 0.595 56.34 ; + END + END ccff_tail[0] + PIN pReset_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 22.63 0.8 22.93 ; + END + END pReset_W_in + PIN pReset_N_out + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 97.435 37.1 97.92 ; + END + END pReset_N_out + PIN prog_clk_0_N_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 32.82 97.435 32.96 97.92 ; + END + END prog_clk_0_N_in + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 26.96 3.2 30.16 ; + RECT 100.76 26.96 103.96 30.16 ; + RECT 0 67.76 3.2 70.96 ; + RECT 100.76 67.76 103.96 70.96 ; + LAYER met4 ; + RECT 44.78 0 45.38 0.6 ; + RECT 74.22 0 74.82 0.6 ; + RECT 13.5 10.88 14.1 11.48 ; + RECT 13.5 86.44 14.1 87.04 ; + RECT 44.78 97.32 45.38 97.92 ; + RECT 74.22 97.32 74.82 97.92 ; + LAYER met1 ; + RECT 30.36 2.48 30.84 2.96 ; + RECT 103.48 2.48 103.96 2.96 ; + RECT 30.36 7.92 30.84 8.4 ; + RECT 103.48 7.92 103.96 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 103.48 13.36 103.96 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 103.48 18.8 103.96 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 103.48 24.24 103.96 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 103.48 29.68 103.96 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 103.48 35.12 103.96 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 103.48 40.56 103.96 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 103.48 46 103.96 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 103.48 51.44 103.96 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 103.48 56.88 103.96 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 103.48 62.32 103.96 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 103.48 67.76 103.96 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 103.48 73.2 103.96 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 103.48 78.64 103.96 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 103.48 84.08 103.96 84.56 ; + RECT 30.36 89.52 30.84 90 ; + RECT 103.48 89.52 103.96 90 ; + RECT 30.36 94.96 30.84 95.44 ; + RECT 103.48 94.96 103.96 95.44 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 47.36 3.2 50.56 ; + RECT 100.76 47.36 103.96 50.56 ; + LAYER met4 ; + RECT 59.5 0 60.1 0.6 ; + RECT 88.94 0 89.54 0.6 ; + RECT 59.5 97.32 60.1 97.92 ; + RECT 88.94 97.32 89.54 97.92 ; + LAYER met1 ; + RECT 30.36 -0.24 30.84 0.24 ; + RECT 103.48 -0.24 103.96 0.24 ; + RECT 30.36 5.2 30.84 5.68 ; + RECT 103.48 5.2 103.96 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 103.48 10.64 103.96 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 103.48 16.08 103.96 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 103.48 21.52 103.96 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 103.48 26.96 103.96 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 103.48 32.4 103.96 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 103.48 37.84 103.96 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 103.48 43.28 103.96 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 103.48 48.72 103.96 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 103.48 54.16 103.96 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 103.48 59.6 103.96 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 103.48 65.04 103.96 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 103.48 70.48 103.96 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 103.48 75.92 103.96 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 103.48 81.36 103.96 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 103.48 86.8 103.96 87.28 ; + RECT 30.36 92.24 30.84 92.72 ; + RECT 103.48 92.24 103.96 92.72 ; + RECT 30.36 97.68 30.84 98.16 ; + RECT 103.48 97.68 103.96 98.16 ; + END + END VSS + OBS + LAYER met2 ; + RECT 89.1 97.615 89.38 97.985 ; + RECT 59.66 97.615 59.94 97.985 ; + POLYGON 73.94 97.82 73.94 97.68 73.9 97.68 73.9 81.19 73.76 81.19 73.76 97.82 ; + POLYGON 52.32 97.82 52.32 97.68 52.28 97.68 52.28 86.63 52.14 86.63 52.14 97.82 ; + POLYGON 73.04 97.57 73.04 97 72.84 97 72.84 97.25 72.78 97.25 72.78 97.57 ; + RECT 71.4 97.25 71.66 97.57 ; + POLYGON 31.58 94.25 31.58 94.11 30.66 94.11 30.66 83.4 30.52 83.4 30.52 94.25 ; + POLYGON 21.99 86.885 21.99 86.515 21.92 86.515 21.92 81.02 21.78 81.02 21.78 86.515 21.71 86.515 21.71 86.885 ; + POLYGON 10.42 12.82 10.42 11.405 10.49 11.405 10.49 11.035 10.21 11.035 10.21 11.405 10.28 11.405 10.28 12.82 ; + POLYGON 30.66 12.48 30.66 4.49 31.58 4.49 31.58 4.35 30.52 4.35 30.52 12.48 ; + RECT 3.32 11.57 3.58 11.89 ; + POLYGON 73.9 10.44 73.9 0.24 73.94 0.24 73.94 0.1 73.76 0.1 73.76 10.44 ; + POLYGON 44 6.7 44 0.24 44.96 0.24 44.96 0.1 43.86 0.1 43.86 6.7 ; + RECT 37.36 0.35 37.62 0.67 ; + RECT 89.1 -0.065 89.38 0.305 ; + RECT 59.66 -0.065 59.94 0.305 ; + POLYGON 103.68 97.64 103.68 0.28 96.72 0.28 96.72 0.765 96.02 0.765 96.02 0.28 95.8 0.28 95.8 0.765 95.1 0.765 95.1 0.28 94.88 0.28 94.88 0.765 94.18 0.765 94.18 0.28 93.96 0.28 93.96 0.765 93.26 0.765 93.26 0.28 93.04 0.28 93.04 0.765 92.34 0.765 92.34 0.28 92.12 0.28 92.12 0.765 91.42 0.765 91.42 0.28 91.2 0.28 91.2 0.765 90.5 0.765 90.5 0.28 90.28 0.28 90.28 0.765 89.58 0.765 89.58 0.28 88.44 0.28 88.44 0.765 87.74 0.765 87.74 0.28 87.52 0.28 87.52 0.765 86.82 0.765 86.82 0.28 86.6 0.28 86.6 0.765 85.9 0.765 85.9 0.28 85.68 0.28 85.68 0.765 84.98 0.765 84.98 0.28 84.76 0.28 84.76 0.765 84.06 0.765 84.06 0.28 83.84 0.28 83.84 0.765 83.14 0.765 83.14 0.28 82.92 0.28 82.92 0.765 82.22 0.765 82.22 0.28 82 0.28 82 0.765 81.3 0.765 81.3 0.28 81.08 0.28 81.08 0.765 80.38 0.765 80.38 0.28 80.16 0.28 80.16 0.765 79.46 0.765 79.46 0.28 79.24 0.28 79.24 0.765 78.54 0.765 78.54 0.28 78.32 0.28 78.32 0.765 77.62 0.765 77.62 0.28 77.4 0.28 77.4 0.765 76.7 0.765 76.7 0.28 76.48 0.28 76.48 0.765 75.78 0.765 75.78 0.28 75.56 0.28 75.56 0.765 74.86 0.765 74.86 0.28 74.64 0.28 74.64 0.765 73.94 0.765 73.94 0.28 73.72 0.28 73.72 0.765 73.02 0.765 73.02 0.28 72.8 0.28 72.8 0.765 72.1 0.765 72.1 0.28 71.88 0.28 71.88 0.765 71.18 0.765 71.18 0.28 70.96 0.28 70.96 0.765 70.26 0.765 70.26 0.28 70.04 0.28 70.04 0.765 69.34 0.765 69.34 0.28 69.12 0.28 69.12 0.765 68.42 0.765 68.42 0.28 68.2 0.28 68.2 0.765 67.5 0.765 67.5 0.28 67.28 0.28 67.28 0.765 66.58 0.765 66.58 0.28 66.36 0.28 66.36 0.765 65.66 0.765 65.66 0.28 64.98 0.28 64.98 0.765 64.28 0.765 64.28 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 63.14 0.28 63.14 0.765 62.44 0.765 62.44 0.28 61.76 0.28 61.76 0.765 61.06 0.765 61.06 0.28 60.84 0.28 60.84 0.765 60.14 0.765 60.14 0.28 59 0.28 59 0.765 58.3 0.765 58.3 0.28 58.08 0.28 58.08 0.765 57.38 0.765 57.38 0.28 56.7 0.28 56.7 0.765 56 0.765 56 0.28 55.78 0.28 55.78 0.765 55.08 0.765 55.08 0.28 54.86 0.28 54.86 0.765 54.16 0.765 54.16 0.28 53.94 0.28 53.94 0.765 53.24 0.765 53.24 0.28 53.02 0.28 53.02 0.765 52.32 0.765 52.32 0.28 52.1 0.28 52.1 0.765 51.4 0.765 51.4 0.28 51.18 0.28 51.18 0.765 50.48 0.765 50.48 0.28 50.26 0.28 50.26 0.765 49.56 0.765 49.56 0.28 49.34 0.28 49.34 0.765 48.64 0.765 48.64 0.28 48.42 0.28 48.42 0.765 47.72 0.765 47.72 0.28 47.5 0.28 47.5 0.765 46.8 0.765 46.8 0.28 46.58 0.28 46.58 0.765 45.88 0.765 45.88 0.28 45.66 0.28 45.66 0.765 44.96 0.765 44.96 0.28 41.52 0.28 41.52 0.765 40.82 0.765 40.82 0.28 40.6 0.28 40.6 0.765 39.9 0.765 39.9 0.28 37.38 0.28 37.38 0.765 36.68 0.765 36.68 0.28 36.46 0.28 36.46 0.765 35.76 0.765 35.76 0.28 35.54 0.28 35.54 0.765 34.84 0.765 34.84 0.28 30.64 0.28 30.64 11.16 20.36 11.16 20.36 11.645 19.66 11.645 19.66 11.16 19.44 11.16 19.44 11.645 18.74 11.645 18.74 11.16 18.52 11.16 18.52 11.645 17.82 11.645 17.82 11.16 17.14 11.16 17.14 11.645 16.44 11.645 16.44 11.16 16.22 11.16 16.22 11.645 15.52 11.645 15.52 11.16 15.3 11.16 15.3 11.645 14.6 11.645 14.6 11.16 14.38 11.16 14.38 11.645 13.68 11.645 13.68 11.16 13.46 11.16 13.46 11.645 12.76 11.645 12.76 11.16 11.62 11.16 11.62 11.645 10.92 11.645 10.92 11.16 9.78 11.16 9.78 11.645 9.08 11.645 9.08 11.16 8.86 11.16 8.86 11.645 8.16 11.645 8.16 11.16 7.94 11.16 7.94 11.645 7.24 11.645 7.24 11.16 7.02 11.16 7.02 11.645 6.32 11.645 6.32 11.16 4.26 11.16 4.26 11.645 3.56 11.645 3.56 11.16 0.28 11.16 0.28 86.76 9.54 86.76 9.54 86.275 10.24 86.275 10.24 86.76 13.68 86.76 13.68 86.275 14.38 86.275 14.38 86.76 17.36 86.76 17.36 86.275 18.06 86.275 18.06 86.76 18.28 86.76 18.28 86.275 18.98 86.275 18.98 86.76 19.66 86.76 19.66 86.275 20.36 86.275 20.36 86.76 30.64 86.76 30.64 97.64 32.54 97.64 32.54 97.155 33.24 97.155 33.24 97.64 36.68 97.64 36.68 97.155 37.38 97.155 37.38 97.64 37.6 97.64 37.6 97.155 38.3 97.155 38.3 97.64 40.36 97.64 40.36 97.155 41.06 97.155 41.06 97.64 41.28 97.64 41.28 97.155 41.98 97.155 41.98 97.64 43.58 97.64 43.58 97.155 44.28 97.155 44.28 97.64 46.8 97.64 46.8 97.155 47.5 97.155 47.5 97.64 47.72 97.64 47.72 97.155 48.42 97.155 48.42 97.64 48.64 97.64 48.64 97.155 49.34 97.155 49.34 97.64 49.56 97.64 49.56 97.155 50.26 97.155 50.26 97.64 50.48 97.64 50.48 97.155 51.18 97.155 51.18 97.64 51.4 97.64 51.4 97.155 52.1 97.155 52.1 97.64 52.32 97.64 52.32 97.155 53.02 97.155 53.02 97.64 53.24 97.64 53.24 97.155 53.94 97.155 53.94 97.64 54.62 97.64 54.62 97.155 55.32 97.155 55.32 97.64 55.54 97.64 55.54 97.155 56.24 97.155 56.24 97.64 56.46 97.64 56.46 97.155 57.16 97.155 57.16 97.64 57.84 97.64 57.84 97.155 58.54 97.155 58.54 97.64 58.76 97.64 58.76 97.155 59.46 97.155 59.46 97.64 60.14 97.64 60.14 97.155 60.84 97.155 60.84 97.64 61.06 97.64 61.06 97.155 61.76 97.155 61.76 97.64 61.98 97.64 61.98 97.155 62.68 97.155 62.68 97.64 62.9 97.64 62.9 97.155 63.6 97.155 63.6 97.64 63.82 97.64 63.82 97.155 64.52 97.155 64.52 97.64 64.74 97.64 64.74 97.155 65.44 97.155 65.44 97.64 66.12 97.64 66.12 97.155 66.82 97.155 66.82 97.64 67.04 97.64 67.04 97.155 67.74 97.155 67.74 97.64 67.96 97.64 67.96 97.155 68.66 97.155 68.66 97.64 68.88 97.64 68.88 97.155 69.58 97.155 69.58 97.64 69.8 97.64 69.8 97.155 70.5 97.155 70.5 97.64 70.72 97.64 70.72 97.155 71.42 97.155 71.42 97.64 72.1 97.64 72.1 97.155 72.8 97.155 72.8 97.64 73.02 97.64 73.02 97.155 73.72 97.155 73.72 97.64 73.94 97.64 73.94 97.155 74.64 97.155 74.64 97.64 74.86 97.64 74.86 97.155 75.56 97.155 75.56 97.64 75.78 97.64 75.78 97.155 76.48 97.155 76.48 97.64 76.7 97.64 76.7 97.155 77.4 97.155 77.4 97.64 77.62 97.64 77.62 97.155 78.32 97.155 78.32 97.64 78.54 97.64 78.54 97.155 79.24 97.155 79.24 97.64 79.46 97.64 79.46 97.155 80.16 97.155 80.16 97.64 80.38 97.64 80.38 97.155 81.08 97.155 81.08 97.64 81.3 97.64 81.3 97.155 82 97.155 82 97.64 82.22 97.64 82.22 97.155 82.92 97.155 82.92 97.64 83.14 97.64 83.14 97.155 83.84 97.155 83.84 97.64 84.06 97.64 84.06 97.155 84.76 97.155 84.76 97.64 84.98 97.64 84.98 97.155 85.68 97.155 85.68 97.64 85.9 97.64 85.9 97.155 86.6 97.155 86.6 97.64 86.82 97.64 86.82 97.155 87.52 97.155 87.52 97.64 87.74 97.64 87.74 97.155 88.44 97.155 88.44 97.64 89.58 97.64 89.58 97.155 90.28 97.155 90.28 97.64 90.5 97.64 90.5 97.155 91.2 97.155 91.2 97.64 91.42 97.64 91.42 97.155 92.12 97.155 92.12 97.64 92.34 97.64 92.34 97.155 93.04 97.155 93.04 97.64 93.72 97.64 93.72 97.155 94.42 97.155 94.42 97.64 94.64 97.64 94.64 97.155 95.34 97.155 95.34 97.64 95.56 97.64 95.56 97.155 96.26 97.155 96.26 97.64 96.48 97.64 96.48 97.155 97.18 97.155 97.18 97.64 97.4 97.64 97.4 97.155 98.1 97.155 98.1 97.64 98.32 97.64 98.32 97.155 99.02 97.155 99.02 97.64 99.24 97.64 99.24 97.155 99.94 97.155 99.94 97.64 100.16 97.64 100.16 97.155 100.86 97.155 100.86 97.64 101.08 97.64 101.08 97.155 101.78 97.155 101.78 97.64 ; + LAYER met4 ; + POLYGON 39.265 97.745 39.265 97.415 39.25 97.415 39.25 62.75 38.95 62.75 38.95 97.415 38.935 97.415 38.935 97.745 ; + POLYGON 31.89 87.53 31.89 87.23 30.97 87.23 30.97 23.31 30.67 23.31 30.67 87.53 ; + POLYGON 103.56 97.52 103.56 0.4 89.94 0.4 89.94 1 88.54 1 88.54 0.4 75.22 0.4 75.22 1 73.82 1 73.82 0.4 65.41 0.4 65.41 1.2 64.31 1.2 64.31 0.4 63.57 0.4 63.57 1.2 62.47 1.2 62.47 0.4 61.73 0.4 61.73 1.2 60.63 1.2 60.63 0.4 60.5 0.4 60.5 1 59.1 1 59.1 0.4 45.78 0.4 45.78 1 44.38 1 44.38 0.4 30.76 0.4 30.76 11.28 14.5 11.28 14.5 11.88 13.1 11.88 13.1 11.28 0.4 11.28 0.4 86.64 13.1 86.64 13.1 86.04 14.5 86.04 14.5 86.64 30.76 86.64 30.76 97.52 44.38 97.52 44.38 96.92 45.78 96.92 45.78 97.52 59.1 97.52 59.1 96.92 60.5 96.92 60.5 97.52 60.63 97.52 60.63 96.72 61.73 96.72 61.73 97.52 62.47 97.52 62.47 96.72 63.57 96.72 63.57 97.52 71.67 97.52 71.67 96.72 72.77 96.72 72.77 97.52 73.82 97.52 73.82 96.92 75.22 96.92 75.22 97.52 88.54 97.52 88.54 96.92 89.94 96.92 89.94 97.52 ; + LAYER met1 ; + POLYGON 103.2 98.16 103.2 97.68 89.4 97.68 89.4 97.67 89.08 97.67 89.08 97.68 59.96 97.68 59.96 97.67 59.64 97.67 59.64 97.68 31.12 97.68 31.12 98.16 ; + RECT 0.76 86.8 71.16 87.28 ; + RECT 0.76 10.64 71.16 11.12 ; + POLYGON 89.4 0.25 89.4 0.24 103.2 0.24 103.2 -0.24 31.12 -0.24 31.12 0.24 59.64 0.24 59.64 0.25 59.96 0.25 59.96 0.24 89.08 0.24 89.08 0.25 ; + POLYGON 103.2 97.64 103.2 97.4 103.68 97.4 103.68 95.72 103.2 95.72 103.2 94.68 103.68 94.68 103.68 93 103.2 93 103.2 91.96 103.68 91.96 103.68 90.28 103.2 90.28 103.2 89.24 103.68 89.24 103.68 87.56 103.2 87.56 103.2 86.52 103.68 86.52 103.68 84.84 103.2 84.84 103.2 83.8 103.68 83.8 103.68 82.12 103.2 82.12 103.2 81.08 103.68 81.08 103.68 79.4 103.2 79.4 103.2 78.36 103.68 78.36 103.68 76.68 103.2 76.68 103.2 75.64 103.68 75.64 103.68 73.96 103.2 73.96 103.2 72.92 103.68 72.92 103.68 71.24 103.2 71.24 103.2 70.2 103.68 70.2 103.68 68.52 103.2 68.52 103.2 67.48 103.68 67.48 103.68 65.8 103.2 65.8 103.2 64.76 103.68 64.76 103.68 63.08 103.2 63.08 103.2 62.04 103.68 62.04 103.68 60.36 103.2 60.36 103.2 59.32 103.68 59.32 103.68 57.64 103.2 57.64 103.2 56.6 103.68 56.6 103.68 54.92 103.2 54.92 103.2 53.88 103.68 53.88 103.68 52.2 103.2 52.2 103.2 51.16 103.68 51.16 103.68 49.48 103.2 49.48 103.2 48.44 103.68 48.44 103.68 46.76 103.2 46.76 103.2 45.72 103.68 45.72 103.68 44.04 103.2 44.04 103.2 43 103.68 43 103.68 41.32 103.2 41.32 103.2 40.28 103.68 40.28 103.68 38.6 103.2 38.6 103.2 37.56 103.68 37.56 103.68 35.88 103.2 35.88 103.2 34.84 103.68 34.84 103.68 33.16 103.2 33.16 103.2 32.12 103.68 32.12 103.68 30.44 103.2 30.44 103.2 29.4 103.68 29.4 103.68 27.72 103.2 27.72 103.2 26.68 103.68 26.68 103.68 25 103.2 25 103.2 23.96 103.68 23.96 103.68 22.28 103.2 22.28 103.2 21.24 103.68 21.24 103.68 19.56 103.2 19.56 103.2 18.52 103.68 18.52 103.68 16.84 103.2 16.84 103.2 15.8 103.68 15.8 103.68 14.12 103.2 14.12 103.2 13.08 103.68 13.08 103.68 11.4 103.2 11.4 103.2 10.36 103.68 10.36 103.68 8.68 103.2 8.68 103.2 7.64 103.68 7.64 103.68 5.96 103.2 5.96 103.2 4.92 103.68 4.92 103.68 3.24 103.2 3.24 103.2 2.2 103.68 2.2 103.68 0.52 103.2 0.52 103.2 0.28 31.12 0.28 31.12 0.52 30.64 0.52 30.64 2.2 31.12 2.2 31.12 3.24 30.64 3.24 30.64 4.92 31.12 4.92 31.12 5.94 31.235 5.94 31.235 6.64 30.64 6.64 30.64 7.64 31.12 7.64 31.12 8.68 30.64 8.68 30.64 11.16 0.76 11.16 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.26 0.875 22.26 0.875 22.96 0.28 22.96 0.28 23.96 0.76 23.96 0.76 24.98 0.875 24.98 0.875 26.36 0.28 26.36 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 28.04 0.875 28.04 0.875 29.42 0.76 29.42 0.76 30.44 0.28 30.44 0.28 30.76 0.875 30.76 0.875 32.14 0.76 32.14 0.76 33.16 0.28 33.16 0.28 33.48 0.875 33.48 0.875 34.86 0.76 34.86 0.76 35.86 0.875 35.86 0.875 37.24 0.28 37.24 0.28 37.56 0.76 37.56 0.76 38.58 0.875 38.58 0.875 39.96 0.28 39.96 0.28 40.28 0.76 40.28 0.76 41.3 0.875 41.3 0.875 42.68 0.28 42.68 0.28 43 0.76 43 0.76 44.02 0.875 44.02 0.875 45.4 0.28 45.4 0.28 45.72 0.76 45.72 0.76 46.74 0.875 46.74 0.875 48.12 0.28 48.12 0.28 48.44 0.76 48.44 0.76 49.46 0.875 49.46 0.875 50.84 0.28 50.84 0.28 51.16 0.76 51.16 0.76 52.18 0.875 52.18 0.875 53.56 0.28 53.56 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 55.24 0.875 55.24 0.875 56.62 0.76 56.62 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.5 0.875 68.5 0.875 69.88 0.28 69.88 0.28 70.2 0.76 70.2 0.76 71.22 0.875 71.22 0.875 72.6 0.28 72.6 0.28 72.92 0.76 72.92 0.76 73.94 0.875 73.94 0.875 75.32 0.28 75.32 0.28 75.64 0.76 75.64 0.76 76.66 0.875 76.66 0.875 78.04 0.28 78.04 0.28 78.36 0.76 78.36 0.76 79.38 0.875 79.38 0.875 80.76 0.28 80.76 0.28 81.08 0.76 81.08 0.76 82.1 0.875 82.1 0.875 83.48 0.28 83.48 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 86.76 30.64 86.76 30.64 89.24 31.12 89.24 31.12 90.28 30.64 90.28 30.64 90.6 31.235 90.6 31.235 91.98 31.12 91.98 31.12 93 30.64 93 30.64 94.68 31.12 94.68 31.12 95.72 30.64 95.72 30.64 97.4 31.12 97.4 31.12 97.64 ; + LAYER met3 ; + POLYGON 89.405 97.965 89.405 97.96 89.62 97.96 89.62 97.64 89.405 97.64 89.405 97.635 89.075 97.635 89.075 97.64 88.86 97.64 88.86 97.96 89.075 97.96 89.075 97.965 ; + POLYGON 59.965 97.965 59.965 97.96 60.18 97.96 60.18 97.64 59.965 97.64 59.965 97.635 59.635 97.635 59.635 97.64 59.42 97.64 59.42 97.96 59.635 97.96 59.635 97.965 ; + POLYGON 40.875 97.745 40.875 97.415 40.545 97.415 40.545 97.43 39.29 97.43 39.29 97.42 38.91 97.42 38.91 97.74 39.29 97.74 39.29 97.73 40.545 97.73 40.545 97.745 ; + POLYGON 22.015 86.865 22.015 86.85 52.36 86.85 52.36 86.55 22.015 86.55 22.015 86.535 21.685 86.535 21.685 86.865 ; + POLYGON 25.45 42.65 25.45 42.35 1.2 42.35 1.2 42.37 0.65 42.37 0.65 42.65 ; + POLYGON 10.515 11.385 10.515 11.37 41.09 11.37 41.09 11.07 10.515 11.07 10.515 11.055 10.185 11.055 10.185 11.385 ; + POLYGON 89.405 0.285 89.405 0.28 89.62 0.28 89.62 -0.04 89.405 -0.04 89.405 -0.045 89.075 -0.045 89.075 -0.04 88.86 -0.04 88.86 0.28 89.075 0.28 89.075 0.285 ; + POLYGON 59.965 0.285 59.965 0.28 60.18 0.28 60.18 -0.04 59.965 -0.04 59.965 -0.045 59.635 -0.045 59.635 -0.04 59.42 -0.04 59.42 0.28 59.635 0.28 59.635 0.285 ; + POLYGON 103.56 97.52 103.56 0.4 30.76 0.4 30.76 5.23 31.56 5.23 31.56 6.33 30.76 6.33 30.76 11.28 0.4 11.28 0.4 22.23 1.2 22.23 1.2 23.33 0.4 23.33 0.4 24.95 1.2 24.95 1.2 26.05 0.4 26.05 0.4 26.31 1.2 26.31 1.2 27.41 0.4 27.41 0.4 27.67 1.2 27.67 1.2 28.77 0.4 28.77 0.4 29.03 1.2 29.03 1.2 30.13 0.4 30.13 0.4 30.39 1.2 30.39 1.2 31.49 0.4 31.49 0.4 31.75 1.2 31.75 1.2 32.85 0.4 32.85 0.4 33.11 1.2 33.11 1.2 34.21 0.4 34.21 0.4 34.47 1.2 34.47 1.2 35.57 0.4 35.57 0.4 35.83 1.2 35.83 1.2 36.93 0.4 36.93 0.4 37.19 1.2 37.19 1.2 38.29 0.4 38.29 0.4 38.55 1.2 38.55 1.2 39.65 0.4 39.65 0.4 39.91 1.2 39.91 1.2 41.01 0.4 41.01 0.4 41.27 1.2 41.27 1.2 42.37 0.4 42.37 0.4 42.63 1.2 42.63 1.2 43.73 0.4 43.73 0.4 43.99 1.2 43.99 1.2 45.09 0.4 45.09 0.4 45.35 1.2 45.35 1.2 46.45 0.4 46.45 0.4 46.71 1.2 46.71 1.2 47.81 0.4 47.81 0.4 48.07 1.2 48.07 1.2 49.17 0.4 49.17 0.4 49.43 1.2 49.43 1.2 50.53 0.4 50.53 0.4 50.79 1.2 50.79 1.2 51.89 0.4 51.89 0.4 52.15 1.2 52.15 1.2 53.25 0.4 53.25 0.4 53.51 1.2 53.51 1.2 54.61 0.4 54.61 0.4 54.87 1.2 54.87 1.2 55.97 0.4 55.97 0.4 56.23 1.2 56.23 1.2 57.33 0.4 57.33 0.4 86.64 30.76 86.64 30.76 91.59 31.56 91.59 31.56 92.69 30.76 92.69 30.76 97.52 ; + LAYER met5 ; + POLYGON 102.36 96.32 102.36 72.56 99.16 72.56 99.16 66.16 102.36 66.16 102.36 52.16 99.16 52.16 99.16 45.76 102.36 45.76 102.36 31.76 99.16 31.76 99.16 25.36 102.36 25.36 102.36 1.6 31.96 1.6 31.96 12.48 1.6 12.48 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 85.44 31.96 85.44 31.96 96.32 ; + LAYER li1 ; + POLYGON 103.96 98.005 103.96 97.835 100.725 97.835 100.725 97.035 100.395 97.035 100.395 97.835 99.885 97.835 99.885 97.355 99.555 97.355 99.555 97.835 99.045 97.835 99.045 97.355 98.715 97.355 98.715 97.835 98.205 97.835 98.205 97.355 97.875 97.355 97.875 97.835 97.365 97.835 97.365 97.355 97.035 97.355 97.035 97.835 96.525 97.835 96.525 97.355 96.195 97.355 96.195 97.835 95.04 97.835 95.04 97.375 94.715 97.375 94.715 97.835 92.925 97.835 92.925 97.375 92.655 97.375 92.655 97.835 91.485 97.835 91.485 97.355 91.155 97.355 91.155 97.835 90.645 97.835 90.645 97.355 90.315 97.355 90.315 97.835 89.805 97.835 89.805 97.355 89.475 97.355 89.475 97.835 88.965 97.835 88.965 97.355 88.635 97.355 88.635 97.835 88.125 97.835 88.125 97.355 87.795 97.355 87.795 97.835 87.285 97.835 87.285 97.035 86.955 97.035 86.955 97.835 86.225 97.835 86.225 97.375 85.97 97.375 85.97 97.835 85.3 97.835 85.3 97.375 85.13 97.375 85.13 97.835 84.46 97.835 84.46 97.375 84.29 97.375 84.29 97.835 83.62 97.835 83.62 97.375 83.45 97.375 83.45 97.835 82.78 97.835 82.78 97.375 82.475 97.375 82.475 97.835 81.865 97.835 81.865 97.035 81.535 97.035 81.535 97.835 81.025 97.835 81.025 97.355 80.695 97.355 80.695 97.835 80.185 97.835 80.185 97.355 79.855 97.355 79.855 97.835 79.345 97.835 79.345 97.355 79.015 97.355 79.015 97.835 78.505 97.835 78.505 97.355 78.175 97.355 78.175 97.835 77.665 97.835 77.665 97.355 77.335 97.355 77.335 97.835 76.265 97.835 76.265 97.035 75.935 97.035 75.935 97.835 75.425 97.835 75.425 97.355 75.095 97.355 75.095 97.835 74.585 97.835 74.585 97.355 74.255 97.355 74.255 97.835 73.665 97.835 73.665 97.355 73.495 97.355 73.495 97.835 72.825 97.835 72.825 97.355 72.655 97.355 72.655 97.835 71.745 97.835 71.745 97.035 71.415 97.035 71.415 97.835 70.905 97.835 70.905 97.355 70.575 97.355 70.575 97.835 70.065 97.835 70.065 97.355 69.735 97.355 69.735 97.835 69.225 97.835 69.225 97.355 68.895 97.355 68.895 97.835 68.385 97.835 68.385 97.355 68.055 97.355 68.055 97.835 67.545 97.835 67.545 97.355 67.215 97.355 67.215 97.835 66.225 97.835 66.225 97.035 65.895 97.035 65.895 97.835 65.385 97.835 65.385 97.355 65.055 97.355 65.055 97.835 64.545 97.835 64.545 97.355 64.215 97.355 64.215 97.835 63.705 97.835 63.705 97.355 63.375 97.355 63.375 97.835 62.865 97.835 62.865 97.355 62.535 97.355 62.535 97.835 62.025 97.835 62.025 97.355 61.695 97.355 61.695 97.835 60.205 97.835 60.205 97.355 59.875 97.355 59.875 97.835 59.365 97.835 59.365 97.355 59.035 97.355 59.035 97.835 58.525 97.835 58.525 97.355 58.195 97.355 58.195 97.835 57.685 97.835 57.685 97.355 57.355 97.355 57.355 97.835 56.845 97.835 56.845 97.355 56.515 97.355 56.515 97.835 56.005 97.835 56.005 97.035 55.675 97.035 55.675 97.835 53.725 97.835 53.725 97.035 53.395 97.035 53.395 97.835 52.885 97.835 52.885 97.355 52.555 97.355 52.555 97.835 52.045 97.835 52.045 97.355 51.715 97.355 51.715 97.835 51.125 97.835 51.125 97.355 50.955 97.355 50.955 97.835 50.285 97.835 50.285 97.355 50.115 97.355 50.115 97.835 49.165 97.835 49.165 97.355 48.835 97.355 48.835 97.835 48.325 97.835 48.325 97.355 47.995 97.355 47.995 97.835 47.485 97.835 47.485 97.355 47.155 97.355 47.155 97.835 46.645 97.835 46.645 97.355 46.315 97.355 46.315 97.835 45.805 97.835 45.805 97.355 45.475 97.355 45.475 97.835 44.965 97.835 44.965 97.035 44.635 97.035 44.635 97.835 43.645 97.835 43.645 97.355 43.315 97.355 43.315 97.835 42.805 97.835 42.805 97.355 42.475 97.355 42.475 97.835 41.965 97.835 41.965 97.355 41.635 97.355 41.635 97.835 41.125 97.835 41.125 97.355 40.795 97.355 40.795 97.835 40.285 97.835 40.285 97.355 39.955 97.355 39.955 97.835 39.445 97.835 39.445 97.035 39.115 97.035 39.115 97.835 38.125 97.835 38.125 97.355 37.795 97.355 37.795 97.835 37.285 97.835 37.285 97.355 36.955 97.355 36.955 97.835 36.445 97.835 36.445 97.355 36.115 97.355 36.115 97.835 35.605 97.835 35.605 97.355 35.275 97.355 35.275 97.835 34.765 97.835 34.765 97.355 34.435 97.355 34.435 97.835 33.925 97.835 33.925 97.035 33.595 97.035 33.595 97.835 30.36 97.835 30.36 98.005 ; + RECT 103.04 95.115 103.96 95.285 ; + RECT 30.36 95.115 34.04 95.285 ; + RECT 103.04 92.395 103.96 92.565 ; + RECT 30.36 92.395 34.04 92.565 ; + RECT 103.04 89.675 103.96 89.845 ; + RECT 30.36 89.675 32.2 89.845 ; + RECT 103.04 86.955 103.96 87.125 ; + POLYGON 32.2 87.125 32.2 86.955 31.945 86.955 31.945 86.495 31.69 86.495 31.69 86.955 31.02 86.955 31.02 86.495 30.85 86.495 30.85 86.955 30.18 86.955 30.18 86.495 30.01 86.495 30.01 86.955 29.34 86.955 29.34 86.495 29.17 86.495 29.17 86.955 28.5 86.955 28.5 86.495 28.195 86.495 28.195 86.955 26.625 86.955 26.625 86.495 26.32 86.495 26.32 86.955 24.835 86.955 24.835 86.515 24.645 86.515 24.645 86.955 22.745 86.955 22.745 86.495 22.415 86.495 22.415 86.955 19.815 86.955 19.815 86.595 19.485 86.595 19.485 86.955 18.785 86.955 18.785 86.575 18.455 86.575 18.455 86.955 15.73 86.955 15.73 86.135 15.5 86.135 15.5 86.955 13.735 86.955 13.735 86.575 13.405 86.575 13.405 86.955 11.445 86.955 11.445 86.495 11.14 86.495 11.14 86.955 9.655 86.955 9.655 86.515 9.465 86.515 9.465 86.955 7.565 86.955 7.565 86.495 7.235 86.495 7.235 86.955 4.635 86.955 4.635 86.595 4.305 86.595 4.305 86.955 3.605 86.955 3.605 86.575 3.275 86.575 3.275 86.955 0 86.955 0 87.125 ; + RECT 103.04 84.235 103.96 84.405 ; + RECT 0 84.235 1.84 84.405 ; + RECT 103.04 81.515 103.96 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 100.28 78.795 103.96 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 100.28 76.075 103.96 76.245 ; + RECT 0 76.075 1.84 76.245 ; + RECT 103.04 73.355 103.96 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 103.04 70.635 103.96 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 103.04 67.915 103.96 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 103.04 65.195 103.96 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 103.04 62.475 103.96 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 103.04 59.755 103.96 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 100.28 57.035 103.96 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 100.28 54.315 103.96 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 103.04 51.595 103.96 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 103.04 48.875 103.96 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 103.04 46.155 103.96 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 103.04 43.435 103.96 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 100.28 40.715 103.96 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 100.28 37.995 103.96 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 103.04 35.275 103.96 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 103.04 32.555 103.96 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 103.04 29.835 103.96 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 103.04 27.115 103.96 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 103.04 24.395 103.96 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 103.04 21.675 103.96 21.845 ; + RECT 0 21.675 1.84 21.845 ; + RECT 100.28 18.955 103.96 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 100.28 16.235 103.96 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 103.04 13.515 103.96 13.685 ; + RECT 0 13.515 1.84 13.685 ; + POLYGON 17.16 11.785 17.16 10.965 18.075 10.965 18.075 11.425 18.38 11.425 18.38 10.965 19.05 10.965 19.05 11.425 19.22 11.425 19.22 10.965 19.89 10.965 19.89 11.425 20.06 11.425 20.06 10.965 20.73 10.965 20.73 11.425 20.9 11.425 20.9 10.965 21.57 10.965 21.57 11.425 21.825 11.425 21.825 10.965 22.675 10.965 22.675 11.425 22.98 11.425 22.98 10.965 23.65 10.965 23.65 11.425 23.82 11.425 23.82 10.965 24.49 10.965 24.49 11.425 24.66 11.425 24.66 10.965 25.33 10.965 25.33 11.425 25.5 11.425 25.5 10.965 26.17 10.965 26.17 11.425 26.425 11.425 26.425 10.965 27.575 10.965 27.575 11.445 27.745 11.445 27.745 10.965 28.415 10.965 28.415 11.445 28.585 11.445 28.585 10.965 29.175 10.965 29.175 11.445 29.505 11.445 29.505 10.965 30.015 10.965 30.015 11.445 30.345 11.445 30.345 10.965 30.855 10.965 30.855 11.765 31.185 11.765 31.185 10.965 32.2 10.965 32.2 10.795 0 10.795 0 10.965 3.015 10.965 3.015 11.425 3.27 11.425 3.27 10.965 3.94 10.965 3.94 11.425 4.11 11.425 4.11 10.965 4.78 10.965 4.78 11.425 4.95 11.425 4.95 10.965 5.62 10.965 5.62 11.425 5.79 11.425 5.79 10.965 6.46 10.965 6.46 11.425 6.765 11.425 6.765 10.965 8.19 10.965 8.19 11.785 8.42 11.785 8.42 10.965 9.57 10.965 9.57 11.785 9.8 11.785 9.8 10.965 11.055 10.965 11.055 11.765 11.385 11.765 11.385 10.965 11.895 10.965 11.895 11.445 12.225 11.445 12.225 10.965 12.735 10.965 12.735 11.445 13.065 11.445 13.065 10.965 13.575 10.965 13.575 11.445 13.905 11.445 13.905 10.965 14.415 10.965 14.415 11.445 14.745 11.445 14.745 10.965 15.255 10.965 15.255 11.445 15.585 11.445 15.585 10.965 16.93 10.965 16.93 11.785 ; + RECT 103.04 10.795 103.96 10.965 ; + RECT 103.04 8.075 103.96 8.245 ; + RECT 30.36 8.075 32.2 8.245 ; + RECT 103.04 5.355 103.96 5.525 ; + RECT 30.36 5.355 32.2 5.525 ; + RECT 103.04 2.635 103.96 2.805 ; + RECT 30.36 2.635 34.04 2.805 ; + POLYGON 100.725 0.885 100.725 0.085 103.96 0.085 103.96 -0.085 30.36 -0.085 30.36 0.085 36.775 0.085 36.775 0.565 36.945 0.565 36.945 0.085 37.615 0.085 37.615 0.565 37.785 0.565 37.785 0.085 38.375 0.085 38.375 0.565 38.705 0.565 38.705 0.085 39.215 0.085 39.215 0.565 39.545 0.565 39.545 0.085 40.055 0.085 40.055 0.885 40.385 0.885 40.385 0.085 42.335 0.085 42.335 0.885 42.665 0.885 42.665 0.085 43.175 0.085 43.175 0.565 43.505 0.565 43.505 0.085 44.015 0.085 44.015 0.565 44.345 0.565 44.345 0.085 44.855 0.085 44.855 0.565 45.185 0.565 45.185 0.085 45.695 0.085 45.695 0.565 46.025 0.565 46.025 0.085 46.535 0.085 46.535 0.565 46.865 0.565 46.865 0.085 47.895 0.085 47.895 0.565 48.225 0.565 48.225 0.085 48.735 0.085 48.735 0.565 49.065 0.565 49.065 0.085 49.575 0.085 49.575 0.565 49.905 0.565 49.905 0.085 50.415 0.085 50.415 0.565 50.745 0.565 50.745 0.085 51.255 0.085 51.255 0.565 51.585 0.565 51.585 0.085 52.095 0.085 52.095 0.885 52.425 0.885 52.425 0.085 53.375 0.085 53.375 0.885 53.705 0.885 53.705 0.085 54.215 0.085 54.215 0.565 54.545 0.565 54.545 0.085 55.055 0.085 55.055 0.565 55.385 0.565 55.385 0.085 55.895 0.085 55.895 0.565 56.225 0.565 56.225 0.085 56.735 0.085 56.735 0.565 57.065 0.565 57.065 0.085 57.575 0.085 57.575 0.565 57.905 0.565 57.905 0.085 58.895 0.085 58.895 0.885 59.225 0.885 59.225 0.085 59.735 0.085 59.735 0.565 60.065 0.565 60.065 0.085 60.575 0.085 60.575 0.565 60.905 0.565 60.905 0.085 61.415 0.085 61.415 0.565 61.745 0.565 61.745 0.085 62.255 0.085 62.255 0.565 62.585 0.565 62.585 0.085 63.095 0.085 63.095 0.565 63.425 0.565 63.425 0.085 64.415 0.085 64.415 0.885 64.745 0.885 64.745 0.085 65.255 0.085 65.255 0.565 65.585 0.565 65.585 0.085 66.095 0.085 66.095 0.565 66.425 0.565 66.425 0.085 66.935 0.085 66.935 0.565 67.265 0.565 67.265 0.085 67.775 0.085 67.775 0.565 68.105 0.565 68.105 0.085 68.615 0.085 68.615 0.565 68.945 0.565 68.945 0.085 69.935 0.085 69.935 0.885 70.265 0.885 70.265 0.085 70.775 0.085 70.775 0.565 71.105 0.565 71.105 0.085 71.615 0.085 71.615 0.565 71.945 0.565 71.945 0.085 72.455 0.085 72.455 0.565 72.785 0.565 72.785 0.085 73.295 0.085 73.295 0.565 73.625 0.565 73.625 0.085 74.135 0.085 74.135 0.565 74.465 0.565 74.465 0.085 75.115 0.085 75.115 0.545 75.42 0.545 75.42 0.085 76.09 0.085 76.09 0.545 76.26 0.545 76.26 0.085 76.93 0.085 76.93 0.545 77.1 0.545 77.1 0.085 77.77 0.085 77.77 0.545 77.94 0.545 77.94 0.085 78.61 0.085 78.61 0.545 78.865 0.545 78.865 0.085 79.595 0.085 79.595 0.885 79.925 0.885 79.925 0.085 80.435 0.085 80.435 0.565 80.765 0.565 80.765 0.085 81.275 0.085 81.275 0.565 81.605 0.565 81.605 0.085 82.115 0.085 82.115 0.565 82.445 0.565 82.445 0.085 82.955 0.085 82.955 0.565 83.285 0.565 83.285 0.085 83.795 0.085 83.795 0.565 84.125 0.565 84.125 0.085 85.115 0.085 85.115 0.885 85.445 0.885 85.445 0.085 85.955 0.085 85.955 0.565 86.285 0.565 86.285 0.085 86.795 0.085 86.795 0.565 87.125 0.565 87.125 0.085 87.635 0.085 87.635 0.565 87.965 0.565 87.965 0.085 88.475 0.085 88.475 0.565 88.805 0.565 88.805 0.085 89.315 0.085 89.315 0.565 89.645 0.565 89.645 0.085 90.675 0.085 90.675 0.565 91.005 0.565 91.005 0.085 91.515 0.085 91.515 0.565 91.845 0.565 91.845 0.085 92.355 0.085 92.355 0.565 92.685 0.565 92.685 0.085 93.195 0.085 93.195 0.565 93.525 0.565 93.525 0.085 94.035 0.085 94.035 0.565 94.365 0.565 94.365 0.085 94.875 0.085 94.875 0.885 95.205 0.885 95.205 0.085 96.195 0.085 96.195 0.565 96.525 0.565 96.525 0.085 97.035 0.085 97.035 0.565 97.365 0.565 97.365 0.085 97.875 0.085 97.875 0.565 98.205 0.565 98.205 0.085 98.715 0.085 98.715 0.565 99.045 0.565 99.045 0.085 99.555 0.085 99.555 0.565 99.885 0.565 99.885 0.085 100.395 0.085 100.395 0.885 ; + POLYGON 103.79 97.75 103.79 0.17 30.53 0.17 30.53 11.05 0.17 11.05 0.17 86.87 30.53 86.87 30.53 97.75 ; + LAYER via ; + RECT 89.165 97.725 89.315 97.875 ; + RECT 59.725 97.725 59.875 97.875 ; + RECT 97.675 97.335 97.825 97.485 ; + RECT 53.515 97.335 53.665 97.485 ; + RECT 68.695 0.435 68.845 0.585 ; + RECT 89.165 0.045 89.315 0.195 ; + RECT 59.725 0.045 59.875 0.195 ; + LAYER via2 ; + RECT 89.14 97.7 89.34 97.9 ; + RECT 59.7 97.7 59.9 97.9 ; + RECT 40.61 97.48 40.81 97.68 ; + RECT 21.75 86.6 21.95 86.8 ; + RECT 1.05 56.68 1.25 56.88 ; + RECT 1.05 28.12 1.25 28.32 ; + RECT 10.25 11.12 10.45 11.32 ; + RECT 89.14 0.02 89.34 0.22 ; + RECT 59.7 0.02 59.9 0.22 ; + LAYER via3 ; + RECT 89.14 97.7 89.34 97.9 ; + RECT 59.7 97.7 59.9 97.9 ; + RECT 39 97.48 39.2 97.68 ; + RECT 61.08 96.8 61.28 97 ; + RECT 89.14 0.02 89.34 0.22 ; + RECT 59.7 0.02 59.9 0.22 ; + LAYER OVERLAP ; + POLYGON 30.36 0 30.36 10.88 0 10.88 0 87.04 30.36 87.04 30.36 97.92 103.96 97.92 103.96 0 ; + END +END sb_2__1_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_2__2__icv_in_design.lef b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_2__2__icv_in_design.lef new file mode 100644 index 0000000..d0802eb --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/lef/sb_2__2__icv_in_design.lef @@ -0,0 +1,1747 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +MACRO sb_2__2_ + CLASS BLOCK ; + ORIGIN 0 0 ; + SIZE 103.96 BY 87.04 ; + SYMMETRY X Y ; + PIN pReset[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.14 86.555 52.28 87.04 ; + END + END pReset[0] + PIN chany_bottom_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 62.87 0 63.17 0.8 ; + END + END chany_bottom_in[0] + PIN chany_bottom_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 61.03 0 61.33 0.8 ; + END + END chany_bottom_in[1] + PIN chany_bottom_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 64.71 0 65.01 0.8 ; + END + END chany_bottom_in[2] + PIN chany_bottom_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 45.24 0 45.38 0.485 ; + END + END chany_bottom_in[3] + PIN chany_bottom_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 69.62 0 69.76 0.485 ; + END + END chany_bottom_in[4] + PIN chany_bottom_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 96.3 0 96.44 0.485 ; + END + END chany_bottom_in[5] + PIN chany_bottom_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48.92 0 49.06 0.485 ; + END + END chany_bottom_in[6] + PIN chany_bottom_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 88.02 0 88.16 0.485 ; + END + END chany_bottom_in[7] + PIN chany_bottom_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 71.46 0 71.6 0.485 ; + END + END chany_bottom_in[8] + PIN chany_bottom_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 72.38 0 72.52 0.485 ; + END + END chany_bottom_in[9] + PIN chany_bottom_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 57.66 0 57.8 0.485 ; + END + END chany_bottom_in[10] + PIN chany_bottom_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 46.16 0 46.3 0.485 ; + END + END chany_bottom_in[11] + PIN chany_bottom_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 56.28 0 56.42 0.485 ; + END + END chany_bottom_in[12] + PIN chany_bottom_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 77.9 0 78.04 0.485 ; + END + END chany_bottom_in[13] + PIN chany_bottom_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 58.58 0 58.72 0.485 ; + END + END chany_bottom_in[14] + PIN chany_bottom_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 92.62 0 92.76 0.485 ; + END + END chany_bottom_in[15] + PIN chany_bottom_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 91.7 0 91.84 0.485 ; + END + END chany_bottom_in[16] + PIN chany_bottom_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 95.38 0 95.52 0.485 ; + END + END chany_bottom_in[17] + PIN chany_bottom_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 60.42 0 60.56 0.485 ; + END + END chany_bottom_in[18] + PIN chany_bottom_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 47.08 0 47.22 0.485 ; + END + END chany_bottom_in[19] + PIN chany_bottom_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 73.3 0 73.44 0.485 ; + END + END chany_bottom_in[20] + PIN chany_bottom_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 81.58 0 81.72 0.485 ; + END + END chany_bottom_in[21] + PIN chany_bottom_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 86.18 0 86.32 0.485 ; + END + END chany_bottom_in[22] + PIN chany_bottom_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.54 0 70.68 0.485 ; + END + END chany_bottom_in[23] + PIN chany_bottom_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 62.72 0 62.86 0.485 ; + END + END chany_bottom_in[24] + PIN chany_bottom_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 93.54 0 93.68 0.485 ; + END + END chany_bottom_in[25] + PIN chany_bottom_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 61.34 0 61.48 0.485 ; + END + END chany_bottom_in[26] + PIN chany_bottom_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 55.36 0 55.5 0.485 ; + END + END chany_bottom_in[27] + PIN chany_bottom_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 90.78 0 90.92 0.485 ; + END + END chany_bottom_in[28] + PIN chany_bottom_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 87.1 0 87.24 0.485 ; + END + END chany_bottom_in[29] + PIN bottom_right_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 68.7 0 68.84 0.485 ; + END + END bottom_right_grid_pin_1_[0] + PIN bottom_left_grid_pin_44_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.44 10.88 8.58 11.365 ; + END + END bottom_left_grid_pin_44_[0] + PIN bottom_left_grid_pin_45_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 11.2 10.88 11.34 11.365 ; + END + END bottom_left_grid_pin_45_[0] + PIN bottom_left_grid_pin_46_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 3.84 10.88 3.98 11.365 ; + END + END bottom_left_grid_pin_46_[0] + PIN bottom_left_grid_pin_47_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.94 10.88 20.08 11.365 ; + END + END bottom_left_grid_pin_47_[0] + PIN bottom_left_grid_pin_48_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 19.02 10.88 19.16 11.365 ; + END + END bottom_left_grid_pin_48_[0] + PIN bottom_left_grid_pin_49_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 18.1 10.88 18.24 11.365 ; + END + END bottom_left_grid_pin_49_[0] + PIN bottom_left_grid_pin_50_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 16.72 10.88 16.86 11.365 ; + END + END bottom_left_grid_pin_50_[0] + PIN bottom_left_grid_pin_51_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 15.8 10.88 15.94 11.365 ; + END + END bottom_left_grid_pin_51_[0] + PIN chanx_left_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 38.86 0.595 39 ; + END + END chanx_left_in[0] + PIN chanx_left_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 24.67 0.8 24.97 ; + END + END chanx_left_in[1] + PIN chanx_left_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 43.71 0.8 44.01 ; + END + END chanx_left_in[2] + PIN chanx_left_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 20.84 0.595 20.98 ; + END + END chanx_left_in[3] + PIN chanx_left_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 27.39 0.8 27.69 ; + END + END chanx_left_in[4] + PIN chanx_left_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 23.56 0.595 23.7 ; + END + END chanx_left_in[5] + PIN chanx_left_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 34.44 0.595 34.58 ; + END + END chanx_left_in[6] + PIN chanx_left_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 26.03 0.8 26.33 ; + END + END chanx_left_in[7] + PIN chanx_left_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 22.88 0.595 23.02 ; + END + END chanx_left_in[8] + PIN chanx_left_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 63.34 0.595 63.48 ; + END + END chanx_left_in[9] + PIN chanx_left_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 57.9 0.595 58.04 ; + END + END chanx_left_in[10] + PIN chanx_left_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.3 0.595 44.44 ; + END + END chanx_left_in[11] + PIN chanx_left_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 35.55 0.8 35.85 ; + END + END chanx_left_in[12] + PIN chanx_left_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 42.26 0.595 42.4 ; + END + END chanx_left_in[13] + PIN chanx_left_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 55.18 0.595 55.32 ; + END + END chanx_left_in[14] + PIN chanx_left_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 50.42 0.595 50.56 ; + END + END chanx_left_in[15] + PIN chanx_left_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 61.3 0.595 61.44 ; + END + END chanx_left_in[16] + PIN chanx_left_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.72 0.595 31.86 ; + END + END chanx_left_in[17] + PIN chanx_left_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 47.02 0.595 47.16 ; + END + END chanx_left_in[18] + PIN chanx_left_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 31.47 0.8 31.77 ; + END + END chanx_left_in[19] + PIN chanx_left_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 40.99 0.8 41.29 ; + END + END chanx_left_in[20] + PIN chanx_left_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 34.19 0.8 34.49 ; + END + END chanx_left_in[21] + PIN chanx_left_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 28.32 0.595 28.46 ; + END + END chanx_left_in[22] + PIN chanx_left_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.82 0.595 36.96 ; + END + END chanx_left_in[23] + PIN chanx_left_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 33.76 0.595 33.9 ; + END + END chanx_left_in[24] + PIN chanx_left_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 52.46 0.595 52.6 ; + END + END chanx_left_in[25] + PIN chanx_left_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 58.58 0.595 58.72 ; + END + END chanx_left_in[26] + PIN chanx_left_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 60.62 0.595 60.76 ; + END + END chanx_left_in[27] + PIN chanx_left_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 53.23 0.8 53.53 ; + END + END chanx_left_in[28] + PIN chanx_left_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 36.14 0.595 36.28 ; + END + END chanx_left_in[29] + PIN left_top_grid_pin_1_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 51.87 0.8 52.17 ; + END + END left_top_grid_pin_1_[0] + PIN left_bottom_grid_pin_36_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 12.12 10.88 12.26 11.365 ; + END + END left_bottom_grid_pin_36_[0] + PIN left_bottom_grid_pin_37_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 30.36 8.94 30.955 9.08 ; + END + END left_bottom_grid_pin_37_[0] + PIN left_bottom_grid_pin_38_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 10.28 10.88 10.42 11.365 ; + END + END left_bottom_grid_pin_38_[0] + PIN left_bottom_grid_pin_39_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 30.36 7.24 30.955 7.38 ; + END + END left_bottom_grid_pin_39_[0] + PIN left_bottom_grid_pin_40_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.04 10.88 13.18 11.365 ; + END + END left_bottom_grid_pin_40_[0] + PIN left_bottom_grid_pin_41_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 13.96 10.88 14.1 11.365 ; + END + END left_bottom_grid_pin_41_[0] + PIN left_bottom_grid_pin_42_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 30.36 6.56 30.955 6.7 ; + END + END left_bottom_grid_pin_42_[0] + PIN left_bottom_grid_pin_43_[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 14.88 10.88 15.02 11.365 ; + END + END left_bottom_grid_pin_43_[0] + PIN ccff_head[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 103.365 85.1 103.96 85.24 ; + END + END ccff_head[0] + PIN chany_bottom_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.96 0 37.1 0.485 ; + END + END chany_bottom_out[0] + PIN chany_bottom_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 36.04 0 36.18 0.485 ; + END + END chany_bottom_out[1] + PIN chany_bottom_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.12 0 35.26 0.485 ; + END + END chany_bottom_out[2] + PIN chany_bottom_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 41.1 0 41.24 0.485 ; + END + END chany_bottom_out[3] + PIN chany_bottom_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 51.68 0 51.82 0.485 ; + END + END chany_bottom_out[4] + PIN chany_bottom_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 40.18 0 40.32 0.485 ; + END + END chany_bottom_out[5] + PIN chany_bottom_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 84.34 0 84.48 0.485 ; + END + END chany_bottom_out[6] + PIN chany_bottom_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 50.76 0 50.9 0.485 ; + END + END chany_bottom_out[7] + PIN chany_bottom_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 85.26 0 85.4 0.485 ; + END + END chany_bottom_out[8] + PIN chany_bottom_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 67.78 0 67.92 0.485 ; + END + END chany_bottom_out[9] + PIN chany_bottom_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 78.82 0 78.96 0.485 ; + END + END chany_bottom_out[10] + PIN chany_bottom_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.98 0 77.12 0.485 ; + END + END chany_bottom_out[11] + PIN chany_bottom_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 49.84 0 49.98 0.485 ; + END + END chany_bottom_out[12] + PIN chany_bottom_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 80.66 0 80.8 0.485 ; + END + END chany_bottom_out[13] + PIN chany_bottom_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 82.5 0 82.64 0.485 ; + END + END chany_bottom_out[14] + PIN chany_bottom_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 74.22 0 74.36 0.485 ; + END + END chany_bottom_out[15] + PIN chany_bottom_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 52.6 0 52.74 0.485 ; + END + END chany_bottom_out[16] + PIN chany_bottom_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 76.06 0 76.2 0.485 ; + END + END chany_bottom_out[17] + PIN chany_bottom_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 53.52 0 53.66 0.485 ; + END + END chany_bottom_out[18] + PIN chany_bottom_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 83.42 0 83.56 0.485 ; + END + END chany_bottom_out[19] + PIN chany_bottom_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 65.94 0 66.08 0.485 ; + END + END chany_bottom_out[20] + PIN chany_bottom_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 89.86 0 90 0.485 ; + END + END chany_bottom_out[21] + PIN chany_bottom_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 66.86 0 67 0.485 ; + END + END chany_bottom_out[22] + PIN chany_bottom_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 64.56 0 64.7 0.485 ; + END + END chany_bottom_out[23] + PIN chany_bottom_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 63.64 0 63.78 0.485 ; + END + END chany_bottom_out[24] + PIN chany_bottom_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 48 0 48.14 0.485 ; + END + END chany_bottom_out[25] + PIN chany_bottom_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 79.74 0 79.88 0.485 ; + END + END chany_bottom_out[26] + PIN chany_bottom_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 54.44 0 54.58 0.485 ; + END + END chany_bottom_out[27] + PIN chany_bottom_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 75.14 0 75.28 0.485 ; + END + END chany_bottom_out[28] + PIN chany_bottom_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 94.46 0 94.6 0.485 ; + END + END chany_bottom_out[29] + PIN chanx_left_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 53.48 0.595 53.62 ; + END + END chanx_left_out[0] + PIN chanx_left_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 48.04 0.595 48.18 ; + END + END chanx_left_out[1] + PIN chanx_left_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 56.2 0.595 56.34 ; + END + END chanx_left_out[2] + PIN chanx_left_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 47.79 0.8 48.09 ; + END + END chanx_left_out[3] + PIN chanx_left_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 50.51 0.8 50.81 ; + END + END chanx_left_out[4] + PIN chanx_left_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 49.15 0.8 49.45 ; + END + END chanx_left_out[5] + PIN chanx_left_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 36.91 0.8 37.21 ; + END + END chanx_left_out[6] + PIN chanx_left_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 18.12 0.595 18.26 ; + END + END chanx_left_out[7] + PIN chanx_left_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 30.11 0.8 30.41 ; + END + END chanx_left_out[8] + PIN chanx_left_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 28.75 0.8 29.05 ; + END + END chanx_left_out[9] + PIN chanx_left_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 38.27 0.8 38.57 ; + END + END chanx_left_out[10] + PIN chanx_left_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 32.83 0.8 33.13 ; + END + END chanx_left_out[11] + PIN chanx_left_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 25.6 0.595 25.74 ; + END + END chanx_left_out[12] + PIN chanx_left_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 15.4 0.595 15.54 ; + END + END chanx_left_out[13] + PIN chanx_left_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 46.43 0.8 46.73 ; + END + END chanx_left_out[14] + PIN chanx_left_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 45.07 0.8 45.37 ; + END + END chanx_left_out[15] + PIN chanx_left_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 14.72 0.595 14.86 ; + END + END chanx_left_out[16] + PIN chanx_left_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 26.28 0.595 26.42 ; + END + END chanx_left_out[17] + PIN chanx_left_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 64.02 0.595 64.16 ; + END + END chanx_left_out[18] + PIN chanx_left_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 18.55 0.8 18.85 ; + END + END chanx_left_out[19] + PIN chanx_left_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 41.58 0.595 41.72 ; + END + END chanx_left_out[20] + PIN chanx_left_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 39.54 0.595 39.68 ; + END + END chanx_left_out[21] + PIN chanx_left_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 23.31 0.8 23.61 ; + END + END chanx_left_out[22] + PIN chanx_left_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 31.04 0.595 31.18 ; + END + END chanx_left_out[23] + PIN chanx_left_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 42.35 0.8 42.65 ; + END + END chanx_left_out[24] + PIN chanx_left_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 44.98 0.595 45.12 ; + END + END chanx_left_out[25] + PIN chanx_left_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 39.63 0.8 39.93 ; + END + END chanx_left_out[26] + PIN chanx_left_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 49.74 0.595 49.88 ; + END + END chanx_left_out[27] + PIN chanx_left_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 17.19 0.8 17.49 ; + END + END chanx_left_out[28] + PIN chanx_left_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 29 0.595 29.14 ; + END + END chanx_left_out[29] + PIN ccff_tail[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 21.95 0.8 22.25 ; + END + END ccff_tail[0] + PIN SC_IN_BOT + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 0 19.91 0.8 20.21 ; + END + END SC_IN_BOT + PIN SC_OUT_BOT + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 27.76 10.88 27.9 11.365 ; + END + END SC_OUT_BOT + PIN pReset_W_in + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met1 ; + RECT 0 17.44 0.595 17.58 ; + END + END pReset_W_in + PIN prog_clk_0_S_in + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 42.02 0 42.16 0.485 ; + END + END prog_clk_0_S_in + PIN VDD + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met5 ; + RECT 0 26.96 3.2 30.16 ; + RECT 100.76 26.96 103.96 30.16 ; + RECT 0 67.76 3.2 70.96 ; + RECT 100.76 67.76 103.96 70.96 ; + LAYER met4 ; + RECT 44.78 0 45.38 0.6 ; + RECT 74.22 0 74.82 0.6 ; + RECT 13.5 10.88 14.1 11.48 ; + RECT 13.5 86.44 14.1 87.04 ; + RECT 44.78 86.44 45.38 87.04 ; + RECT 74.22 86.44 74.82 87.04 ; + LAYER met1 ; + RECT 30.36 2.48 30.84 2.96 ; + RECT 103.48 2.48 103.96 2.96 ; + RECT 30.36 7.92 30.84 8.4 ; + RECT 103.48 7.92 103.96 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 103.48 13.36 103.96 13.84 ; + RECT 0 18.8 0.48 19.28 ; + RECT 103.48 18.8 103.96 19.28 ; + RECT 0 24.24 0.48 24.72 ; + RECT 103.48 24.24 103.96 24.72 ; + RECT 0 29.68 0.48 30.16 ; + RECT 103.48 29.68 103.96 30.16 ; + RECT 0 35.12 0.48 35.6 ; + RECT 103.48 35.12 103.96 35.6 ; + RECT 0 40.56 0.48 41.04 ; + RECT 103.48 40.56 103.96 41.04 ; + RECT 0 46 0.48 46.48 ; + RECT 103.48 46 103.96 46.48 ; + RECT 0 51.44 0.48 51.92 ; + RECT 103.48 51.44 103.96 51.92 ; + RECT 0 56.88 0.48 57.36 ; + RECT 103.48 56.88 103.96 57.36 ; + RECT 0 62.32 0.48 62.8 ; + RECT 103.48 62.32 103.96 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 103.48 67.76 103.96 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 103.48 73.2 103.96 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 103.48 78.64 103.96 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 103.48 84.08 103.96 84.56 ; + END + END VDD + PIN VSS + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met5 ; + RECT 0 47.36 3.2 50.56 ; + RECT 100.76 47.36 103.96 50.56 ; + LAYER met4 ; + RECT 59.5 0 60.1 0.6 ; + RECT 88.94 0 89.54 0.6 ; + RECT 59.5 86.44 60.1 87.04 ; + RECT 88.94 86.44 89.54 87.04 ; + LAYER met1 ; + RECT 30.36 -0.24 30.84 0.24 ; + RECT 103.48 -0.24 103.96 0.24 ; + RECT 30.36 5.2 30.84 5.68 ; + RECT 103.48 5.2 103.96 5.68 ; + RECT 0 10.64 0.48 11.12 ; + RECT 103.48 10.64 103.96 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 103.48 16.08 103.96 16.56 ; + RECT 0 21.52 0.48 22 ; + RECT 103.48 21.52 103.96 22 ; + RECT 0 26.96 0.48 27.44 ; + RECT 103.48 26.96 103.96 27.44 ; + RECT 0 32.4 0.48 32.88 ; + RECT 103.48 32.4 103.96 32.88 ; + RECT 0 37.84 0.48 38.32 ; + RECT 103.48 37.84 103.96 38.32 ; + RECT 0 43.28 0.48 43.76 ; + RECT 103.48 43.28 103.96 43.76 ; + RECT 0 48.72 0.48 49.2 ; + RECT 103.48 48.72 103.96 49.2 ; + RECT 0 54.16 0.48 54.64 ; + RECT 103.48 54.16 103.96 54.64 ; + RECT 0 59.6 0.48 60.08 ; + RECT 103.48 59.6 103.96 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 103.48 65.04 103.96 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 103.48 70.48 103.96 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 103.48 75.92 103.96 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 103.48 81.36 103.96 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 103.48 86.8 103.96 87.28 ; + END + END VSS + OBS + LAYER met2 ; + RECT 89.1 86.735 89.38 87.105 ; + RECT 59.66 86.735 59.94 87.105 ; + RECT 51.62 86.03 51.88 86.35 ; + POLYGON 79.42 19.45 79.42 0.24 79.46 0.24 79.46 0.1 79.28 0.1 79.28 19.45 ; + RECT 95.78 0.69 96.04 1.01 ; + RECT 66.34 0.69 66.6 1.01 ; + RECT 71.86 0.35 72.1 0.67 ; + RECT 89.1 -0.065 89.38 0.305 ; + RECT 59.66 -0.065 59.94 0.305 ; + POLYGON 103.68 86.76 103.68 0.28 96.72 0.28 96.72 0.765 96.02 0.765 96.02 0.28 95.8 0.28 95.8 0.765 95.1 0.765 95.1 0.28 94.88 0.28 94.88 0.765 94.18 0.765 94.18 0.28 93.96 0.28 93.96 0.765 93.26 0.765 93.26 0.28 93.04 0.28 93.04 0.765 92.34 0.765 92.34 0.28 92.12 0.28 92.12 0.765 91.42 0.765 91.42 0.28 91.2 0.28 91.2 0.765 90.5 0.765 90.5 0.28 90.28 0.28 90.28 0.765 89.58 0.765 89.58 0.28 88.44 0.28 88.44 0.765 87.74 0.765 87.74 0.28 87.52 0.28 87.52 0.765 86.82 0.765 86.82 0.28 86.6 0.28 86.6 0.765 85.9 0.765 85.9 0.28 85.68 0.28 85.68 0.765 84.98 0.765 84.98 0.28 84.76 0.28 84.76 0.765 84.06 0.765 84.06 0.28 83.84 0.28 83.84 0.765 83.14 0.765 83.14 0.28 82.92 0.28 82.92 0.765 82.22 0.765 82.22 0.28 82 0.28 82 0.765 81.3 0.765 81.3 0.28 81.08 0.28 81.08 0.765 80.38 0.765 80.38 0.28 80.16 0.28 80.16 0.765 79.46 0.765 79.46 0.28 79.24 0.28 79.24 0.765 78.54 0.765 78.54 0.28 78.32 0.28 78.32 0.765 77.62 0.765 77.62 0.28 77.4 0.28 77.4 0.765 76.7 0.765 76.7 0.28 76.48 0.28 76.48 0.765 75.78 0.765 75.78 0.28 75.56 0.28 75.56 0.765 74.86 0.765 74.86 0.28 74.64 0.28 74.64 0.765 73.94 0.765 73.94 0.28 73.72 0.28 73.72 0.765 73.02 0.765 73.02 0.28 72.8 0.28 72.8 0.765 72.1 0.765 72.1 0.28 71.88 0.28 71.88 0.765 71.18 0.765 71.18 0.28 70.96 0.28 70.96 0.765 70.26 0.765 70.26 0.28 70.04 0.28 70.04 0.765 69.34 0.765 69.34 0.28 69.12 0.28 69.12 0.765 68.42 0.765 68.42 0.28 68.2 0.28 68.2 0.765 67.5 0.765 67.5 0.28 67.28 0.28 67.28 0.765 66.58 0.765 66.58 0.28 66.36 0.28 66.36 0.765 65.66 0.765 65.66 0.28 64.98 0.28 64.98 0.765 64.28 0.765 64.28 0.28 64.06 0.28 64.06 0.765 63.36 0.765 63.36 0.28 63.14 0.28 63.14 0.765 62.44 0.765 62.44 0.28 61.76 0.28 61.76 0.765 61.06 0.765 61.06 0.28 60.84 0.28 60.84 0.765 60.14 0.765 60.14 0.28 59 0.28 59 0.765 58.3 0.765 58.3 0.28 58.08 0.28 58.08 0.765 57.38 0.765 57.38 0.28 56.7 0.28 56.7 0.765 56 0.765 56 0.28 55.78 0.28 55.78 0.765 55.08 0.765 55.08 0.28 54.86 0.28 54.86 0.765 54.16 0.765 54.16 0.28 53.94 0.28 53.94 0.765 53.24 0.765 53.24 0.28 53.02 0.28 53.02 0.765 52.32 0.765 52.32 0.28 52.1 0.28 52.1 0.765 51.4 0.765 51.4 0.28 51.18 0.28 51.18 0.765 50.48 0.765 50.48 0.28 50.26 0.28 50.26 0.765 49.56 0.765 49.56 0.28 49.34 0.28 49.34 0.765 48.64 0.765 48.64 0.28 48.42 0.28 48.42 0.765 47.72 0.765 47.72 0.28 47.5 0.28 47.5 0.765 46.8 0.765 46.8 0.28 46.58 0.28 46.58 0.765 45.88 0.765 45.88 0.28 45.66 0.28 45.66 0.765 44.96 0.765 44.96 0.28 42.44 0.28 42.44 0.765 41.74 0.765 41.74 0.28 41.52 0.28 41.52 0.765 40.82 0.765 40.82 0.28 40.6 0.28 40.6 0.765 39.9 0.765 39.9 0.28 37.38 0.28 37.38 0.765 36.68 0.765 36.68 0.28 36.46 0.28 36.46 0.765 35.76 0.765 35.76 0.28 35.54 0.28 35.54 0.765 34.84 0.765 34.84 0.28 30.64 0.28 30.64 11.16 28.18 11.16 28.18 11.645 27.48 11.645 27.48 11.16 20.36 11.16 20.36 11.645 19.66 11.645 19.66 11.16 19.44 11.16 19.44 11.645 18.74 11.645 18.74 11.16 18.52 11.16 18.52 11.645 17.82 11.645 17.82 11.16 17.14 11.16 17.14 11.645 16.44 11.645 16.44 11.16 16.22 11.16 16.22 11.645 15.52 11.645 15.52 11.16 15.3 11.16 15.3 11.645 14.6 11.645 14.6 11.16 14.38 11.16 14.38 11.645 13.68 11.645 13.68 11.16 13.46 11.16 13.46 11.645 12.76 11.645 12.76 11.16 12.54 11.16 12.54 11.645 11.84 11.645 11.84 11.16 11.62 11.16 11.62 11.645 10.92 11.645 10.92 11.16 10.7 11.16 10.7 11.645 10 11.645 10 11.16 8.86 11.16 8.86 11.645 8.16 11.645 8.16 11.16 4.26 11.16 4.26 11.645 3.56 11.645 3.56 11.16 0.28 11.16 0.28 86.76 51.86 86.76 51.86 86.275 52.56 86.275 52.56 86.76 ; + LAYER met4 ; + POLYGON 79.73 60.33 79.73 0.505 79.745 0.505 79.745 0.175 79.415 0.175 79.415 0.505 79.43 0.505 79.43 60.33 ; + POLYGON 30.97 13.41 30.97 1.17 31.89 1.17 31.89 0.87 30.67 0.87 30.67 13.41 ; + POLYGON 103.56 86.64 103.56 0.4 89.94 0.4 89.94 1 88.54 1 88.54 0.4 75.22 0.4 75.22 1 73.82 1 73.82 0.4 65.41 0.4 65.41 1.2 64.31 1.2 64.31 0.4 63.57 0.4 63.57 1.2 62.47 1.2 62.47 0.4 61.73 0.4 61.73 1.2 60.63 1.2 60.63 0.4 60.5 0.4 60.5 1 59.1 1 59.1 0.4 45.78 0.4 45.78 1 44.38 1 44.38 0.4 30.76 0.4 30.76 11.28 14.5 11.28 14.5 11.88 13.1 11.88 13.1 11.28 0.4 11.28 0.4 86.64 13.1 86.64 13.1 86.04 14.5 86.04 14.5 86.64 44.38 86.64 44.38 86.04 45.78 86.04 45.78 86.64 59.1 86.64 59.1 86.04 60.5 86.04 60.5 86.64 73.82 86.64 73.82 86.04 75.22 86.04 75.22 86.64 88.54 86.64 88.54 86.04 89.94 86.04 89.94 86.64 ; + LAYER met1 ; + POLYGON 103.2 87.28 103.2 86.8 89.4 86.8 89.4 86.79 89.08 86.79 89.08 86.8 59.96 86.8 59.96 86.79 59.64 86.79 59.64 86.8 0.76 86.8 0.76 87.28 ; + RECT 0.76 10.64 71.16 11.12 ; + POLYGON 89.4 0.25 89.4 0.24 103.2 0.24 103.2 -0.24 31.12 -0.24 31.12 0.24 59.64 0.24 59.64 0.25 59.96 0.25 59.96 0.24 89.08 0.24 89.08 0.25 ; + POLYGON 103.2 86.76 103.2 86.52 103.68 86.52 103.68 85.52 103.085 85.52 103.085 84.82 103.2 84.82 103.2 83.8 103.68 83.8 103.68 82.12 103.2 82.12 103.2 81.08 103.68 81.08 103.68 79.4 103.2 79.4 103.2 78.36 103.68 78.36 103.68 76.68 103.2 76.68 103.2 75.64 103.68 75.64 103.68 73.96 103.2 73.96 103.2 72.92 103.68 72.92 103.68 71.24 103.2 71.24 103.2 70.2 103.68 70.2 103.68 68.52 103.2 68.52 103.2 67.48 103.68 67.48 103.68 65.8 103.2 65.8 103.2 64.76 103.68 64.76 103.68 63.08 103.2 63.08 103.2 62.04 103.68 62.04 103.68 60.36 103.2 60.36 103.2 59.32 103.68 59.32 103.68 57.64 103.2 57.64 103.2 56.6 103.68 56.6 103.68 54.92 103.2 54.92 103.2 53.88 103.68 53.88 103.68 52.2 103.2 52.2 103.2 51.16 103.68 51.16 103.68 49.48 103.2 49.48 103.2 48.44 103.68 48.44 103.68 46.76 103.2 46.76 103.2 45.72 103.68 45.72 103.68 44.04 103.2 44.04 103.2 43 103.68 43 103.68 41.32 103.2 41.32 103.2 40.28 103.68 40.28 103.68 38.6 103.2 38.6 103.2 37.56 103.68 37.56 103.68 35.88 103.2 35.88 103.2 34.84 103.68 34.84 103.68 33.16 103.2 33.16 103.2 32.12 103.68 32.12 103.68 30.44 103.2 30.44 103.2 29.4 103.68 29.4 103.68 27.72 103.2 27.72 103.2 26.68 103.68 26.68 103.68 25 103.2 25 103.2 23.96 103.68 23.96 103.68 22.28 103.2 22.28 103.2 21.24 103.68 21.24 103.68 19.56 103.2 19.56 103.2 18.52 103.68 18.52 103.68 16.84 103.2 16.84 103.2 15.8 103.68 15.8 103.68 14.12 103.2 14.12 103.2 13.08 103.68 13.08 103.68 11.4 103.2 11.4 103.2 10.36 103.68 10.36 103.68 8.68 103.2 8.68 103.2 7.64 103.68 7.64 103.68 5.96 103.2 5.96 103.2 4.92 103.68 4.92 103.68 3.24 103.2 3.24 103.2 2.2 103.68 2.2 103.68 0.52 103.2 0.52 103.2 0.28 31.12 0.28 31.12 0.52 30.64 0.52 30.64 2.2 31.12 2.2 31.12 3.24 30.64 3.24 30.64 4.92 31.12 4.92 31.12 5.96 30.64 5.96 30.64 6.28 31.235 6.28 31.235 7.66 31.12 7.66 31.12 8.66 31.235 8.66 31.235 9.36 30.64 9.36 30.64 11.16 0.76 11.16 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 14.44 0.875 14.44 0.875 15.82 0.76 15.82 0.76 16.84 0.28 16.84 0.28 17.16 0.875 17.16 0.875 18.54 0.76 18.54 0.76 19.56 0.28 19.56 0.28 20.56 0.875 20.56 0.875 21.26 0.76 21.26 0.76 22.28 0.28 22.28 0.28 22.6 0.875 22.6 0.875 23.98 0.76 23.98 0.76 25 0.28 25 0.28 25.32 0.875 25.32 0.875 26.7 0.76 26.7 0.76 27.72 0.28 27.72 0.28 28.04 0.875 28.04 0.875 29.42 0.76 29.42 0.76 30.44 0.28 30.44 0.28 30.76 0.875 30.76 0.875 32.14 0.76 32.14 0.76 33.16 0.28 33.16 0.28 33.48 0.875 33.48 0.875 34.86 0.76 34.86 0.76 35.86 0.875 35.86 0.875 37.24 0.28 37.24 0.28 37.56 0.76 37.56 0.76 38.58 0.875 38.58 0.875 39.96 0.28 39.96 0.28 40.28 0.76 40.28 0.76 41.3 0.875 41.3 0.875 42.68 0.28 42.68 0.28 43 0.76 43 0.76 44.02 0.875 44.02 0.875 45.4 0.28 45.4 0.28 45.72 0.76 45.72 0.76 46.74 0.875 46.74 0.875 47.44 0.28 47.44 0.28 47.76 0.875 47.76 0.875 48.46 0.76 48.46 0.76 49.46 0.875 49.46 0.875 50.84 0.28 50.84 0.28 51.16 0.76 51.16 0.76 52.18 0.875 52.18 0.875 52.88 0.28 52.88 0.28 53.2 0.875 53.2 0.875 53.9 0.76 53.9 0.76 54.9 0.875 54.9 0.875 55.6 0.28 55.6 0.28 55.92 0.875 55.92 0.875 56.62 0.76 56.62 0.76 57.62 0.875 57.62 0.875 59 0.28 59 0.28 59.32 0.76 59.32 0.76 60.34 0.875 60.34 0.875 61.72 0.28 61.72 0.28 62.04 0.76 62.04 0.76 63.06 0.875 63.06 0.875 64.44 0.28 64.44 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 86.76 ; + LAYER met3 ; + POLYGON 89.405 87.085 89.405 87.08 89.62 87.08 89.62 86.76 89.405 86.76 89.405 86.755 89.075 86.755 89.075 86.76 88.86 86.76 88.86 87.08 89.075 87.08 89.075 87.085 ; + POLYGON 59.965 87.085 59.965 87.08 60.18 87.08 60.18 86.76 59.965 86.76 59.965 86.755 59.635 86.755 59.635 86.76 59.42 86.76 59.42 87.08 59.635 87.08 59.635 87.085 ; + POLYGON 1.315 21.585 1.315 21.57 2.45 21.57 2.45 21.27 1.315 21.27 1.315 21.255 0.985 21.255 0.985 21.585 ; + POLYGON 14.195 11.385 14.195 11.37 43.62 11.37 43.62 11.07 14.195 11.07 14.195 11.055 13.865 11.055 13.865 11.385 ; + POLYGON 69.855 0.505 69.855 0.49 79.39 0.49 79.39 0.5 79.77 0.5 79.77 0.18 79.39 0.18 79.39 0.19 69.855 0.19 69.855 0.175 69.525 0.175 69.525 0.505 ; + POLYGON 89.405 0.285 89.405 0.28 89.62 0.28 89.62 -0.04 89.405 -0.04 89.405 -0.045 89.075 -0.045 89.075 -0.04 88.86 -0.04 88.86 0.28 89.075 0.28 89.075 0.285 ; + POLYGON 59.965 0.285 59.965 0.28 60.18 0.28 60.18 -0.04 59.965 -0.04 59.965 -0.045 59.635 -0.045 59.635 -0.04 59.42 -0.04 59.42 0.28 59.635 0.28 59.635 0.285 ; + POLYGON 103.56 86.64 103.56 0.4 30.76 0.4 30.76 11.28 0.4 11.28 0.4 16.79 1.2 16.79 1.2 17.89 0.4 17.89 0.4 18.15 1.2 18.15 1.2 19.25 0.4 19.25 0.4 19.51 1.2 19.51 1.2 20.61 0.4 20.61 0.4 21.55 1.2 21.55 1.2 22.65 0.4 22.65 0.4 22.91 1.2 22.91 1.2 24.01 0.4 24.01 0.4 24.27 1.2 24.27 1.2 25.37 0.4 25.37 0.4 25.63 1.2 25.63 1.2 26.73 0.4 26.73 0.4 26.99 1.2 26.99 1.2 28.09 0.4 28.09 0.4 28.35 1.2 28.35 1.2 29.45 0.4 29.45 0.4 29.71 1.2 29.71 1.2 30.81 0.4 30.81 0.4 31.07 1.2 31.07 1.2 32.17 0.4 32.17 0.4 32.43 1.2 32.43 1.2 33.53 0.4 33.53 0.4 33.79 1.2 33.79 1.2 34.89 0.4 34.89 0.4 35.15 1.2 35.15 1.2 36.25 0.4 36.25 0.4 36.51 1.2 36.51 1.2 37.61 0.4 37.61 0.4 37.87 1.2 37.87 1.2 38.97 0.4 38.97 0.4 39.23 1.2 39.23 1.2 40.33 0.4 40.33 0.4 40.59 1.2 40.59 1.2 41.69 0.4 41.69 0.4 41.95 1.2 41.95 1.2 43.05 0.4 43.05 0.4 43.31 1.2 43.31 1.2 44.41 0.4 44.41 0.4 44.67 1.2 44.67 1.2 45.77 0.4 45.77 0.4 46.03 1.2 46.03 1.2 47.13 0.4 47.13 0.4 47.39 1.2 47.39 1.2 48.49 0.4 48.49 0.4 48.75 1.2 48.75 1.2 49.85 0.4 49.85 0.4 50.11 1.2 50.11 1.2 51.21 0.4 51.21 0.4 51.47 1.2 51.47 1.2 52.57 0.4 52.57 0.4 52.83 1.2 52.83 1.2 53.93 0.4 53.93 0.4 86.64 ; + LAYER met5 ; + POLYGON 102.36 85.44 102.36 72.56 99.16 72.56 99.16 66.16 102.36 66.16 102.36 52.16 99.16 52.16 99.16 45.76 102.36 45.76 102.36 31.76 99.16 31.76 99.16 25.36 102.36 25.36 102.36 1.6 31.96 1.6 31.96 12.48 1.6 12.48 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 85.44 ; + LAYER li1 ; + POLYGON 103.96 87.125 103.96 86.955 100.56 86.955 100.56 86.495 100.235 86.495 100.235 86.955 98.445 86.955 98.445 86.495 98.175 86.495 98.175 86.955 97.435 86.955 97.435 86.23 97.145 86.23 97.145 86.955 96.42 86.955 96.42 86.495 96.095 86.495 96.095 86.955 94.305 86.955 94.305 86.495 94.035 86.495 94.035 86.955 91.485 86.955 91.485 86.495 91.18 86.495 91.18 86.955 89.695 86.955 89.695 86.515 89.505 86.515 89.505 86.955 87.605 86.955 87.605 86.495 87.275 86.495 87.275 86.955 84.675 86.955 84.675 86.595 84.345 86.595 84.345 86.955 83.645 86.955 83.645 86.575 83.315 86.575 83.315 86.955 82.255 86.955 82.255 86.23 81.965 86.23 81.965 86.955 81.24 86.955 81.24 86.495 80.915 86.495 80.915 86.955 79.125 86.955 79.125 86.495 78.855 86.495 78.855 86.955 76.305 86.955 76.305 86.495 76 86.495 76 86.955 74.515 86.955 74.515 86.515 74.325 86.515 74.325 86.955 72.425 86.955 72.425 86.495 72.095 86.495 72.095 86.955 69.495 86.955 69.495 86.595 69.165 86.595 69.165 86.955 68.465 86.955 68.465 86.575 68.135 86.575 68.135 86.955 67.535 86.955 67.535 86.23 67.245 86.23 67.245 86.955 65.725 86.955 65.725 86.495 65.42 86.495 65.42 86.955 63.935 86.955 63.935 86.515 63.745 86.515 63.745 86.955 61.845 86.955 61.845 86.495 61.515 86.495 61.515 86.955 58.915 86.955 58.915 86.595 58.585 86.595 58.585 86.955 57.885 86.955 57.885 86.575 57.555 86.575 57.555 86.955 52.355 86.955 52.355 86.23 52.065 86.23 52.065 86.955 46.405 86.955 46.405 86.495 46.1 86.495 46.1 86.955 44.615 86.955 44.615 86.515 44.425 86.515 44.425 86.955 42.525 86.955 42.525 86.495 42.195 86.495 42.195 86.955 39.595 86.955 39.595 86.595 39.265 86.595 39.265 86.955 38.565 86.955 38.565 86.575 38.235 86.575 38.235 86.955 37.635 86.955 37.635 86.23 37.345 86.23 37.345 86.955 34.435 86.955 34.435 86.575 34.105 86.575 34.105 86.955 32.145 86.955 32.145 86.495 31.84 86.495 31.84 86.955 30.355 86.955 30.355 86.515 30.165 86.515 30.165 86.955 28.265 86.955 28.265 86.495 27.935 86.495 27.935 86.955 25.335 86.955 25.335 86.595 25.005 86.595 25.005 86.955 24.305 86.955 24.305 86.575 23.975 86.575 23.975 86.955 22.455 86.955 22.455 86.23 22.165 86.23 22.165 86.955 21.565 86.955 21.565 86.495 21.26 86.495 21.26 86.955 19.775 86.955 19.775 86.515 19.585 86.515 19.585 86.955 17.685 86.955 17.685 86.495 17.355 86.495 17.355 86.955 14.755 86.955 14.755 86.595 14.425 86.595 14.425 86.955 13.725 86.955 13.725 86.575 13.395 86.575 13.395 86.955 10.515 86.955 10.515 86.575 10.185 86.575 10.185 86.955 7.735 86.955 7.735 86.23 7.445 86.23 7.445 86.955 0 86.955 0 87.125 ; + RECT 103.04 84.235 103.96 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 103.04 81.515 103.96 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 103.04 78.795 103.96 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 103.04 76.075 103.96 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 103.04 73.355 103.96 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 103.04 70.635 103.96 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 103.04 67.915 103.96 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 103.04 65.195 103.96 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 103.04 62.475 103.96 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 103.04 59.755 103.96 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 103.04 57.035 103.96 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 103.04 54.315 103.96 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 103.04 51.595 103.96 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 103.04 48.875 103.96 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 103.04 46.155 103.96 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 103.04 43.435 103.96 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 100.28 40.715 103.96 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 100.28 37.995 103.96 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 103.04 35.275 103.96 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 103.04 32.555 103.96 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 103.04 29.835 103.96 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 103.04 27.115 103.96 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 103.04 24.395 103.96 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 103.04 21.675 103.96 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 103.04 18.955 103.96 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 103.04 16.235 103.96 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 103.04 13.515 103.96 13.685 ; + RECT 0 13.515 3.68 13.685 ; + POLYGON 28.61 11.785 28.61 10.965 34.04 10.965 34.04 10.795 0 10.795 0 10.965 7.445 10.965 7.445 11.69 7.735 11.69 7.735 10.965 10.095 10.965 10.095 11.445 10.265 11.445 10.265 10.965 10.935 10.965 10.935 11.445 11.105 11.445 11.105 10.965 11.695 10.965 11.695 11.445 12.025 11.445 12.025 10.965 12.535 10.965 12.535 11.445 12.865 11.445 12.865 10.965 13.375 10.965 13.375 11.765 13.705 11.765 13.705 10.965 16.355 10.965 16.355 11.425 16.61 11.425 16.61 10.965 17.28 10.965 17.28 11.425 17.45 11.425 17.45 10.965 18.12 10.965 18.12 11.425 18.29 11.425 18.29 10.965 18.96 10.965 18.96 11.425 19.13 11.425 19.13 10.965 19.8 10.965 19.8 11.425 20.105 11.425 20.105 10.965 21.02 10.965 21.02 11.785 21.25 11.785 21.25 10.965 22.165 10.965 22.165 11.69 22.455 11.69 22.455 10.965 23.365 10.965 23.365 11.5 23.875 11.5 23.875 10.965 25.835 10.965 25.835 11.365 26.165 11.365 26.165 10.965 27 10.965 27 11.785 27.23 11.785 27.23 10.965 28.38 10.965 28.38 11.785 ; + RECT 103.04 10.795 103.96 10.965 ; + RECT 103.04 8.075 103.96 8.245 ; + RECT 30.36 8.075 34.04 8.245 ; + RECT 103.04 5.355 103.96 5.525 ; + RECT 30.36 5.355 34.04 5.525 ; + RECT 103.04 2.635 103.96 2.805 ; + RECT 30.36 2.635 34.04 2.805 ; + POLYGON 90.065 0.885 90.065 0.085 92.975 0.085 92.975 0.485 93.305 0.485 93.305 0.085 95.265 0.085 95.265 0.62 95.775 0.62 95.775 0.085 97.145 0.085 97.145 0.81 97.435 0.81 97.435 0.085 103.96 0.085 103.96 -0.085 30.36 -0.085 30.36 0.085 33.255 0.085 33.255 0.545 33.56 0.545 33.56 0.085 34.23 0.085 34.23 0.545 34.4 0.545 34.4 0.085 35.07 0.085 35.07 0.545 35.24 0.545 35.24 0.085 35.91 0.085 35.91 0.545 36.08 0.545 36.08 0.085 36.75 0.085 36.75 0.545 37.005 0.545 37.005 0.085 37.345 0.085 37.345 0.81 37.635 0.81 37.635 0.085 39.995 0.085 39.995 0.565 40.165 0.565 40.165 0.085 40.835 0.085 40.835 0.565 41.005 0.565 41.005 0.085 41.595 0.085 41.595 0.565 41.925 0.565 41.925 0.085 42.435 0.085 42.435 0.565 42.765 0.565 42.765 0.085 43.275 0.085 43.275 0.885 43.605 0.885 43.605 0.085 46.895 0.085 46.895 0.565 47.065 0.565 47.065 0.085 47.735 0.085 47.735 0.565 47.905 0.565 47.905 0.085 48.495 0.085 48.495 0.565 48.825 0.565 48.825 0.085 49.335 0.085 49.335 0.565 49.665 0.565 49.665 0.085 50.175 0.085 50.175 0.885 50.505 0.885 50.505 0.085 52.065 0.085 52.065 0.81 52.355 0.81 52.355 0.085 52.575 0.085 52.575 0.545 52.88 0.545 52.88 0.085 53.55 0.085 53.55 0.545 53.72 0.545 53.72 0.085 54.39 0.085 54.39 0.545 54.56 0.545 54.56 0.085 55.23 0.085 55.23 0.545 55.4 0.545 55.4 0.085 56.07 0.085 56.07 0.545 56.325 0.545 56.325 0.085 57.015 0.085 57.015 0.565 57.185 0.565 57.185 0.085 57.855 0.085 57.855 0.565 58.025 0.565 58.025 0.085 58.615 0.085 58.615 0.565 58.945 0.565 58.945 0.085 59.455 0.085 59.455 0.565 59.785 0.565 59.785 0.085 60.295 0.085 60.295 0.885 60.625 0.885 60.625 0.085 62.235 0.085 62.235 0.545 62.54 0.545 62.54 0.085 63.21 0.085 63.21 0.545 63.38 0.545 63.38 0.085 64.05 0.085 64.05 0.545 64.22 0.545 64.22 0.085 64.89 0.085 64.89 0.545 65.06 0.545 65.06 0.085 65.73 0.085 65.73 0.545 65.985 0.545 65.985 0.085 67.245 0.085 67.245 0.81 67.535 0.81 67.535 0.085 68.905 0.085 68.905 0.62 69.415 0.62 69.415 0.085 71.375 0.085 71.375 0.485 71.705 0.485 71.705 0.085 72.475 0.085 72.475 0.545 72.73 0.545 72.73 0.085 73.4 0.085 73.4 0.545 73.57 0.545 73.57 0.085 74.24 0.085 74.24 0.545 74.41 0.545 74.41 0.085 75.08 0.085 75.08 0.545 75.25 0.545 75.25 0.085 75.92 0.085 75.92 0.545 76.225 0.545 76.225 0.085 76.795 0.085 76.795 0.565 76.965 0.565 76.965 0.085 77.635 0.085 77.635 0.565 77.805 0.565 77.805 0.085 78.395 0.085 78.395 0.565 78.725 0.565 78.725 0.085 79.235 0.085 79.235 0.565 79.565 0.565 79.565 0.085 80.075 0.085 80.075 0.885 80.405 0.885 80.405 0.085 81.965 0.085 81.965 0.81 82.255 0.81 82.255 0.085 86.455 0.085 86.455 0.565 86.625 0.565 86.625 0.085 87.295 0.085 87.295 0.565 87.465 0.565 87.465 0.085 88.055 0.085 88.055 0.565 88.385 0.565 88.385 0.085 88.895 0.085 88.895 0.565 89.225 0.565 89.225 0.085 89.735 0.085 89.735 0.885 ; + POLYGON 103.79 86.87 103.79 0.17 30.53 0.17 30.53 11.05 0.17 11.05 0.17 86.87 ; + LAYER via ; + RECT 89.165 86.845 89.315 86.995 ; + RECT 59.725 86.845 59.875 86.995 ; + RECT 82.495 0.435 82.645 0.585 ; + RECT 50.755 0.435 50.905 0.585 ; + RECT 41.095 0.435 41.245 0.585 ; + RECT 89.165 0.045 89.315 0.195 ; + RECT 59.725 0.045 59.875 0.195 ; + LAYER via2 ; + RECT 89.14 86.82 89.34 87.02 ; + RECT 59.7 86.82 59.9 87.02 ; + RECT 1.05 39.68 1.25 39.88 ; + RECT 1.05 34.24 1.25 34.44 ; + RECT 13.93 11.12 14.13 11.32 ; + RECT 69.59 0.24 69.79 0.44 ; + RECT 89.14 0.02 89.34 0.22 ; + RECT 59.7 0.02 59.9 0.22 ; + LAYER via3 ; + RECT 89.14 86.82 89.34 87.02 ; + RECT 59.7 86.82 59.9 87.02 ; + RECT 79.48 0.24 79.68 0.44 ; + RECT 89.14 0.02 89.34 0.22 ; + RECT 59.7 0.02 59.9 0.22 ; + LAYER OVERLAP ; + POLYGON 30.36 0 30.36 10.88 0 10.88 0 87.04 103.96 87.04 103.96 0 ; + END +END sb_2__2_ + +END LIBRARY diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..489f54e --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c8ec3a5cf25c0ea22bb23cc8df16625bdab0eef21c9250eb5f1c74d5bd3afe25 +size 1265917 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..21f25b8 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:efb93b8618059e2a2e8a3f9d7c2003370283fa51e9e604a8d81102dadd4cc0e3 +size 1676070 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..21a68ad --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:001b933788da040261f9f1908479f05adad26a2fa4c6bb6805ba58b94ff02c00 +size 1580368 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..675f556 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c92223f6897b8d3db40b28a917374a7742a83dedd1b99ef1f87addd792f776b0 +size 344148 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/cby_1__1__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cby_1__1__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..b0b30fa --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cby_1__1__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:17cbf71133a6ceb0b758ed064f283209e8e7b71ad2f07bafd3502176d8e45222 +size 1434351 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/cby_2__1__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cby_2__1__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..405dee7 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cby_2__1__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:41b1d6784a11ee2970b29c21da3faf68d9baf0da5ddba6bb5226a5ea4931dda6 +size 1669821 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_0__0__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_0__0__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..c97a018 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_0__0__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:65ddfa40d1514718b308e1ad0910952103af8f3cea33404c24fa2397a77b6e51 +size 1039540 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_0__1__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_0__1__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..ec4f3dc --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_0__1__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:14c6acf0e1501bf5b13e3e0ce4459f5583658fcb72349cd303f8ca6f30149eba +size 2043874 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_0__2__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_0__2__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..ee943ad --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_0__2__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:4651390147388e9c8b873c0e8b67d92b83e5a9b1e5c404694ebd162b2d104e66 +size 1091271 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_1__0__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_1__0__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..5a8d517 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_1__0__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:4dc2fd0ff3be8829d300a8b1eee36571aecf5213fb47d54757c84f85db99e07c +size 2296653 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_1__1__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_1__1__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..5a2e8e4 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_1__1__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:712b5eb08fd9ee97526816b65c1bccc697c188d5e955b91a3f3de48e3343cba6 +size 3857761 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_1__2__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_1__2__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..99a864c --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_1__2__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9ee327abd168f261fc10f163f9a70c3f0c93902e5ced4d294dc679e508c51b22 +size 2325280 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_2__0__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_2__0__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..973d06f --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_2__0__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1e56a58548f37b4260d8b403193f2e13d093a33b46b2b0589b712b54913f026f +size 1518053 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_2__1__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_2__1__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..54c5605 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_2__1__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6e78b9fd1d87abfef4e49ca64d674fe4cc60986f78d715dbb7fd49076ce8847b +size 2292634 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_2__2__icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_2__2__icv_in_design.nominal_25.spef new file mode 100644 index 0000000..d9b3a3a --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/spef/sb_2__2__icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f56ad0635629e245cc8014915422732556887d071703d625fa589a01272c7ce7 +size 1610201 diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v new file mode 100644 index 0000000..f509f52 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v @@ -0,0 +1,2166 @@ +// +// +// +// +// +// +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_113 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_113 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_110 ) , + .X ( copt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_111 ) , + .X ( copt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_113 ) , + .X ( copt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_109 ) , + .X ( mem_out[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_898_f_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input ZBUF_898_f_0 ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_898_f_0 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_898_f_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input ZBUF_898_f_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .ZBUF_898_f_0 ( ZBUF_898_f_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , ZBUF_898_f_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input ZBUF_898_f_0 ; + +cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .ZBUF_898_f_0 ( ZBUF_898_f_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_208_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input ZBUF_208_0 ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_208_0 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( ZBUF_208_0 ) , .Z ( SOC_OUT ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_7 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_208_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input ZBUF_208_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_7 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .ZBUF_208_0 ( ZBUF_208_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__7 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , ZBUF_208_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input ZBUF_208_0 ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .ZBUF_208_0 ( ZBUF_208_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_96 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( net_net_96 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_6 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_6 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__6 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_217_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input ZBUF_217_0 ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_217_0 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( ZBUF_217_0 ) , .Z ( SOC_OUT ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_5 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_217_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input ZBUF_217_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_5 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .ZBUF_217_0 ( ZBUF_217_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__5 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , ZBUF_217_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input ZBUF_217_0 ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .ZBUF_217_0 ( ZBUF_217_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_95 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( net_net_95 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_4 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__4 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_93 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_93 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_94 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_3 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__3 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_91 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( net_net_91 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_90 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_1 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__1 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_89 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_0 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__0 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_123 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( ccff_head[0] ) , + .X ( copt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_116 ) , + .X ( copt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_114 ) , + .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1358 ( .A ( copt_net_115 ) , + .X ( copt_net_117 ) ) ; +sky130_fd_sc_hd__bufbuf_16 copt_h_inst_1359 ( .A ( ropt_net_124 ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_117 ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_118 ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_119 ) , + .X ( ropt_net_124 ) ) ; +endmodule + + +module cbx_1__0__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_102 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0__const1_7 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__const1_6 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__const1_5 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__const1_4 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module cbx_1__0__const1_3 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__const1_2 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0__const1_0 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , + bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ , + bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ , + top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ , + top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower , + top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower , + top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower , + top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower , + top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , + top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , + top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower , + top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower , + top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower , + SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , pReset_E_in , + pReset_W_in , pReset_W_out , pReset_E_out , prog_clk_0_N_in , + prog_clk_0_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_16_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +input [0:0] top_width_0_height_0__pin_12_ ; +input [0:0] top_width_0_height_0__pin_14_ ; +input [0:0] top_width_0_height_0__pin_16_ ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] top_width_0_height_0__pin_3_upper ; +output [0:0] top_width_0_height_0__pin_3_lower ; +output [0:0] top_width_0_height_0__pin_5_upper ; +output [0:0] top_width_0_height_0__pin_5_lower ; +output [0:0] top_width_0_height_0__pin_7_upper ; +output [0:0] top_width_0_height_0__pin_7_lower ; +output [0:0] top_width_0_height_0__pin_9_upper ; +output [0:0] top_width_0_height_0__pin_9_lower ; +output [0:0] top_width_0_height_0__pin_11_upper ; +output [0:0] top_width_0_height_0__pin_11_lower ; +output [0:0] top_width_0_height_0__pin_13_upper ; +output [0:0] top_width_0_height_0__pin_13_lower ; +output [0:0] top_width_0_height_0__pin_15_upper ; +output [0:0] top_width_0_height_0__pin_15_lower ; +output [0:0] top_width_0_height_0__pin_17_upper ; +output [0:0] top_width_0_height_0__pin_17_lower ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_E_out ; +input prog_clk_0_N_in ; +output prog_clk_0_W_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__7_ccff_tail ; + +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; + +cbx_1__0__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_1 mux_top_ipin_1 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_2 mux_top_ipin_2 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_3 mux_top_ipin_3 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_4 mux_top_ipin_4 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_5 mux_top_ipin_5 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_6 mux_top_ipin_6 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_7 mux_top_ipin_7 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12 mux_top_ipin_8 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( top_width_0_height_0__pin_1_lower ) , + .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_3_lower ) , + .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_5_lower ) , + .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_7_lower ) , + .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_9_lower ) , + .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_506_ } ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_11_lower ) , + .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) , + .ZBUF_217_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ; +cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , + .io_outpad ( top_width_0_height_0__pin_12_ ) , + .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_13_lower ) , + .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_507_ } ) , + .io_outpad ( top_width_0_height_0__pin_14_ ) , + .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_15_lower ) , + .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) , + .ZBUF_208_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ; +cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_508_ } ) , + .io_outpad ( top_width_0_height_0__pin_16_ ) , + .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_17_lower ) , + .ccff_tail ( ccff_tail ) , + .ZBUF_898_f_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( aps_rename_509_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , + .X ( ctsbuf_net_1106 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( top_width_0_height_0__pin_1_lower[0] ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( + .A ( top_width_0_height_0__pin_3_lower[0] ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( + .A ( top_width_0_height_0__pin_5_lower[0] ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_82__81 ( + .A ( top_width_0_height_0__pin_7_lower[0] ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_83__82 ( + .A ( top_width_0_height_0__pin_9_lower[0] ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_84__83 ( + .A ( top_width_0_height_0__pin_11_lower[0] ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_85__84 ( + .A ( top_width_0_height_0__pin_13_lower[0] ) , + .X ( top_width_0_height_0__pin_13_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_86__85 ( + .A ( top_width_0_height_0__pin_15_lower[0] ) , + .X ( top_width_0_height_0__pin_15_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_87__86 ( + .A ( top_width_0_height_0__pin_17_lower[0] ) , + .X ( top_width_0_height_0__pin_17_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__buf_8 ZBUF_208_inst_110 ( .A ( aps_rename_507_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_111 ( .A ( aps_rename_509_ ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_217_inst_112 ( .A ( aps_rename_506_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ; +sky130_fd_sc_hd__buf_8 ZBUF_898_f_inst_113 ( .A ( aps_rename_508_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1106 ) , + .X ( prog_clk_0_W_out ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v new file mode 100644 index 0000000..19a0b5d --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v @@ -0,0 +1,2524 @@ +// +// +// +// +// +// +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_113 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_113 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_110 ) , + .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_111 ) , + .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_113 ) , + .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_109 ) , + .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS , ZBUF_898_f_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; +input ZBUF_898_f_0 ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_898_f_0 ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , + ZBUF_898_f_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input ZBUF_898_f_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .ZBUF_898_f_0 ( ZBUF_898_f_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , ZBUF_898_f_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input ZBUF_898_f_0 ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .ZBUF_898_f_0 ( ZBUF_898_f_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS , ZBUF_208_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; +input ZBUF_208_0 ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_208_0 ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( ZBUF_208_0 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_7 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , + ZBUF_208_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input ZBUF_208_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_7 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .ZBUF_208_0 ( ZBUF_208_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__7 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , ZBUF_208_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input ZBUF_208_0 ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .ZBUF_208_0 ( ZBUF_208_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( net_net_96 ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_6 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_6 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__6 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS , ZBUF_217_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; +input ZBUF_217_0 ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_217_0 ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( ZBUF_217_0 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_5 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , + ZBUF_217_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input ZBUF_217_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_5 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .ZBUF_217_0 ( ZBUF_217_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__5 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , ZBUF_217_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input ZBUF_217_0 ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .ZBUF_217_0 ( ZBUF_217_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( net_net_95 ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_4 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__4 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_93 ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_93 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_94 ) , .Y ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( BUF_net_93 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_3 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__3 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( net_net_91 ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_1 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__1 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_0 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__0 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_123 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( ccff_head[0] ) , + .X ( copt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_116 ) , + .X ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_114 ) , + .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1358 ( .A ( copt_net_115 ) , + .X ( copt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 copt_h_inst_1359 ( .A ( ropt_net_124 ) , + .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_117 ) , + .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_118 ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_119 ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_102 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , + bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ , + bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ , + top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ , + top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower , + top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower , + top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower , + top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower , + top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , + top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , + top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower , + top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower , + top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower , + SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , pReset_E_in , + pReset_W_in , pReset_W_out , pReset_E_out , prog_clk_0_N_in , + prog_clk_0_W_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_16_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +input [0:0] top_width_0_height_0__pin_12_ ; +input [0:0] top_width_0_height_0__pin_14_ ; +input [0:0] top_width_0_height_0__pin_16_ ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] top_width_0_height_0__pin_3_upper ; +output [0:0] top_width_0_height_0__pin_3_lower ; +output [0:0] top_width_0_height_0__pin_5_upper ; +output [0:0] top_width_0_height_0__pin_5_lower ; +output [0:0] top_width_0_height_0__pin_7_upper ; +output [0:0] top_width_0_height_0__pin_7_lower ; +output [0:0] top_width_0_height_0__pin_9_upper ; +output [0:0] top_width_0_height_0__pin_9_lower ; +output [0:0] top_width_0_height_0__pin_11_upper ; +output [0:0] top_width_0_height_0__pin_11_lower ; +output [0:0] top_width_0_height_0__pin_13_upper ; +output [0:0] top_width_0_height_0__pin_13_lower ; +output [0:0] top_width_0_height_0__pin_15_upper ; +output [0:0] top_width_0_height_0__pin_15_lower ; +output [0:0] top_width_0_height_0__pin_17_upper ; +output [0:0] top_width_0_height_0__pin_17_lower ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_E_out ; +input prog_clk_0_N_in ; +output prog_clk_0_W_out ; +input VDD ; +input VSS ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__7_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; + +cbx_1__0__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_1 mux_top_ipin_1 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_2 mux_top_ipin_2 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_3 mux_top_ipin_3 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_4 mux_top_ipin_4 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_5 mux_top_ipin_5 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_6 mux_top_ipin_6 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_7 mux_top_ipin_7 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12 mux_top_ipin_8 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( top_width_0_height_0__pin_1_lower ) , + .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_3_lower ) , + .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_5_lower ) , + .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_7_lower ) , + .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_9_lower ) , + .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_506_ } ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_11_lower ) , + .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .ZBUF_217_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ; +cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , + .io_outpad ( top_width_0_height_0__pin_12_ ) , + .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_13_lower ) , + .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_507_ } ) , + .io_outpad ( top_width_0_height_0__pin_14_ ) , + .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_15_lower ) , + .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .ZBUF_208_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ; +cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_508_ } ) , + .io_outpad ( top_width_0_height_0__pin_16_ ) , + .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_17_lower ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .ZBUF_898_f_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , + .X ( ctsbuf_net_1106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( top_width_0_height_0__pin_1_lower[0] ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( + .A ( top_width_0_height_0__pin_3_lower[0] ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( + .A ( top_width_0_height_0__pin_5_lower[0] ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_82__81 ( + .A ( top_width_0_height_0__pin_7_lower[0] ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_83__82 ( + .A ( top_width_0_height_0__pin_9_lower[0] ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_84__83 ( + .A ( top_width_0_height_0__pin_11_lower[0] ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_85__84 ( + .A ( top_width_0_height_0__pin_13_lower[0] ) , + .X ( top_width_0_height_0__pin_13_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_86__85 ( + .A ( top_width_0_height_0__pin_15_lower[0] ) , + .X ( top_width_0_height_0__pin_15_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_87__86 ( + .A ( top_width_0_height_0__pin_17_lower[0] ) , + .X ( top_width_0_height_0__pin_17_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ZBUF_208_inst_110 ( .A ( aps_rename_507_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_111 ( .A ( aps_rename_509_ ) , + .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_217_inst_112 ( .A ( aps_rename_506_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ZBUF_898_f_inst_113 ( .A ( aps_rename_508_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1106 ) , + .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v new file mode 100644 index 0000000..6408f62 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v @@ -0,0 +1,2067 @@ +// +// +// +// +// +// +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_113 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_113 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_110 ) , + .X ( copt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_111 ) , + .X ( copt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_113 ) , + .X ( copt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_109 ) , + .X ( mem_out[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_898_f_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input ZBUF_898_f_0 ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_898_f_0 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_898_f_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input ZBUF_898_f_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .ZBUF_898_f_0 ( ZBUF_898_f_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , ZBUF_898_f_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input ZBUF_898_f_0 ; + +cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .ZBUF_898_f_0 ( ZBUF_898_f_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_208_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input ZBUF_208_0 ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_208_0 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( ZBUF_208_0 ) , .Z ( SOC_OUT ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_7 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_208_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input ZBUF_208_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_7 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .ZBUF_208_0 ( ZBUF_208_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__7 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , ZBUF_208_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input ZBUF_208_0 ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .ZBUF_208_0 ( ZBUF_208_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_96 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( net_net_96 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_6 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_6 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__6 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_217_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input ZBUF_217_0 ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_217_0 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( ZBUF_217_0 ) , .Z ( SOC_OUT ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_5 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_217_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input ZBUF_217_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_5 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .ZBUF_217_0 ( ZBUF_217_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__5 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , ZBUF_217_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input ZBUF_217_0 ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .ZBUF_217_0 ( ZBUF_217_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_95 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( net_net_95 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_4 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__4 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_93 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_93 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_94 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_3 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__3 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_91 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( net_net_91 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_90 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_1 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__1 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_89 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_0 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__0 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_123 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( ccff_head[0] ) , + .X ( copt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_116 ) , + .X ( copt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_114 ) , + .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1358 ( .A ( copt_net_115 ) , + .X ( copt_net_117 ) ) ; +sky130_fd_sc_hd__bufbuf_16 copt_h_inst_1359 ( .A ( ropt_net_124 ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_117 ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_118 ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_119 ) , + .X ( ropt_net_124 ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_102 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , + bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ , + bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ , + top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ , + top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower , + top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower , + top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower , + top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower , + top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , + top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , + top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower , + top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower , + top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower , + SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , pReset_E_in , + pReset_W_in , pReset_W_out , pReset_E_out , prog_clk_0_N_in , + prog_clk_0_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_16_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +input [0:0] top_width_0_height_0__pin_12_ ; +input [0:0] top_width_0_height_0__pin_14_ ; +input [0:0] top_width_0_height_0__pin_16_ ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] top_width_0_height_0__pin_3_upper ; +output [0:0] top_width_0_height_0__pin_3_lower ; +output [0:0] top_width_0_height_0__pin_5_upper ; +output [0:0] top_width_0_height_0__pin_5_lower ; +output [0:0] top_width_0_height_0__pin_7_upper ; +output [0:0] top_width_0_height_0__pin_7_lower ; +output [0:0] top_width_0_height_0__pin_9_upper ; +output [0:0] top_width_0_height_0__pin_9_lower ; +output [0:0] top_width_0_height_0__pin_11_upper ; +output [0:0] top_width_0_height_0__pin_11_lower ; +output [0:0] top_width_0_height_0__pin_13_upper ; +output [0:0] top_width_0_height_0__pin_13_lower ; +output [0:0] top_width_0_height_0__pin_15_upper ; +output [0:0] top_width_0_height_0__pin_15_lower ; +output [0:0] top_width_0_height_0__pin_17_upper ; +output [0:0] top_width_0_height_0__pin_17_lower ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_E_out ; +input prog_clk_0_N_in ; +output prog_clk_0_W_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__7_ccff_tail ; + +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; + +cbx_1__0__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_1 mux_top_ipin_1 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_2 mux_top_ipin_2 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_3 mux_top_ipin_3 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_4 mux_top_ipin_4 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_5 mux_top_ipin_5 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_6 mux_top_ipin_6 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_7 mux_top_ipin_7 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12 mux_top_ipin_8 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( top_width_0_height_0__pin_1_lower ) , + .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_3_lower ) , + .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_5_lower ) , + .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_7_lower ) , + .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_9_lower ) , + .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_506_ } ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_11_lower ) , + .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) , + .ZBUF_217_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ; +cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , + .io_outpad ( top_width_0_height_0__pin_12_ ) , + .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_13_lower ) , + .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_507_ } ) , + .io_outpad ( top_width_0_height_0__pin_14_ ) , + .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_15_lower ) , + .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) , + .ZBUF_208_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ; +cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_508_ } ) , + .io_outpad ( top_width_0_height_0__pin_16_ ) , + .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_17_lower ) , + .ccff_tail ( ccff_tail ) , + .ZBUF_898_f_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( aps_rename_509_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , + .X ( ctsbuf_net_1106 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( top_width_0_height_0__pin_1_lower[0] ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( + .A ( top_width_0_height_0__pin_3_lower[0] ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( + .A ( top_width_0_height_0__pin_5_lower[0] ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_82__81 ( + .A ( top_width_0_height_0__pin_7_lower[0] ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_83__82 ( + .A ( top_width_0_height_0__pin_9_lower[0] ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_84__83 ( + .A ( top_width_0_height_0__pin_11_lower[0] ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_85__84 ( + .A ( top_width_0_height_0__pin_13_lower[0] ) , + .X ( top_width_0_height_0__pin_13_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_86__85 ( + .A ( top_width_0_height_0__pin_15_lower[0] ) , + .X ( top_width_0_height_0__pin_15_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_87__86 ( + .A ( top_width_0_height_0__pin_17_lower[0] ) , + .X ( top_width_0_height_0__pin_17_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__buf_8 ZBUF_208_inst_110 ( .A ( aps_rename_507_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_111 ( .A ( aps_rename_509_ ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_217_inst_112 ( .A ( aps_rename_506_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ; +sky130_fd_sc_hd__buf_8 ZBUF_898_f_inst_113 ( .A ( aps_rename_508_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1106 ) , + .X ( prog_clk_0_W_out ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..d847635 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__0__icv_in_design.top_only.pt.v @@ -0,0 +1,504 @@ +// +// +// +// +// +// +module cbx_1__0_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , + bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ , + bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ , + top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ , + top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower , + top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower , + top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower , + top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower , + top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , + top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , + top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower , + top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower , + top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower , + SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , pReset_E_in , + pReset_W_in , pReset_W_out , pReset_E_out , prog_clk_0_N_in , + prog_clk_0_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_16_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +input [0:0] top_width_0_height_0__pin_12_ ; +input [0:0] top_width_0_height_0__pin_14_ ; +input [0:0] top_width_0_height_0__pin_16_ ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] top_width_0_height_0__pin_3_upper ; +output [0:0] top_width_0_height_0__pin_3_lower ; +output [0:0] top_width_0_height_0__pin_5_upper ; +output [0:0] top_width_0_height_0__pin_5_lower ; +output [0:0] top_width_0_height_0__pin_7_upper ; +output [0:0] top_width_0_height_0__pin_7_lower ; +output [0:0] top_width_0_height_0__pin_9_upper ; +output [0:0] top_width_0_height_0__pin_9_lower ; +output [0:0] top_width_0_height_0__pin_11_upper ; +output [0:0] top_width_0_height_0__pin_11_lower ; +output [0:0] top_width_0_height_0__pin_13_upper ; +output [0:0] top_width_0_height_0__pin_13_lower ; +output [0:0] top_width_0_height_0__pin_15_upper ; +output [0:0] top_width_0_height_0__pin_15_lower ; +output [0:0] top_width_0_height_0__pin_17_upper ; +output [0:0] top_width_0_height_0__pin_17_lower ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_E_out ; +input prog_clk_0_N_in ; +output prog_clk_0_W_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__7_ccff_tail ; + +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; + +cbx_1__0__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_1 mux_top_ipin_1 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_2 mux_top_ipin_2 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_3 mux_top_ipin_3 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_4 mux_top_ipin_4 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_5 mux_top_ipin_5 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_6 mux_top_ipin_6 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_7 mux_top_ipin_7 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12 mux_top_ipin_8 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( top_width_0_height_0__pin_1_lower ) , + .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_3_lower ) , + .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_5_lower ) , + .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_7_lower ) , + .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_9_lower ) , + .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_506_ } ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_11_lower ) , + .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) , + .ZBUF_217_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ; +cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , + .io_outpad ( top_width_0_height_0__pin_12_ ) , + .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_13_lower ) , + .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_507_ } ) , + .io_outpad ( top_width_0_height_0__pin_14_ ) , + .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_15_lower ) , + .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) , + .ZBUF_208_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ; +cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_508_ } ) , + .io_outpad ( top_width_0_height_0__pin_16_ ) , + .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_17_lower ) , + .ccff_tail ( ccff_tail ) , + .ZBUF_898_f_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( aps_rename_509_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , + .X ( ctsbuf_net_1106 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( top_width_0_height_0__pin_1_lower[0] ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( + .A ( top_width_0_height_0__pin_3_lower[0] ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( + .A ( top_width_0_height_0__pin_5_lower[0] ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_82__81 ( + .A ( top_width_0_height_0__pin_7_lower[0] ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_83__82 ( + .A ( top_width_0_height_0__pin_9_lower[0] ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_84__83 ( + .A ( top_width_0_height_0__pin_11_lower[0] ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_85__84 ( + .A ( top_width_0_height_0__pin_13_lower[0] ) , + .X ( top_width_0_height_0__pin_13_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_86__85 ( + .A ( top_width_0_height_0__pin_15_lower[0] ) , + .X ( top_width_0_height_0__pin_15_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_87__86 ( + .A ( top_width_0_height_0__pin_17_lower[0] ) , + .X ( top_width_0_height_0__pin_17_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__buf_8 ZBUF_208_inst_110 ( .A ( aps_rename_507_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_111 ( .A ( aps_rename_509_ ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_217_inst_112 ( .A ( aps_rename_506_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ; +sky130_fd_sc_hd__buf_8 ZBUF_898_f_inst_113 ( .A ( aps_rename_508_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1106 ) , + .X ( prog_clk_0_W_out ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v new file mode 100644 index 0000000..1787466 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v @@ -0,0 +1,1943 @@ +// +// +// +// +// +// +module cbx_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_14 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__const1_13 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_12 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__const1_11 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_10 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_86 ) ) ; +endmodule + + +module cbx_1__1__const1_9 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_8 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_101 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( copt_net_95 ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1325 ( .A ( copt_net_96 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_97 ) , + .X ( copt_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_98 ) , + .X ( copt_net_101 ) ) ; +endmodule + + +module cbx_1__1__const1_7 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_84 ) ) ; +endmodule + + +module cbx_1__1__const1_6 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__const1_5 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_4 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__const1_3 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_2 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__const1_0 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , + REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , CIN_FEEDTHROUGH , + COUT_FEEDTHROUGH , pReset_E_in , pReset_W_in , pReset_W_out , + pReset_S_out , pReset_E_out , prog_clk_0_N_in , prog_clk_0_W_out , + prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , prog_clk_1_S_out , + prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_E_out , + prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , prog_clk_3_W_out , + clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , clk_2_E_in , + clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , + clk_3_E_out , clk_3_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input REGIN_FEEDTHROUGH ; +output REGOUT_FEEDTHROUGH ; +input CIN_FEEDTHROUGH ; +output COUT_FEEDTHROUGH ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_S_out ; +output pReset_E_out ; +input prog_clk_0_N_in ; +output prog_clk_0_W_out ; +input prog_clk_1_W_in ; +input prog_clk_1_E_in ; +output prog_clk_1_N_out ; +output prog_clk_1_S_out ; +input prog_clk_2_E_in ; +input prog_clk_2_W_in ; +output prog_clk_2_W_out ; +output prog_clk_2_E_out ; +input prog_clk_3_W_in ; +input prog_clk_3_E_in ; +output prog_clk_3_E_out ; +output prog_clk_3_W_out ; +input clk_1_W_in ; +input clk_1_E_in ; +output clk_1_N_out ; +output clk_1_S_out ; +input clk_2_E_in ; +input clk_2_W_in ; +output clk_2_W_out ; +output clk_2_E_out ; +input clk_3_W_in ; +input clk_3_E_in ; +output clk_3_E_out ; +output clk_3_W_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; + +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_1_W_in = prog_clk_1_E_in ; +assign prog_clk_2_E_in = prog_clk_2_W_in ; +assign prog_clk_3_W_in = prog_clk_3_E_in ; +assign clk_1_W_in = clk_1_E_in ; +assign clk_2_E_in = clk_2_W_in ; +assign clk_3_W_in = clk_3_E_in ; + +cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , + chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , + chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , + chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[22] , + chanx_left_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[24] , + chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , + chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_90 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] , + chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , + chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_90 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( { copt_net_100 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , + .X ( ctsbuf_net_193 ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( prog_clk_3_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , + .X ( clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , + .X ( clk_3_W_out ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , + .X ( REGOUT_FEEDTHROUGH ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , + .X ( COUT_FEEDTHROUGH ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_602 ( .A ( aps_rename_507_ ) , + .X ( clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_603 ( .A ( aps_rename_505_ ) , + .X ( prog_clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_240_f_inst_604 ( .A ( aps_rename_508_ ) , + .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_39_inst_605 ( .A ( aps_rename_506_ ) , + .X ( prog_clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 copt_h_inst_1328 ( .A ( copt_net_102 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531229 ( .A ( ctsbuf_net_193 ) , + .X ( prog_clk_0_W_out ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_100 ) , + .X ( copt_net_102 ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v new file mode 100644 index 0000000..2fa4f14 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v @@ -0,0 +1,2128 @@ +// +// +// +// +// +// +module cbx_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_101 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( copt_net_95 ) , + .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1325 ( .A ( copt_net_96 ) , + .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_97 ) , + .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_98 ) , + .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , + REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , CIN_FEEDTHROUGH , + COUT_FEEDTHROUGH , pReset_E_in , pReset_W_in , pReset_W_out , + pReset_S_out , pReset_E_out , prog_clk_0_N_in , prog_clk_0_W_out , + prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , prog_clk_1_S_out , + prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_E_out , + prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , prog_clk_3_W_out , + clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , clk_2_E_in , + clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , + clk_3_E_out , clk_3_W_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input REGIN_FEEDTHROUGH ; +output REGOUT_FEEDTHROUGH ; +input CIN_FEEDTHROUGH ; +output COUT_FEEDTHROUGH ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_S_out ; +output pReset_E_out ; +input prog_clk_0_N_in ; +output prog_clk_0_W_out ; +input prog_clk_1_W_in ; +input prog_clk_1_E_in ; +output prog_clk_1_N_out ; +output prog_clk_1_S_out ; +input prog_clk_2_E_in ; +input prog_clk_2_W_in ; +output prog_clk_2_W_out ; +output prog_clk_2_E_out ; +input prog_clk_3_W_in ; +input prog_clk_3_E_in ; +output prog_clk_3_E_out ; +output prog_clk_3_W_out ; +input clk_1_W_in ; +input clk_1_E_in ; +output clk_1_N_out ; +output clk_1_S_out ; +input clk_2_E_in ; +input clk_2_W_in ; +output clk_2_W_out ; +output clk_2_E_out ; +input clk_3_W_in ; +input clk_3_E_in ; +output clk_3_E_out ; +output clk_3_W_out ; +input VDD ; +input VSS ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_1_W_in = prog_clk_1_E_in ; +assign prog_clk_2_E_in = prog_clk_2_W_in ; +assign prog_clk_3_W_in = prog_clk_3_E_in ; +assign clk_1_W_in = clk_1_E_in ; +assign clk_2_E_in = clk_2_W_in ; +assign clk_3_W_in = clk_3_E_in ; + +cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , + chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , + chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , + chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[22] , + chanx_left_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[24] , + chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , + chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] , + chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , + chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( { copt_net_100 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , + .X ( ctsbuf_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( prog_clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( prog_clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , + .X ( clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , + .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , + .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , + .X ( clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , + .X ( REGOUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , + .X ( COUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_602 ( .A ( aps_rename_507_ ) , + .X ( clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_603 ( .A ( aps_rename_505_ ) , + .X ( prog_clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_240_f_inst_604 ( .A ( aps_rename_508_ ) , + .X ( clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_39_inst_605 ( .A ( aps_rename_506_ ) , + .X ( prog_clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 copt_h_inst_1328 ( .A ( copt_net_102 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531229 ( .A ( ctsbuf_net_193 ) , + .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_100 ) , + .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v new file mode 100644 index 0000000..70ff493 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v @@ -0,0 +1,1767 @@ +// +// +// +// +// +// +module cbx_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_86 ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_101 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( copt_net_95 ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1325 ( .A ( copt_net_96 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_97 ) , + .X ( copt_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_98 ) , + .X ( copt_net_101 ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_84 ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , + REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , CIN_FEEDTHROUGH , + COUT_FEEDTHROUGH , pReset_E_in , pReset_W_in , pReset_W_out , + pReset_S_out , pReset_E_out , prog_clk_0_N_in , prog_clk_0_W_out , + prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , prog_clk_1_S_out , + prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_E_out , + prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , prog_clk_3_W_out , + clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , clk_2_E_in , + clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , + clk_3_E_out , clk_3_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input REGIN_FEEDTHROUGH ; +output REGOUT_FEEDTHROUGH ; +input CIN_FEEDTHROUGH ; +output COUT_FEEDTHROUGH ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_S_out ; +output pReset_E_out ; +input prog_clk_0_N_in ; +output prog_clk_0_W_out ; +input prog_clk_1_W_in ; +input prog_clk_1_E_in ; +output prog_clk_1_N_out ; +output prog_clk_1_S_out ; +input prog_clk_2_E_in ; +input prog_clk_2_W_in ; +output prog_clk_2_W_out ; +output prog_clk_2_E_out ; +input prog_clk_3_W_in ; +input prog_clk_3_E_in ; +output prog_clk_3_E_out ; +output prog_clk_3_W_out ; +input clk_1_W_in ; +input clk_1_E_in ; +output clk_1_N_out ; +output clk_1_S_out ; +input clk_2_E_in ; +input clk_2_W_in ; +output clk_2_W_out ; +output clk_2_E_out ; +input clk_3_W_in ; +input clk_3_E_in ; +output clk_3_E_out ; +output clk_3_W_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; + +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_1_E_in = prog_clk_1_W_in ; +assign prog_clk_2_W_in = prog_clk_2_E_in ; +assign prog_clk_3_E_in = prog_clk_3_W_in ; +assign clk_1_E_in = clk_1_W_in ; +assign clk_2_W_in = clk_2_E_in ; +assign clk_3_E_in = clk_3_W_in ; + +cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , + chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , + chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , + chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[22] , + chanx_left_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[24] , + chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , + chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_90 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] , + chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , + chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_90 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( { copt_net_100 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , + .X ( ctsbuf_net_193 ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( prog_clk_3_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , + .X ( clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , + .X ( clk_3_W_out ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , + .X ( REGOUT_FEEDTHROUGH ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , + .X ( COUT_FEEDTHROUGH ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_602 ( .A ( aps_rename_507_ ) , + .X ( clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_603 ( .A ( aps_rename_505_ ) , + .X ( prog_clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_240_f_inst_604 ( .A ( aps_rename_508_ ) , + .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_39_inst_605 ( .A ( aps_rename_506_ ) , + .X ( prog_clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 copt_h_inst_1328 ( .A ( copt_net_102 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531229 ( .A ( ctsbuf_net_193 ) , + .X ( prog_clk_0_W_out ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_100 ) , + .X ( copt_net_102 ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..5ac54ec --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__1__icv_in_design.top_only.pt.v @@ -0,0 +1,538 @@ +// +// +// +// +// +// +module cbx_1__1_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , + REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , CIN_FEEDTHROUGH , + COUT_FEEDTHROUGH , pReset_E_in , pReset_W_in , pReset_W_out , + pReset_S_out , pReset_E_out , prog_clk_0_N_in , prog_clk_0_W_out , + prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , prog_clk_1_S_out , + prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_E_out , + prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , prog_clk_3_W_out , + clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , clk_2_E_in , + clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , + clk_3_E_out , clk_3_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input REGIN_FEEDTHROUGH ; +output REGOUT_FEEDTHROUGH ; +input CIN_FEEDTHROUGH ; +output COUT_FEEDTHROUGH ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_S_out ; +output pReset_E_out ; +input prog_clk_0_N_in ; +output prog_clk_0_W_out ; +input prog_clk_1_W_in ; +input prog_clk_1_E_in ; +output prog_clk_1_N_out ; +output prog_clk_1_S_out ; +input prog_clk_2_E_in ; +input prog_clk_2_W_in ; +output prog_clk_2_W_out ; +output prog_clk_2_E_out ; +input prog_clk_3_W_in ; +input prog_clk_3_E_in ; +output prog_clk_3_E_out ; +output prog_clk_3_W_out ; +input clk_1_W_in ; +input clk_1_E_in ; +output clk_1_N_out ; +output clk_1_S_out ; +input clk_2_E_in ; +input clk_2_W_in ; +output clk_2_W_out ; +output clk_2_E_out ; +input clk_3_W_in ; +input clk_3_E_in ; +output clk_3_E_out ; +output clk_3_W_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; + +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_1_E_in = prog_clk_1_W_in ; +assign prog_clk_2_W_in = prog_clk_2_E_in ; +assign prog_clk_3_E_in = prog_clk_3_W_in ; +assign clk_1_E_in = clk_1_W_in ; +assign clk_2_W_in = clk_2_E_in ; +assign clk_3_E_in = clk_3_W_in ; + +cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , + chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_89 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , + chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , + chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[22] , + chanx_left_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_91 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[24] , + chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , + chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_90 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] , + chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , + chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_90 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_92 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( { copt_net_100 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , + .X ( ctsbuf_net_193 ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( prog_clk_3_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , + .X ( clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , + .X ( clk_3_W_out ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , + .X ( REGOUT_FEEDTHROUGH ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , + .X ( COUT_FEEDTHROUGH ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_602 ( .A ( aps_rename_507_ ) , + .X ( clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_603 ( .A ( aps_rename_505_ ) , + .X ( prog_clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_240_f_inst_604 ( .A ( aps_rename_508_ ) , + .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_39_inst_605 ( .A ( aps_rename_506_ ) , + .X ( prog_clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 copt_h_inst_1328 ( .A ( copt_net_102 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531229 ( .A ( ctsbuf_net_193 ) , + .X ( prog_clk_0_W_out ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_100 ) , + .X ( copt_net_102 ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v new file mode 100644 index 0000000..3356e10 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v @@ -0,0 +1,2082 @@ +// +// +// +// +// +// +module cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_108 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_108 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_108 ) , + .X ( mem_out[0] ) ) ; +endmodule + + +module cbx_1__2__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( BUF_net_83 ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_83 ) ) ; +endmodule + + +module cbx_1__2__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__2__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__2__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_15 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_100 ) ) ; +endmodule + + +module cbx_1__2__const1_14 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_13 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_12 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__2__const1_11 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_97 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +endmodule + + +module cbx_1__2__const1_10 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_9 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__const1_8 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_95 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +endmodule + + +module cbx_1__2__const1_7 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_87 ) ) ; +endmodule + + +module cbx_1__2__const1_6 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_5 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_4 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_3 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_2 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_0 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +endmodule + + +module cbx_1__2_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT , + SC_IN_BOT , SC_OUT_TOP , pReset_E_in , pReset_W_in , pReset_W_out , + pReset_S_out , pReset_E_out , prog_clk_0_S_in , prog_clk_0_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] top_grid_pin_0_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_S_out ; +output pReset_E_out ; +input prog_clk_0_S_in ; +output prog_clk_0_W_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; + +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; + +cbx_1__2__mux_tree_tapbuf_size12_0 mux_bottom_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_1 mux_top_ipin_0 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_2 mux_top_ipin_2 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_3 mux_top_ipin_4 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_4 mux_top_ipin_6 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_5 mux_top_ipin_8 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_6 mux_top_ipin_10 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_7 mux_top_ipin_12 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_0 mem_bottom_ipin_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , + chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , + chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[21] , + chanx_left_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[23] , + chanx_left_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , + chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_102 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] , + chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , + chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] , + chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , + chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_1107 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( bottom_width_0_height_0__pin_1_lower[0] ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk_0_W_out ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v new file mode 100644 index 0000000..104baea --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v @@ -0,0 +1,2311 @@ +// +// +// +// +// +// +module cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_108 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_108 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_108 ) , + .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , + .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( BUF_net_83 ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__2__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__2__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_97 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_95 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT , + SC_IN_BOT , SC_OUT_TOP , pReset_E_in , pReset_W_in , pReset_W_out , + pReset_S_out , pReset_E_out , prog_clk_0_S_in , prog_clk_0_W_out , VDD , + VSS ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] top_grid_pin_0_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_S_out ; +output pReset_E_out ; +input prog_clk_0_S_in ; +output prog_clk_0_W_out ; +input VDD ; +input VSS ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; + +cbx_1__2__mux_tree_tapbuf_size12_0 mux_bottom_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_1 mux_top_ipin_0 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_2 mux_top_ipin_2 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_3 mux_top_ipin_4 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_4 mux_top_ipin_6 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_5 mux_top_ipin_8 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_6 mux_top_ipin_10 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_7 mux_top_ipin_12 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_0 mem_bottom_ipin_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , + chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , + chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[21] , + chanx_left_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[23] , + chanx_left_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , + chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] , + chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , + chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] , + chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , + chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_1107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( bottom_width_0_height_0__pin_1_lower[0] ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v new file mode 100644 index 0000000..8ad81b8 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v @@ -0,0 +1,1895 @@ +// +// +// +// +// +// +module cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_108 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_108 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_108 ) , + .X ( mem_out[0] ) ) ; +endmodule + + +module cbx_1__2__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( BUF_net_83 ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_83 ) ) ; +endmodule + + +module cbx_1__2__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__2__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__2__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_100 ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_97 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_95 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_87 ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +endmodule + + +module cbx_1__2_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT , + SC_IN_BOT , SC_OUT_TOP , pReset_E_in , pReset_W_in , pReset_W_out , + pReset_S_out , pReset_E_out , prog_clk_0_S_in , prog_clk_0_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] top_grid_pin_0_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_S_out ; +output pReset_E_out ; +input prog_clk_0_S_in ; +output prog_clk_0_W_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; + +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; + +cbx_1__2__mux_tree_tapbuf_size12_0 mux_bottom_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_1 mux_top_ipin_0 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_2 mux_top_ipin_2 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_3 mux_top_ipin_4 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_4 mux_top_ipin_6 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_5 mux_top_ipin_8 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_6 mux_top_ipin_10 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_7 mux_top_ipin_12 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_0 mem_bottom_ipin_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , + chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , + chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[21] , + chanx_left_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[23] , + chanx_left_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , + chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_102 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] , + chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , + chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] , + chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , + chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_1107 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( bottom_width_0_height_0__pin_1_lower[0] ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk_0_W_out ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..81ad05f --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cbx_1__2__icv_in_design.top_only.pt.v @@ -0,0 +1,500 @@ +// +// +// +// +// +// +module cbx_1__2_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT , + SC_IN_BOT , SC_OUT_TOP , pReset_E_in , pReset_W_in , pReset_W_out , + pReset_S_out , pReset_E_out , prog_clk_0_S_in , prog_clk_0_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] top_grid_pin_0_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_S_out ; +output pReset_E_out ; +input prog_clk_0_S_in ; +output prog_clk_0_W_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; + +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; + +cbx_1__2__mux_tree_tapbuf_size12_0 mux_bottom_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_1 mux_top_ipin_0 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_2 mux_top_ipin_2 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_3 mux_top_ipin_4 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_4 mux_top_ipin_6 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_5 mux_top_ipin_8 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_6 mux_top_ipin_10 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_7 mux_top_ipin_12 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_0 mem_bottom_ipin_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , + chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , + chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[21] , + chanx_left_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[23] , + chanx_left_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , + chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_102 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] , + chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , + chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] , + chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , + chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_1107 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( bottom_width_0_height_0__pin_1_lower[0] ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk_0_W_out ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v new file mode 100644 index 0000000..c73d82d --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v @@ -0,0 +1,441 @@ +// +// +// +// +// +// +module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_74 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_74 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_75 ) , + .X ( copt_net_73 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_78 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_74 ) , + .X ( copt_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_73 ) , + .X ( copt_net_76 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_76 ) , + .X ( copt_net_77 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_77 ) , + .X ( copt_net_78 ) ) ; +endmodule + + +module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , + .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_65 ) , .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_65 ) ) ; +endmodule + + +module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cby_0__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_71 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1211 ( .A ( ccff_head[0] ) , + .X ( copt_net_67 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1212 ( .A ( copt_net_67 ) , + .X ( copt_net_68 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1213 ( .A ( copt_net_68 ) , + .X ( copt_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1214 ( .A ( copt_net_69 ) , + .X ( copt_net_70 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_72 ) , + .X ( copt_net_71 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_70 ) , + .X ( copt_net_72 ) ) ; +endmodule + + +module cby_0__1__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_0__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_0__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_0__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , + IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] left_grid_pin_0_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] right_width_0_height_0__pin_0_ ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; +input pReset_N_in ; +input prog_clk_0_E_in ; + +wire ropt_net_120 ; +wire ropt_net_118 ; +wire ropt_net_136 ; +wire ropt_net_117 ; +wire ropt_net_121 ; +wire ropt_net_125 ; +wire ropt_net_124 ; +wire ropt_net_122 ; +wire ropt_net_115 ; +wire ropt_net_116 ; +wire ropt_net_126 ; +wire ropt_net_119 ; +wire ropt_net_123 ; +wire ropt_net_114 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; + +assign prog_clk_0 = prog_clk[0] ; + +cby_0__1__mux_tree_tapbuf_size12 mux_right_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_66 ) ) ; +cby_0__1__mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( right_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_bottom_in[27] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_63__62 ( + .A ( right_width_0_height_0__pin_1_lower[0] ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_66 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_114 ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1259 ( .A ( ropt_net_115 ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1260 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1261 ( .A ( ropt_net_117 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1262 ( .A ( ropt_net_118 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_119 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_121 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_123 ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1269 ( .A ( ropt_net_125 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_126 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[8] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v new file mode 100644 index 0000000..0ce9604 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v @@ -0,0 +1,486 @@ +// +// +// +// +// +// +module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_74 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_74 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_75 ) , + .X ( copt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_78 ) , + .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_74 ) , + .X ( copt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_73 ) , + .X ( copt_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_76 ) , + .X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_77 ) , + .X ( copt_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , + .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_65 ) , .Y ( BUF_net_63 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cby_0__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_71 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1211 ( .A ( ccff_head[0] ) , + .X ( copt_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1212 ( .A ( copt_net_67 ) , + .X ( copt_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1213 ( .A ( copt_net_68 ) , + .X ( copt_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1214 ( .A ( copt_net_69 ) , + .X ( copt_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_72 ) , + .X ( copt_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_70 ) , + .X ( copt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_0__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_0__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , + IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in , + VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] left_grid_pin_0_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] right_width_0_height_0__pin_0_ ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; +input pReset_N_in ; +input prog_clk_0_E_in ; +input VDD ; +input VSS ; + +wire ropt_net_120 ; +wire ropt_net_118 ; +wire ropt_net_136 ; +wire ropt_net_117 ; +wire ropt_net_121 ; +wire ropt_net_125 ; +wire ropt_net_124 ; +wire ropt_net_122 ; +wire ropt_net_115 ; +wire ropt_net_116 ; +wire ropt_net_126 ; +wire ropt_net_119 ; +wire ropt_net_123 ; +wire ropt_net_114 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +cby_0__1__mux_tree_tapbuf_size12 mux_right_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_66 ) ) ; +cby_0__1__mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( right_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_bottom_in[27] ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) , + .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_63__62 ( + .A ( right_width_0_height_0__pin_1_lower[0] ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_114 ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1259 ( .A ( ropt_net_115 ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1260 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1261 ( .A ( ropt_net_117 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1262 ( .A ( ropt_net_118 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_119 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_121 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_123 ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1269 ( .A ( ropt_net_125 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_126 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v new file mode 100644 index 0000000..333dd81 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v @@ -0,0 +1,430 @@ +// +// +// +// +// +// +module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_74 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_74 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_75 ) , + .X ( copt_net_73 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_78 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_74 ) , + .X ( copt_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_73 ) , + .X ( copt_net_76 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_76 ) , + .X ( copt_net_77 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_77 ) , + .X ( copt_net_78 ) ) ; +endmodule + + +module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , + .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_65 ) , .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_65 ) ) ; +endmodule + + +module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cby_0__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_71 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1211 ( .A ( ccff_head[0] ) , + .X ( copt_net_67 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1212 ( .A ( copt_net_67 ) , + .X ( copt_net_68 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1213 ( .A ( copt_net_68 ) , + .X ( copt_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1214 ( .A ( copt_net_69 ) , + .X ( copt_net_70 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_72 ) , + .X ( copt_net_71 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_70 ) , + .X ( copt_net_72 ) ) ; +endmodule + + +module cby_0__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_0__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , + IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] left_grid_pin_0_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] right_width_0_height_0__pin_0_ ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; +input pReset_N_in ; +input prog_clk_0_E_in ; + +wire ropt_net_120 ; +wire ropt_net_118 ; +wire ropt_net_136 ; +wire ropt_net_117 ; +wire ropt_net_121 ; +wire ropt_net_125 ; +wire ropt_net_124 ; +wire ropt_net_122 ; +wire ropt_net_115 ; +wire ropt_net_116 ; +wire ropt_net_126 ; +wire ropt_net_119 ; +wire ropt_net_123 ; +wire ropt_net_114 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; + +assign prog_clk_0 = prog_clk[0] ; + +cby_0__1__mux_tree_tapbuf_size12 mux_right_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_66 ) ) ; +cby_0__1__mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( right_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_bottom_in[27] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_63__62 ( + .A ( right_width_0_height_0__pin_1_lower[0] ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_66 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_114 ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1259 ( .A ( ropt_net_115 ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1260 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1261 ( .A ( ropt_net_117 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1262 ( .A ( ropt_net_118 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_119 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_121 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_123 ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1269 ( .A ( ropt_net_125 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_126 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[8] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..1aa3b76 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_0__1__icv_in_design.top_only.pt.v @@ -0,0 +1,231 @@ +// +// +// +// +// +// +module cby_0__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , + IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] left_grid_pin_0_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] right_width_0_height_0__pin_0_ ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; +input pReset_N_in ; +input prog_clk_0_E_in ; + +wire ropt_net_120 ; +wire ropt_net_118 ; +wire ropt_net_136 ; +wire ropt_net_117 ; +wire ropt_net_121 ; +wire ropt_net_125 ; +wire ropt_net_124 ; +wire ropt_net_122 ; +wire ropt_net_115 ; +wire ropt_net_116 ; +wire ropt_net_126 ; +wire ropt_net_119 ; +wire ropt_net_123 ; +wire ropt_net_114 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; + +assign prog_clk_0 = prog_clk[0] ; + +cby_0__1__mux_tree_tapbuf_size12 mux_right_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_66 ) ) ; +cby_0__1__mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( right_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_bottom_in[27] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) , + .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_63__62 ( + .A ( right_width_0_height_0__pin_1_lower[0] ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_66 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_114 ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1259 ( .A ( ropt_net_115 ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1260 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1261 ( .A ( ropt_net_117 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1262 ( .A ( ropt_net_118 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_119 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_121 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_123 ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1269 ( .A ( ropt_net_125 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_126 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[8] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v new file mode 100644 index 0000000..753d925 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v @@ -0,0 +1,1963 @@ +// +// +// +// +// +// +module cby_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +wire copt_net_115 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_115 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_118 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_115 ) , + .X ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_120 ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( mem_out[3] ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1__const1_14 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1__const1_13 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1__const1_12 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_11 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_10 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_9 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_84 ) ) ; +endmodule + + +module cby_1__1__const1_8 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_129 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( ccff_head[0] ) , + .X ( copt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( copt_net_111 ) , + .X ( copt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_112 ) , + .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( copt_net_117 ) , + .X ( copt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_123 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1366 ( .A ( ropt_net_130 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1367 ( .A ( ropt_net_128 ) , + .X ( ropt_net_130 ) ) ; +endmodule + + +module cby_1__1__const1_7 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_6 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_5 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_4 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +endmodule + + +module cby_1__1__const1_3 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module cby_1__1__const1_2 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_103 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +endmodule + + +module cby_1__1__const1_0 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , + left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , + left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , + left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , + left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in , + Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out , + Test_en_E_out , pReset_S_in , pReset_N_out , Reset_S_in , Reset_E_in , + Reset_W_in , Reset_N_out , Reset_W_out , Reset_E_out , prog_clk_0_W_in , + prog_clk_0_S_out , prog_clk_0_N_out , prog_clk_2_N_in , prog_clk_2_S_in , + prog_clk_2_S_out , prog_clk_2_N_out , prog_clk_3_S_in , prog_clk_3_N_in , + prog_clk_3_N_out , prog_clk_3_S_out , clk_2_N_in , clk_2_S_in , + clk_2_S_out , clk_2_N_out , clk_3_S_in , clk_3_N_in , clk_3_N_out , + clk_3_S_out ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input Test_en_S_in ; +input Test_en_E_in ; +input Test_en_W_in ; +output Test_en_N_out ; +output Test_en_W_out ; +output Test_en_E_out ; +input pReset_S_in ; +output pReset_N_out ; +input Reset_S_in ; +input Reset_E_in ; +input Reset_W_in ; +output Reset_N_out ; +output Reset_W_out ; +output Reset_E_out ; +input prog_clk_0_W_in ; +output prog_clk_0_S_out ; +output prog_clk_0_N_out ; +input prog_clk_2_N_in ; +input prog_clk_2_S_in ; +output prog_clk_2_S_out ; +output prog_clk_2_N_out ; +input prog_clk_3_S_in ; +input prog_clk_3_N_in ; +output prog_clk_3_N_out ; +output prog_clk_3_S_out ; +input clk_2_N_in ; +input clk_2_S_in ; +output clk_2_S_out ; +output clk_2_N_out ; +input clk_3_S_in ; +input clk_3_N_in ; +output clk_3_N_out ; +output clk_3_S_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; + +assign Test_en_S_in = Test_en_E_in ; +assign Test_en_W_in = Test_en_E_in ; +assign Reset_S_in = Reset_E_in ; +assign Reset_W_in = Reset_E_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_2_N_in = prog_clk_2_S_in ; +assign prog_clk_3_S_in = prog_clk_3_N_in ; +assign clk_2_N_in = clk_2_S_in ; +assign clk_3_S_in = clk_3_N_in ; + +cby_1__1__mux_tree_tapbuf_size12_0 mux_right_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_1 mux_right_ipin_2 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_2 mux_right_ipin_4 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_3 mux_right_ipin_6 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_4 mux_right_ipin_8 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_5 mux_right_ipin_10 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_6 mux_right_ipin_12 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , + chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , + chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , + chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[22] , + chany_bottom_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[24] , + chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , + chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] , + chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , + chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , + .X ( Test_en_E_out ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_E_in ) , .X ( net_net_94 ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_E_in ) , + .X ( Reset_E_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_1109 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_2110 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( ZBUF_4_f_0 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( aps_rename_509_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( prog_clk_3_S_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , + .X ( clk_2_S_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( aps_rename_511_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , + .X ( clk_3_S_out ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( Test_en_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( pReset_S_in ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( Reset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( Reset_W_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( clk_2_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_102 ) , + .Y ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_114 ( .A ( aps_rename_505_ ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_115 ( .A ( aps_rename_508_ ) , + .X ( prog_clk_2_S_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1347 ( .A ( ZBUF_4_f_0 ) , + .X ( prog_clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591249 ( .A ( ctsbuf_net_1109 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3641254 ( .A ( ctsbuf_net_2110 ) , + .X ( prog_clk_0_N_out ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v new file mode 100644 index 0000000..cc627a6 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v @@ -0,0 +1,2155 @@ +// +// +// +// +// +// +module cby_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_115 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_115 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_118 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_115 ) , + .X ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_120 ) , + .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( mem_out[3] ) , + .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_129 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( ccff_head[0] ) , + .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( copt_net_111 ) , + .X ( copt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_112 ) , + .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( copt_net_117 ) , + .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_123 ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1366 ( .A ( ropt_net_130 ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1367 ( .A ( ropt_net_128 ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_103 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , + left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , + left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , + left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , + left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in , + Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out , + Test_en_E_out , pReset_S_in , pReset_N_out , Reset_S_in , Reset_E_in , + Reset_W_in , Reset_N_out , Reset_W_out , Reset_E_out , prog_clk_0_W_in , + prog_clk_0_S_out , prog_clk_0_N_out , prog_clk_2_N_in , prog_clk_2_S_in , + prog_clk_2_S_out , prog_clk_2_N_out , prog_clk_3_S_in , prog_clk_3_N_in , + prog_clk_3_N_out , prog_clk_3_S_out , clk_2_N_in , clk_2_S_in , + clk_2_S_out , clk_2_N_out , clk_3_S_in , clk_3_N_in , clk_3_N_out , + clk_3_S_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input Test_en_S_in ; +input Test_en_E_in ; +input Test_en_W_in ; +output Test_en_N_out ; +output Test_en_W_out ; +output Test_en_E_out ; +input pReset_S_in ; +output pReset_N_out ; +input Reset_S_in ; +input Reset_E_in ; +input Reset_W_in ; +output Reset_N_out ; +output Reset_W_out ; +output Reset_E_out ; +input prog_clk_0_W_in ; +output prog_clk_0_S_out ; +output prog_clk_0_N_out ; +input prog_clk_2_N_in ; +input prog_clk_2_S_in ; +output prog_clk_2_S_out ; +output prog_clk_2_N_out ; +input prog_clk_3_S_in ; +input prog_clk_3_N_in ; +output prog_clk_3_N_out ; +output prog_clk_3_S_out ; +input clk_2_N_in ; +input clk_2_S_in ; +output clk_2_S_out ; +output clk_2_N_out ; +input clk_3_S_in ; +input clk_3_N_in ; +output clk_3_N_out ; +output clk_3_S_out ; +input VDD ; +input VSS ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign Test_en_S_in = Test_en_E_in ; +assign Test_en_W_in = Test_en_E_in ; +assign Reset_S_in = Reset_E_in ; +assign Reset_W_in = Reset_E_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_2_N_in = prog_clk_2_S_in ; +assign prog_clk_3_S_in = prog_clk_3_N_in ; +assign clk_2_N_in = clk_2_S_in ; +assign clk_3_S_in = clk_3_N_in ; + +cby_1__1__mux_tree_tapbuf_size12_0 mux_right_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_1 mux_right_ipin_2 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_2 mux_right_ipin_4 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_3 mux_right_ipin_6 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_4 mux_right_ipin_8 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_5 mux_right_ipin_10 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_6 mux_right_ipin_12 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , + chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , + chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , + chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[22] , + chany_bottom_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[24] , + chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , + chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] , + chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , + chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , + .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , + .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , + .X ( Test_en_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) , + .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_E_in ) , .X ( net_net_94 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_E_in ) , + .X ( Reset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_1109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_2110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( ZBUF_4_f_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( prog_clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , + .X ( clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , + .X ( clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( Test_en_W_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( pReset_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( pReset_S_in ) , .Y ( BUF_net_91 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( Reset_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( Reset_W_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( clk_2_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( clk_3_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_102 ) , + .Y ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_114 ( .A ( aps_rename_505_ ) , + .X ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_115 ( .A ( aps_rename_508_ ) , + .X ( prog_clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1347 ( .A ( ZBUF_4_f_0 ) , + .X ( prog_clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591249 ( .A ( ctsbuf_net_1109 ) , + .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3641254 ( .A ( ctsbuf_net_2110 ) , + .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v new file mode 100644 index 0000000..f2a1f64 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v @@ -0,0 +1,1787 @@ +// +// +// +// +// +// +module cby_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +wire copt_net_115 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_115 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_118 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_115 ) , + .X ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_120 ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( mem_out[3] ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_84 ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_129 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( ccff_head[0] ) , + .X ( copt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( copt_net_111 ) , + .X ( copt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_112 ) , + .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( copt_net_117 ) , + .X ( copt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_123 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1366 ( .A ( ropt_net_130 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1367 ( .A ( ropt_net_128 ) , + .X ( ropt_net_130 ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_103 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , + left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , + left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , + left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , + left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in , + Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out , + Test_en_E_out , pReset_S_in , pReset_N_out , Reset_S_in , Reset_E_in , + Reset_W_in , Reset_N_out , Reset_W_out , Reset_E_out , prog_clk_0_W_in , + prog_clk_0_S_out , prog_clk_0_N_out , prog_clk_2_N_in , prog_clk_2_S_in , + prog_clk_2_S_out , prog_clk_2_N_out , prog_clk_3_S_in , prog_clk_3_N_in , + prog_clk_3_N_out , prog_clk_3_S_out , clk_2_N_in , clk_2_S_in , + clk_2_S_out , clk_2_N_out , clk_3_S_in , clk_3_N_in , clk_3_N_out , + clk_3_S_out ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input Test_en_S_in ; +input Test_en_E_in ; +input Test_en_W_in ; +output Test_en_N_out ; +output Test_en_W_out ; +output Test_en_E_out ; +input pReset_S_in ; +output pReset_N_out ; +input Reset_S_in ; +input Reset_E_in ; +input Reset_W_in ; +output Reset_N_out ; +output Reset_W_out ; +output Reset_E_out ; +input prog_clk_0_W_in ; +output prog_clk_0_S_out ; +output prog_clk_0_N_out ; +input prog_clk_2_N_in ; +input prog_clk_2_S_in ; +output prog_clk_2_S_out ; +output prog_clk_2_N_out ; +input prog_clk_3_S_in ; +input prog_clk_3_N_in ; +output prog_clk_3_N_out ; +output prog_clk_3_S_out ; +input clk_2_N_in ; +input clk_2_S_in ; +output clk_2_S_out ; +output clk_2_N_out ; +input clk_3_S_in ; +input clk_3_N_in ; +output clk_3_N_out ; +output clk_3_S_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; + +assign Test_en_E_in = Test_en_S_in ; +assign Test_en_E_in = Test_en_W_in ; +assign Reset_E_in = Reset_S_in ; +assign Reset_E_in = Reset_W_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_2_S_in = prog_clk_2_N_in ; +assign prog_clk_3_N_in = prog_clk_3_S_in ; +assign clk_2_S_in = clk_2_N_in ; +assign clk_3_N_in = clk_3_S_in ; + +cby_1__1__mux_tree_tapbuf_size12_0 mux_right_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_1 mux_right_ipin_2 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_2 mux_right_ipin_4 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_3 mux_right_ipin_6 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_4 mux_right_ipin_8 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_5 mux_right_ipin_10 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_6 mux_right_ipin_12 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , + chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , + chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , + chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[22] , + chany_bottom_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[24] , + chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , + chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] , + chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , + chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , + .X ( Test_en_E_out ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_E_in ) , .X ( net_net_94 ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_E_in ) , + .X ( Reset_E_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_1109 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_2110 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( ZBUF_4_f_0 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( aps_rename_509_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( prog_clk_3_S_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , + .X ( clk_2_S_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( aps_rename_511_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , + .X ( clk_3_S_out ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( Test_en_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( pReset_S_in ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( Reset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( Reset_W_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( clk_2_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_102 ) , + .Y ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_114 ( .A ( aps_rename_505_ ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_115 ( .A ( aps_rename_508_ ) , + .X ( prog_clk_2_S_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1347 ( .A ( ZBUF_4_f_0 ) , + .X ( prog_clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591249 ( .A ( ctsbuf_net_1109 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3641254 ( .A ( ctsbuf_net_2110 ) , + .X ( prog_clk_0_N_out ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..7e1ca27 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_1__1__icv_in_design.top_only.pt.v @@ -0,0 +1,538 @@ +// +// +// +// +// +// +module cby_1__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , + left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , + left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , + left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , + left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in , + Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out , + Test_en_E_out , pReset_S_in , pReset_N_out , Reset_S_in , Reset_E_in , + Reset_W_in , Reset_N_out , Reset_W_out , Reset_E_out , prog_clk_0_W_in , + prog_clk_0_S_out , prog_clk_0_N_out , prog_clk_2_N_in , prog_clk_2_S_in , + prog_clk_2_S_out , prog_clk_2_N_out , prog_clk_3_S_in , prog_clk_3_N_in , + prog_clk_3_N_out , prog_clk_3_S_out , clk_2_N_in , clk_2_S_in , + clk_2_S_out , clk_2_N_out , clk_3_S_in , clk_3_N_in , clk_3_N_out , + clk_3_S_out ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input Test_en_S_in ; +input Test_en_E_in ; +input Test_en_W_in ; +output Test_en_N_out ; +output Test_en_W_out ; +output Test_en_E_out ; +input pReset_S_in ; +output pReset_N_out ; +input Reset_S_in ; +input Reset_E_in ; +input Reset_W_in ; +output Reset_N_out ; +output Reset_W_out ; +output Reset_E_out ; +input prog_clk_0_W_in ; +output prog_clk_0_S_out ; +output prog_clk_0_N_out ; +input prog_clk_2_N_in ; +input prog_clk_2_S_in ; +output prog_clk_2_S_out ; +output prog_clk_2_N_out ; +input prog_clk_3_S_in ; +input prog_clk_3_N_in ; +output prog_clk_3_N_out ; +output prog_clk_3_S_out ; +input clk_2_N_in ; +input clk_2_S_in ; +output clk_2_S_out ; +output clk_2_N_out ; +input clk_3_S_in ; +input clk_3_N_in ; +output clk_3_N_out ; +output clk_3_S_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; + +assign Test_en_E_in = Test_en_S_in ; +assign Test_en_E_in = Test_en_W_in ; +assign Reset_E_in = Reset_S_in ; +assign Reset_E_in = Reset_W_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_2_S_in = prog_clk_2_N_in ; +assign prog_clk_3_N_in = prog_clk_3_S_in ; +assign clk_2_S_in = clk_2_N_in ; +assign clk_3_N_in = clk_3_S_in ; + +cby_1__1__mux_tree_tapbuf_size12_0 mux_right_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_1 mux_right_ipin_2 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_2 mux_right_ipin_4 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_3 mux_right_ipin_6 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_4 mux_right_ipin_8 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_5 mux_right_ipin_10 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_6 mux_right_ipin_12 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , + chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , + chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , + chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[22] , + chany_bottom_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[24] , + chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , + chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] , + chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , + chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , + .X ( Test_en_E_out ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_E_in ) , .X ( net_net_94 ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_E_in ) , + .X ( Reset_E_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_1109 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_2110 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( ZBUF_4_f_0 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( aps_rename_509_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( prog_clk_3_S_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , + .X ( clk_2_S_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( aps_rename_511_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , + .X ( clk_3_S_out ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( Test_en_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( pReset_S_in ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( Reset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( Reset_W_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( clk_2_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_102 ) , + .Y ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_114 ( .A ( aps_rename_505_ ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_115 ( .A ( aps_rename_508_ ) , + .X ( prog_clk_2_S_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1347 ( .A ( ZBUF_4_f_0 ) , + .X ( prog_clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591249 ( .A ( ctsbuf_net_1109 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3641254 ( .A ( ctsbuf_net_2110 ) , + .X ( prog_clk_0_N_out ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v new file mode 100644 index 0000000..5c5db51 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v @@ -0,0 +1,2091 @@ +// +// +// +// +// +// +module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_102 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_102 ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_105 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_107 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_102 ) , + .X ( copt_net_107 ) ) ; +endmodule + + +module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_79 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_81 ) ) ; +endmodule + + +module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_15 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_14 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_13 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_88 ) ) ; +endmodule + + +module cby_2__1__const1_12 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_11 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_10 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_2__1__const1_9 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_110 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ropt_net_113 ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1331 ( .A ( copt_net_99 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( ropt_net_111 ) , + .X ( copt_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_96 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_97 ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1343 ( .A ( copt_net_98 ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_112 ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( copt_net_100 ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1346 ( .A ( copt_net_95 ) , + .X ( ropt_net_113 ) ) ; +endmodule + + +module cby_2__1__const1_8 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_7 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_6 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_5 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) ) ; +endmodule + + +module cby_2__1__const1_4 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_3 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_2 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_83 ) ) ; +endmodule + + +module cby_2__1__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_0 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , + left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , + left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , + left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , + left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , + left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , + IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , + left_width_0_height_0__pin_1_lower , pReset_S_in , prog_clk_0_W_in , + prog_clk_0_S_out , prog_clk_0_N_out ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] right_grid_pin_0_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] left_width_0_height_0__pin_0_ ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; +input pReset_S_in ; +input prog_clk_0_W_in ; +output prog_clk_0_S_out ; +output prog_clk_0_N_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +cby_2__1__mux_tree_tapbuf_size12_0 mux_left_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , + chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_89 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , + chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_89 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_7 mem_right_ipin_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , + chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , + chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[21] , + chany_bottom_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[23] , + chany_bottom_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , + chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , + chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , + chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , + chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , + chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( { ropt_net_108 } ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_193 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_294 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( left_width_0_height_0__pin_1_lower[0] ) , + .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1342 ( .A ( ropt_net_108 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591231 ( .A ( ctsbuf_net_193 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__clkbuf_8 cts_buf_3641236 ( .A ( ctsbuf_net_294 ) , + .X ( prog_clk_0_N_out ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v new file mode 100644 index 0000000..54c93cb --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v @@ -0,0 +1,2320 @@ +// +// +// +// +// +// +module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_102 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_102 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_105 ) , + .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_107 ) , + .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_102 ) , + .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_79 ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_110 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ropt_net_113 ) , + .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1331 ( .A ( copt_net_99 ) , + .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( ropt_net_111 ) , + .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_96 ) , + .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_97 ) , + .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1343 ( .A ( copt_net_98 ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_112 ) , + .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( copt_net_100 ) , + .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1346 ( .A ( copt_net_95 ) , + .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , + left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , + left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , + left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , + left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , + left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , + IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , + left_width_0_height_0__pin_1_lower , pReset_S_in , prog_clk_0_W_in , + prog_clk_0_S_out , prog_clk_0_N_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] right_grid_pin_0_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] left_width_0_height_0__pin_0_ ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; +input pReset_S_in ; +input prog_clk_0_W_in ; +output prog_clk_0_S_out ; +output prog_clk_0_N_out ; +input VDD ; +input VSS ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +cby_2__1__mux_tree_tapbuf_size12_0 mux_left_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , + chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_89 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , + chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_89 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_7 mem_right_ipin_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , + chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , + chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[21] , + chany_bottom_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[23] , + chany_bottom_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , + chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , + chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , + chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , + chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , + chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( { ropt_net_108 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_294 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( left_width_0_height_0__pin_1_lower[0] ) , + .X ( left_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1342 ( .A ( ropt_net_108 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591231 ( .A ( ctsbuf_net_193 ) , + .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_8 cts_buf_3641236 ( .A ( ctsbuf_net_294 ) , + .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v new file mode 100644 index 0000000..4286ddf --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v @@ -0,0 +1,1904 @@ +// +// +// +// +// +// +module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_102 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_102 ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_105 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_107 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_102 ) , + .X ( copt_net_107 ) ) ; +endmodule + + +module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_79 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_81 ) ) ; +endmodule + + +module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_88 ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_110 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ropt_net_113 ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1331 ( .A ( copt_net_99 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( ropt_net_111 ) , + .X ( copt_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_96 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_97 ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1343 ( .A ( copt_net_98 ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_112 ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( copt_net_100 ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1346 ( .A ( copt_net_95 ) , + .X ( ropt_net_113 ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_83 ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , + left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , + left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , + left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , + left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , + left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , + IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , + left_width_0_height_0__pin_1_lower , pReset_S_in , prog_clk_0_W_in , + prog_clk_0_S_out , prog_clk_0_N_out ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] right_grid_pin_0_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] left_width_0_height_0__pin_0_ ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; +input pReset_S_in ; +input prog_clk_0_W_in ; +output prog_clk_0_S_out ; +output prog_clk_0_N_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +cby_2__1__mux_tree_tapbuf_size12_0 mux_left_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , + chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_89 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , + chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_89 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_7 mem_right_ipin_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , + chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , + chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[21] , + chany_bottom_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[23] , + chany_bottom_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , + chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , + chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , + chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , + chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , + chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( { ropt_net_108 } ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_193 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_294 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( left_width_0_height_0__pin_1_lower[0] ) , + .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1342 ( .A ( ropt_net_108 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591231 ( .A ( ctsbuf_net_193 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__clkbuf_8 cts_buf_3641236 ( .A ( ctsbuf_net_294 ) , + .X ( prog_clk_0_N_out ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..04cf336 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/cby_2__1__icv_in_design.top_only.pt.v @@ -0,0 +1,485 @@ +// +// +// +// +// +// +module cby_2__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , + left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , + left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , + left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , + left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , + left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , + IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , + left_width_0_height_0__pin_1_lower , pReset_S_in , prog_clk_0_W_in , + prog_clk_0_S_out , prog_clk_0_N_out ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] right_grid_pin_0_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] left_width_0_height_0__pin_0_ ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; +input pReset_S_in ; +input prog_clk_0_W_in ; +output prog_clk_0_S_out ; +output prog_clk_0_N_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +cby_2__1__mux_tree_tapbuf_size12_0 mux_left_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , + chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_89 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , + chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_89 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_7 mem_right_ipin_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , + chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , + chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[21] , + chany_bottom_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[23] , + chany_bottom_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , + chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , + chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , + chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , + chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , + chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( { ropt_net_108 } ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_193 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_294 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( left_width_0_height_0__pin_1_lower[0] ) , + .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1342 ( .A ( ropt_net_108 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591231 ( .A ( ctsbuf_net_193 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__clkbuf_8 cts_buf_3641236 ( .A ( ctsbuf_net_294 ) , + .X ( prog_clk_0_N_out ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v new file mode 100644 index 0000000..666c456 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v @@ -0,0 +1,2303 @@ +// +// +// +// +// +// +module sb_0__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__0__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_33 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__0__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_32 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__0__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__const1_31 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__0__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_30 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__0__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_89 ) ) ; +endmodule + + +module sb_0__0__const1_29 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__0__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_87 ) ) ; +endmodule + + +module sb_0__0__const1_28 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__0__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_91 ) ) ; +endmodule + + +module sb_0__0__const1_27 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__0__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_85 ) ) ; +endmodule + + +module sb_0__0__const1_26 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__0__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( copt_net_108 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1272 ( .A ( mem_out[1] ) , + .X ( copt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1273 ( .A ( copt_net_106 ) , + .X ( copt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1274 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_191 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( ccff_head[0] ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_103 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_100 ) , + .X ( copt_net_103 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_102 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1355 ( .A ( copt_net_104 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1356 ( .A ( ropt_net_189 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_190 ) , + .X ( ropt_net_191 ) ) ; +endmodule + + +module sb_0__0__const1_25 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_24 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_23 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_22 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_21 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_20 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_19 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_18 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_17 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module sb_0__0__const1_16 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) ) ; +endmodule + + +module sb_0__0__const1_15 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_14 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_13 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) ) ; +endmodule + + +module sb_0__0__const1_12 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_11 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_10 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_9 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_8 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_7 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_6 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_5 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_69 ) ) ; +endmodule + + +module sb_0__0__const1_4 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_67 ) ) ; +endmodule + + +module sb_0__0__const1_3 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_2 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_65 ) ) ; +endmodule + + +module sb_0__0__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_63 ) ) ; +endmodule + + +module sb_0__0__const1_0 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_61 ) ) ; +endmodule + + +module sb_0__0_ ( pReset , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , + right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , + right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , + right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ , + right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , + ccff_tail , pReset_E_in , prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; +input [0:0] right_bottom_grid_pin_13_ ; +input [0:0] right_bottom_grid_pin_15_ ; +input [0:0] right_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:0] ccff_tail ; +input pReset_E_in ; +input prog_clk_0_E_in ; + +wire ropt_net_141 ; +wire ropt_net_133 ; +wire ropt_net_134 ; +wire ropt_net_135 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_28 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_4 mux_top_track_44 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_20 ( + .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_22 ( + .in ( { chany_top_in[10] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_30 ( + .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_32 ( + .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_34 ( + .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_36 ( + .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_38 ( + .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_17 mux_right_track_40 ( + .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_18 mux_right_track_42 ( + .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_19 mux_right_track_46 ( + .in ( { chany_top_in[22] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_20 mux_right_track_48 ( + .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_21 mux_right_track_50 ( + .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_22 mux_right_track_52 ( + .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_23 mux_right_track_54 ( + .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_24 mux_right_track_56 ( + .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2 mux_right_track_58 ( + .in ( { chany_top_in[28] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_24 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_30 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_32 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_34 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_36 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_38 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_17 mem_right_track_40 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_18 mem_right_track_42 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_19 mem_right_track_46 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_20 mem_right_track_48 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_21 mem_right_track_50 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_22 mem_right_track_52 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_23 mem_right_track_54 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_24 mem_right_track_56 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_58 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { chany_top_in[29] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_3 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size3_1 mux_right_track_28 ( + .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size3 mux_right_track_44 ( + .in ( { chany_top_in[21] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem_1 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[3] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[6] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[11] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[14] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[17] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[20] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[21] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[22] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[24] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_right_in[25] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[26] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[27] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[28] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1307 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[1] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v new file mode 100644 index 0000000..c12cc95 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v @@ -0,0 +1,2492 @@ +// +// +// +// +// +// +module sb_0__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( copt_net_108 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1272 ( .A ( mem_out[1] ) , + .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1273 ( .A ( copt_net_106 ) , + .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1274 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_191 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( ccff_head[0] ) , + .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_103 ) , + .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_100 ) , + .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_102 ) , + .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1355 ( .A ( copt_net_104 ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1356 ( .A ( ropt_net_189 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_190 ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0_ ( pReset , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , + right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , + right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , + right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ , + right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , + ccff_tail , pReset_E_in , prog_clk_0_E_in , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; +input [0:0] right_bottom_grid_pin_13_ ; +input [0:0] right_bottom_grid_pin_15_ ; +input [0:0] right_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:0] ccff_tail ; +input pReset_E_in ; +input prog_clk_0_E_in ; +input VDD ; +input VSS ; + +wire ropt_net_141 ; +wire ropt_net_133 ; +wire ropt_net_134 ; +wire ropt_net_135 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_28 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_4 mux_top_track_44 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , + .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_20 ( + .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_22 ( + .in ( { chany_top_in[10] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_30 ( + .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , + .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_32 ( + .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_34 ( + .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_36 ( + .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_38 ( + .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_17 mux_right_track_40 ( + .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_18 mux_right_track_42 ( + .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chanx_right_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_19 mux_right_track_46 ( + .in ( { chany_top_in[22] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chanx_right_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_20 mux_right_track_48 ( + .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_21 mux_right_track_50 ( + .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_22 mux_right_track_52 ( + .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_23 mux_right_track_54 ( + .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_24 mux_right_track_56 ( + .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chanx_right_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2 mux_right_track_58 ( + .in ( { chany_top_in[28] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_24 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_30 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_32 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_34 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_36 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_38 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_17 mem_right_track_40 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_18 mem_right_track_42 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_19 mem_right_track_46 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_20 mem_right_track_48 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_21 mem_right_track_50 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_22 mem_right_track_52 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_23 mem_right_track_54 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_24 mem_right_track_56 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_58 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_25_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { chany_top_in[29] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_3 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size3_1 mux_right_track_28 ( + .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size3 mux_right_track_44 ( + .in ( { chany_top_in[21] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem_1 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[3] ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[6] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[11] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[14] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[17] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[20] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[21] ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[22] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[24] ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_right_in[25] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[26] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[27] ) , + .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[28] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1307 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v new file mode 100644 index 0000000..66f3fa2 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v @@ -0,0 +1,1918 @@ +// +// +// +// +// +// +module sb_0__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_89 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_87 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_91 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_85 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( copt_net_108 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1272 ( .A ( mem_out[1] ) , + .X ( copt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1273 ( .A ( copt_net_106 ) , + .X ( copt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1274 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_191 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( ccff_head[0] ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_103 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_100 ) , + .X ( copt_net_103 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_102 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1355 ( .A ( copt_net_104 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1356 ( .A ( ropt_net_189 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_190 ) , + .X ( ropt_net_191 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_69 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_67 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_65 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_63 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_61 ) ) ; +endmodule + + +module sb_0__0_ ( pReset , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , + right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , + right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , + right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ , + right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , + ccff_tail , pReset_E_in , prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; +input [0:0] right_bottom_grid_pin_13_ ; +input [0:0] right_bottom_grid_pin_15_ ; +input [0:0] right_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:0] ccff_tail ; +input pReset_E_in ; +input prog_clk_0_E_in ; + +wire ropt_net_141 ; +wire ropt_net_133 ; +wire ropt_net_134 ; +wire ropt_net_135 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_28 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_4 mux_top_track_44 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_20 ( + .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_22 ( + .in ( { chany_top_in[10] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_30 ( + .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_32 ( + .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_34 ( + .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_36 ( + .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_38 ( + .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_17 mux_right_track_40 ( + .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_18 mux_right_track_42 ( + .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_19 mux_right_track_46 ( + .in ( { chany_top_in[22] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_20 mux_right_track_48 ( + .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_21 mux_right_track_50 ( + .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_22 mux_right_track_52 ( + .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_23 mux_right_track_54 ( + .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_24 mux_right_track_56 ( + .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2 mux_right_track_58 ( + .in ( { chany_top_in[28] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_24 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_30 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_32 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_34 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_36 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_38 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_17 mem_right_track_40 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_18 mem_right_track_42 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_19 mem_right_track_46 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_20 mem_right_track_48 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_21 mem_right_track_50 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_22 mem_right_track_52 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_23 mem_right_track_54 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_24 mem_right_track_56 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_58 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { chany_top_in[29] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_3 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size3_1 mux_right_track_28 ( + .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size3 mux_right_track_44 ( + .in ( { chany_top_in[21] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem_1 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[3] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[6] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[11] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[14] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[17] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[20] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[21] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[22] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[24] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_right_in[25] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[26] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[27] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[28] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1307 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[1] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..9030bd1 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__0__icv_in_design.top_only.pt.v @@ -0,0 +1,548 @@ +// +// +// +// +// +// +module sb_0__0_ ( pReset , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , + right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , + right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , + right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ , + right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , + ccff_tail , pReset_E_in , prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; +input [0:0] right_bottom_grid_pin_13_ ; +input [0:0] right_bottom_grid_pin_15_ ; +input [0:0] right_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:0] ccff_tail ; +input pReset_E_in ; +input prog_clk_0_E_in ; + +wire ropt_net_141 ; +wire ropt_net_133 ; +wire ropt_net_134 ; +wire ropt_net_135 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_28 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_4 mux_top_track_44 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_20 ( + .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_22 ( + .in ( { chany_top_in[10] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_30 ( + .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_32 ( + .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_34 ( + .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_36 ( + .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_38 ( + .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_17 mux_right_track_40 ( + .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_18 mux_right_track_42 ( + .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_96 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_19 mux_right_track_46 ( + .in ( { chany_top_in[22] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_20 mux_right_track_48 ( + .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_21 mux_right_track_50 ( + .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_95 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_22 mux_right_track_52 ( + .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_23 mux_right_track_54 ( + .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_24 mux_right_track_56 ( + .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2 mux_right_track_58 ( + .in ( { chany_top_in[28] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_94 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_24 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_30 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_32 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_34 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_36 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_38 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_17 mem_right_track_40 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_18 mem_right_track_42 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_19 mem_right_track_46 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_20 mem_right_track_48 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_21 mem_right_track_50 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_22 mem_right_track_52 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_23 mem_right_track_54 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_24 mem_right_track_56 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_58 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { chany_top_in[29] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_3 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size3_1 mux_right_track_28 ( + .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size3 mux_right_track_44 ( + .in ( { chany_top_in[21] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem_1 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[3] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[6] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[11] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[14] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[17] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[20] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[21] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[22] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[24] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_right_in[25] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[26] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[27] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[28] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1307 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[1] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v new file mode 100644 index 0000000..c169918 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v @@ -0,0 +1,3690 @@ +// +// +// +// +// +// +module sb_0__1__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_142 ) ) ; +endmodule + + +module sb_0__1__const1_48 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1_48 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_140 ) ) ; +endmodule + + +module sb_0__1__const1_47 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1_47 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_138 ) ) ; +endmodule + + +module sb_0__1__const1_46 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1_46 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_45 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1_45 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_44 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1_44 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_43 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_42 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_136 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +wire copt_net_160 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_160 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( copt_net_160 ) , + .X ( mem_out[1] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__const1_41 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_134 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_40 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_133 ) ) ; +endmodule + + +module sb_0__1__const1_39 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_131 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_38 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_130 ) ) ; +endmodule + + +module sb_0__1__const1_37 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_36 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_128 ) ) ; +endmodule + + +module sb_0__1__const1_35 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_34 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_126 ) ) ; +endmodule + + +module sb_0__1__const1_33 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_32 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_124 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__const1_31 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_30 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_122 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_29 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_121 ) ) ; +endmodule + + +module sb_0__1__const1_28 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module sb_0__1__const1_27 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_26 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_116 ) ) ; +endmodule + + +module sb_0__1__const1_25 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_24 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_23 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) ) ; +endmodule + + +module sb_0__1__const1_22 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_111 ) ) ; +endmodule + + +module sb_0__1__const1_21 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_109 ) ) ; +endmodule + + +module sb_0__1__const1_20 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__const1_19 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_107 ) ) ; +endmodule + + +module sb_0__1__const1_18 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_17 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) ) ; +endmodule + + +module sb_0__1__const1_16 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_15 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_14 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_102 ) ) ; +endmodule + + +module sb_0__1__const1_13 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_100 ) ) ; +endmodule + + +module sb_0__1__const1_12 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_11 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_98 ) ) ; +endmodule + + +module sb_0__1__const1_10 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_9 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_8 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_168 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( ropt_net_172 ) , + .X ( copt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_149 ) , + .X ( copt_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( ropt_net_170 ) , + .X ( copt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_153 ) , + .X ( copt_net_152 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_150 ) , + .X ( copt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( ccff_head[0] ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1340 ( .A ( copt_net_151 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1341 ( .A ( ropt_net_166 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1342 ( .A ( ropt_net_167 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( copt_net_152 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_171 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__buf_4 ropt_h_inst_1345 ( .A ( ropt_net_169 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1346 ( .A ( copt_net_154 ) , + .X ( ropt_net_172 ) ) ; +endmodule + + +module sb_0__1__const1_7 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_6 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_5 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_4 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_96 ) ) ; +endmodule + + +module sb_0__1__const1_3 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_0__1__const1_2 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_0__1__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_0 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_90 ) ) ; +endmodule + + +module sb_0__1_ ( pReset , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , ccff_tail , pReset_E_in , pReset_S_out , + prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:0] ccff_tail ; +input pReset_E_in ; +output pReset_S_out ; +input prog_clk_0_E_in ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:1] mux_tree_tapbuf_size3_8_sram ; +wire [0:1] mux_tree_tapbuf_size3_9_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_10_sram ; +wire [0:2] mux_tree_tapbuf_size5_11_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:2] mux_tree_tapbuf_size5_6_sram ; +wire [0:2] mux_tree_tapbuf_size5_7_sram ; +wire [0:2] mux_tree_tapbuf_size5_8_sram ; +wire [0:2] mux_tree_tapbuf_size5_9_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_9_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_7_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[12] , + chanx_right_in[23] , chany_top_out[4] , chany_top_out[20] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] , + chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] , + chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_bottom_out[7] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_bottom_out[9] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_top_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 ( + .in ( { chany_top_in[4] , chany_bottom_out[11] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_6 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] , + chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] , + chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( + .in ( { chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] , + chany_top_out[7] , chany_top_out[21] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_4 ( + .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] , + chany_top_out[8] , chany_top_out[23] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_2 mux_top_track_10 ( + .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] , + chany_top_out[11] , chany_top_out[25] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_20 ( + .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] , + chany_top_out[13] , chany_top_out[28] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 ( + .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , + chany_top_out[4] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_bottom_out[8] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 ( + .in ( { chany_top_in[5] , chany_bottom_out[12] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[12] } ) , + .sram ( mux_tree_tapbuf_size5_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , + SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_7 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] , + chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size5_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_8 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_right_in[7] , + chanx_right_in[18] , chanx_right_in[29] } ) , + .sram ( mux_tree_tapbuf_size5_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_9 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] , + chanx_right_in[16] , chanx_right_in[27] } ) , + .sram ( mux_tree_tapbuf_size5_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_10 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] , + chanx_right_in[14] , chanx_right_in[25] } ) , + .sram ( mux_tree_tapbuf_size5_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , + SYNOPSYS_UNCONNECTED_57 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , + chanx_right_in[13] , chanx_right_in[24] } ) , + .sram ( mux_tree_tapbuf_size5_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , + SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_4 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_5 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_6 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_7 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_8 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_9 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_10 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_10_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_11_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_28 ( + .in ( { chanx_right_in[8] , chanx_right_in[19] , chany_top_out[15] , + chany_top_out[29] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_52 ( + .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] , + chany_top_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , + SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_12 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , + right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , + SYNOPSYS_UNCONNECTED_69 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_14 ( + .in ( { chany_top_in[13] , chany_bottom_out[15] , + right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , + SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_16 ( + .in ( { chany_bottom_out[16] , chany_top_in[17] , + right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_18 ( + .in ( { chany_bottom_out[17] , chany_top_in[21] , + right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , + SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_6 mux_right_track_20 ( + .in ( { chany_bottom_out[19] , chany_top_in[25] , + right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , + SYNOPSYS_UNCONNECTED_81 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_7 mux_right_track_22 ( + .in ( { chany_bottom_out[20] , chany_top_in[29] , + right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , + SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_8 mux_right_track_36 ( + .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] , + chany_top_out[29] , chany_bottom_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , + SYNOPSYS_UNCONNECTED_87 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_9 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 , + SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_10 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] , + chanx_right_in[23] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 , + SYNOPSYS_UNCONNECTED_93 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size4 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] , + chanx_right_in[22] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , + SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_6 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_7 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_8 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_9 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_10 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem mem_bottom_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_0 mux_top_track_36 ( + .in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_1 mux_top_track_44 ( + .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_24 ( + .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] , + chany_top_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_26 ( + .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] , + chany_top_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_4 mux_right_track_28 ( + .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , + chany_top_out[24] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_5 mux_right_track_30 ( + .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , + chany_top_out[25] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_6 mux_right_track_32 ( + .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] , + chany_top_out[27] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_7 mux_right_track_34 ( + .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] , + chany_top_out[28] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_8 mux_right_track_50 ( + .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size3_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) , + .sram ( mux_tree_tapbuf_size3_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_5 mem_right_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_6 mem_right_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_7 mem_right_track_34 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_8 mem_right_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_40 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_44 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_46 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_48 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_5 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_6 mux_right_track_54 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2 mux_right_track_56 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_5 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_6 mem_right_track_54 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_56 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[17] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_148 ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v new file mode 100644 index 0000000..7a4256e --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v @@ -0,0 +1,4033 @@ +// +// +// +// +// +// +module sb_0__1__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_160 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_160 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( copt_net_160 ) , + .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_134 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_131 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_122 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_168 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( ropt_net_172 ) , + .X ( copt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_149 ) , + .X ( copt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( ropt_net_170 ) , + .X ( copt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_153 ) , + .X ( copt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_150 ) , + .X ( copt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( ccff_head[0] ) , + .X ( copt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1340 ( .A ( copt_net_151 ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1341 ( .A ( ropt_net_166 ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1342 ( .A ( ropt_net_167 ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( copt_net_152 ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_171 ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 ropt_h_inst_1345 ( .A ( ropt_net_169 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1346 ( .A ( copt_net_154 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1_ ( pReset , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , ccff_tail , pReset_E_in , pReset_S_out , + prog_clk_0_E_in , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:0] ccff_tail ; +input pReset_E_in ; +output pReset_S_out ; +input prog_clk_0_E_in ; +input VDD ; +input VSS ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:1] mux_tree_tapbuf_size3_8_sram ; +wire [0:1] mux_tree_tapbuf_size3_9_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_10_sram ; +wire [0:2] mux_tree_tapbuf_size5_11_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:2] mux_tree_tapbuf_size5_6_sram ; +wire [0:2] mux_tree_tapbuf_size5_7_sram ; +wire [0:2] mux_tree_tapbuf_size5_8_sram ; +wire [0:2] mux_tree_tapbuf_size5_9_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_9_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_7_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[12] , + chanx_right_in[23] , chany_top_out[4] , chany_top_out[20] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] , + chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] , + chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_bottom_out[7] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_bottom_out[9] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_top_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 ( + .in ( { chany_top_in[4] , chany_bottom_out[11] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_6 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] , + chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] , + chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( + .in ( { chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] , + chany_top_out[7] , chany_top_out[21] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_4 ( + .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] , + chany_top_out[8] , chany_top_out[23] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_2 mux_top_track_10 ( + .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] , + chany_top_out[11] , chany_top_out[25] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_20 ( + .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] , + chany_top_out[13] , chany_top_out[28] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 ( + .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , + chany_top_out[4] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_bottom_out[8] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 ( + .in ( { chany_top_in[5] , chany_bottom_out[12] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[12] } ) , + .sram ( mux_tree_tapbuf_size5_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , + SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_7 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] , + chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size5_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_8 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_right_in[7] , + chanx_right_in[18] , chanx_right_in[29] } ) , + .sram ( mux_tree_tapbuf_size5_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_9 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] , + chanx_right_in[16] , chanx_right_in[27] } ) , + .sram ( mux_tree_tapbuf_size5_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_10 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] , + chanx_right_in[14] , chanx_right_in[25] } ) , + .sram ( mux_tree_tapbuf_size5_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , + SYNOPSYS_UNCONNECTED_57 } ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , + chanx_right_in[13] , chanx_right_in[24] } ) , + .sram ( mux_tree_tapbuf_size5_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , + SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_4 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_5 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_6 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_7 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_8 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_9 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_10 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_28 ( + .in ( { chanx_right_in[8] , chanx_right_in[19] , chany_top_out[15] , + chany_top_out[29] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 } ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_52 ( + .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] , + chany_top_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , + SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_12 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , + right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , + SYNOPSYS_UNCONNECTED_69 } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_14 ( + .in ( { chany_top_in[13] , chany_bottom_out[15] , + right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , + SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_16 ( + .in ( { chany_bottom_out[16] , chany_top_in[17] , + right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 } ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_18 ( + .in ( { chany_bottom_out[17] , chany_top_in[21] , + right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , + SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_6 mux_right_track_20 ( + .in ( { chany_bottom_out[19] , chany_top_in[25] , + right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , + SYNOPSYS_UNCONNECTED_81 } ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_7 mux_right_track_22 ( + .in ( { chany_bottom_out[20] , chany_top_in[29] , + right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , + SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_8 mux_right_track_36 ( + .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] , + chany_top_out[29] , chany_bottom_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , + SYNOPSYS_UNCONNECTED_87 } ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_9 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 , + SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_10 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] , + chanx_right_in[23] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 , + SYNOPSYS_UNCONNECTED_93 } ) , + .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size4 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] , + chanx_right_in[22] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , + SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_6 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_7 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_8 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_9 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_10 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem mem_bottom_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_0 mux_top_track_36 ( + .in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_1 mux_top_track_44 ( + .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_24 ( + .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] , + chany_top_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_26 ( + .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] , + chany_top_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_4 mux_right_track_28 ( + .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , + chany_top_out[24] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_5 mux_right_track_30 ( + .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , + chany_top_out[25] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_6 mux_right_track_32 ( + .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] , + chany_top_out[27] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_7 mux_right_track_34 ( + .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] , + chany_top_out[28] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_8 mux_right_track_50 ( + .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size3_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) , + .sram ( mux_tree_tapbuf_size3_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_5 mem_right_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_6 mem_right_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_7 mem_right_track_34 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_8 mem_right_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_9_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_40 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_44 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_46 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chanx_right_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_48 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_5 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_6 mux_right_track_54 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2 mux_right_track_56 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chanx_right_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_5 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_6 mem_right_track_54 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_56 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[17] ) , + .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , + .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v new file mode 100644 index 0000000..31c3022 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v @@ -0,0 +1,3140 @@ +// +// +// +// +// +// +module sb_0__1__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_142 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_140 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_138 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_136 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +wire copt_net_160 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_160 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( copt_net_160 ) , + .X ( mem_out[1] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_134 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_133 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_131 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_130 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_128 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_126 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_124 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_122 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_121 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_116 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_111 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_109 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_107 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_102 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_100 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_98 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_168 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( ropt_net_172 ) , + .X ( copt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_149 ) , + .X ( copt_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( ropt_net_170 ) , + .X ( copt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_153 ) , + .X ( copt_net_152 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_150 ) , + .X ( copt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( ccff_head[0] ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1340 ( .A ( copt_net_151 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1341 ( .A ( ropt_net_166 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1342 ( .A ( ropt_net_167 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( copt_net_152 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_171 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__buf_4 ropt_h_inst_1345 ( .A ( ropt_net_169 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1346 ( .A ( copt_net_154 ) , + .X ( ropt_net_172 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_96 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_90 ) ) ; +endmodule + + +module sb_0__1_ ( pReset , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , ccff_tail , pReset_E_in , pReset_S_out , + prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:0] ccff_tail ; +input pReset_E_in ; +output pReset_S_out ; +input prog_clk_0_E_in ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:1] mux_tree_tapbuf_size3_8_sram ; +wire [0:1] mux_tree_tapbuf_size3_9_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_10_sram ; +wire [0:2] mux_tree_tapbuf_size5_11_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:2] mux_tree_tapbuf_size5_6_sram ; +wire [0:2] mux_tree_tapbuf_size5_7_sram ; +wire [0:2] mux_tree_tapbuf_size5_8_sram ; +wire [0:2] mux_tree_tapbuf_size5_9_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_9_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_7_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[12] , + chanx_right_in[23] , chany_top_out[4] , chany_top_out[20] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] , + chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] , + chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_bottom_out[7] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_bottom_out[9] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_top_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 ( + .in ( { chany_top_in[4] , chany_bottom_out[11] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_6 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] , + chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] , + chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( + .in ( { chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] , + chany_top_out[7] , chany_top_out[21] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_4 ( + .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] , + chany_top_out[8] , chany_top_out[23] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_2 mux_top_track_10 ( + .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] , + chany_top_out[11] , chany_top_out[25] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_20 ( + .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] , + chany_top_out[13] , chany_top_out[28] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 ( + .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , + chany_top_out[4] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_bottom_out[8] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 ( + .in ( { chany_top_in[5] , chany_bottom_out[12] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[12] } ) , + .sram ( mux_tree_tapbuf_size5_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , + SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_7 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] , + chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size5_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_8 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_right_in[7] , + chanx_right_in[18] , chanx_right_in[29] } ) , + .sram ( mux_tree_tapbuf_size5_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_9 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] , + chanx_right_in[16] , chanx_right_in[27] } ) , + .sram ( mux_tree_tapbuf_size5_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_10 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] , + chanx_right_in[14] , chanx_right_in[25] } ) , + .sram ( mux_tree_tapbuf_size5_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , + SYNOPSYS_UNCONNECTED_57 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , + chanx_right_in[13] , chanx_right_in[24] } ) , + .sram ( mux_tree_tapbuf_size5_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , + SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_4 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_5 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_6 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_7 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_8 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_9 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_10 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_10_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_11_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_28 ( + .in ( { chanx_right_in[8] , chanx_right_in[19] , chany_top_out[15] , + chany_top_out[29] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_52 ( + .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] , + chany_top_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , + SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_12 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , + right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , + SYNOPSYS_UNCONNECTED_69 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_14 ( + .in ( { chany_top_in[13] , chany_bottom_out[15] , + right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , + SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_16 ( + .in ( { chany_bottom_out[16] , chany_top_in[17] , + right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_18 ( + .in ( { chany_bottom_out[17] , chany_top_in[21] , + right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , + SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_6 mux_right_track_20 ( + .in ( { chany_bottom_out[19] , chany_top_in[25] , + right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , + SYNOPSYS_UNCONNECTED_81 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_7 mux_right_track_22 ( + .in ( { chany_bottom_out[20] , chany_top_in[29] , + right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , + SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_8 mux_right_track_36 ( + .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] , + chany_top_out[29] , chany_bottom_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , + SYNOPSYS_UNCONNECTED_87 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_9 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 , + SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_10 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] , + chanx_right_in[23] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 , + SYNOPSYS_UNCONNECTED_93 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size4 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] , + chanx_right_in[22] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , + SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_6 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_7 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_8 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_9 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_10 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem mem_bottom_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_0 mux_top_track_36 ( + .in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_1 mux_top_track_44 ( + .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_24 ( + .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] , + chany_top_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_26 ( + .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] , + chany_top_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_4 mux_right_track_28 ( + .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , + chany_top_out[24] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_5 mux_right_track_30 ( + .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , + chany_top_out[25] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_6 mux_right_track_32 ( + .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] , + chany_top_out[27] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_7 mux_right_track_34 ( + .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] , + chany_top_out[28] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_8 mux_right_track_50 ( + .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size3_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) , + .sram ( mux_tree_tapbuf_size3_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_5 mem_right_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_6 mem_right_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_7 mem_right_track_34 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_8 mem_right_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_40 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_44 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_46 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_48 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_5 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_6 mux_right_track_54 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2 mux_right_track_56 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_5 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_6 mem_right_track_54 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_56 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[17] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_148 ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..83af4a5 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__1__icv_in_design.top_only.pt.v @@ -0,0 +1,814 @@ +// +// +// +// +// +// +module sb_0__1_ ( pReset , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , ccff_tail , pReset_E_in , pReset_S_out , + prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:0] ccff_tail ; +input pReset_E_in ; +output pReset_S_out ; +input prog_clk_0_E_in ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:1] mux_tree_tapbuf_size3_8_sram ; +wire [0:1] mux_tree_tapbuf_size3_9_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_10_sram ; +wire [0:2] mux_tree_tapbuf_size5_11_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:2] mux_tree_tapbuf_size5_6_sram ; +wire [0:2] mux_tree_tapbuf_size5_7_sram ; +wire [0:2] mux_tree_tapbuf_size5_8_sram ; +wire [0:2] mux_tree_tapbuf_size5_9_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_9_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_7_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[12] , + chanx_right_in[23] , chany_top_out[4] , chany_top_out[20] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] , + chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] , + chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_bottom_out[7] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_bottom_out[9] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_top_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 ( + .in ( { chany_top_in[4] , chany_bottom_out[11] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_6 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] , + chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] , + chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( + .in ( { chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] , + chany_top_out[7] , chany_top_out[21] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_4 ( + .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] , + chany_top_out[8] , chany_top_out[23] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_2 mux_top_track_10 ( + .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] , + chany_top_out[11] , chany_top_out[25] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_20 ( + .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] , + chany_top_out[13] , chany_top_out[28] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 ( + .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , + chany_top_out[4] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_bottom_out[8] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 ( + .in ( { chany_top_in[5] , chany_bottom_out[12] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[12] } ) , + .sram ( mux_tree_tapbuf_size5_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , + SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_7 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] , + chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size5_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_8 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_right_in[7] , + chanx_right_in[18] , chanx_right_in[29] } ) , + .sram ( mux_tree_tapbuf_size5_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_9 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] , + chanx_right_in[16] , chanx_right_in[27] } ) , + .sram ( mux_tree_tapbuf_size5_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_145 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_10 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] , + chanx_right_in[14] , chanx_right_in[25] } ) , + .sram ( mux_tree_tapbuf_size5_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , + SYNOPSYS_UNCONNECTED_57 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , + chanx_right_in[13] , chanx_right_in[24] } ) , + .sram ( mux_tree_tapbuf_size5_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , + SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_4 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_5 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_6 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_7 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_8 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_9 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_10 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_10_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_11_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_28 ( + .in ( { chanx_right_in[8] , chanx_right_in[19] , chany_top_out[15] , + chany_top_out[29] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_52 ( + .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] , + chany_top_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , + SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_12 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , + right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , + SYNOPSYS_UNCONNECTED_69 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_14 ( + .in ( { chany_top_in[13] , chany_bottom_out[15] , + right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , + SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_16 ( + .in ( { chany_bottom_out[16] , chany_top_in[17] , + right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_18 ( + .in ( { chany_bottom_out[17] , chany_top_in[21] , + right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , + SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_6 mux_right_track_20 ( + .in ( { chany_bottom_out[19] , chany_top_in[25] , + right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , + SYNOPSYS_UNCONNECTED_81 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_7 mux_right_track_22 ( + .in ( { chany_bottom_out[20] , chany_top_in[29] , + right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , + SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_8 mux_right_track_36 ( + .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] , + chany_top_out[29] , chany_bottom_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , + SYNOPSYS_UNCONNECTED_87 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_9 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 , + SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_10 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] , + chanx_right_in[23] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 , + SYNOPSYS_UNCONNECTED_93 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size4 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] , + chanx_right_in[22] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , + SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_6 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_7 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_8 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_9 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_10 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem mem_bottom_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_0 mux_top_track_36 ( + .in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_1 mux_top_track_44 ( + .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_24 ( + .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] , + chany_top_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_146 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_26 ( + .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] , + chany_top_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_4 mux_right_track_28 ( + .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , + chany_top_out[24] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_5 mux_right_track_30 ( + .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , + chany_top_out[25] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_148 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_6 mux_right_track_32 ( + .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] , + chany_top_out[27] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_147 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_7 mux_right_track_34 ( + .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] , + chany_top_out[28] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_144 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_8 mux_right_track_50 ( + .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size3_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) , + .sram ( mux_tree_tapbuf_size3_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_5 mem_right_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_6 mem_right_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_7 mem_right_track_34 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_8 mem_right_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_40 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_44 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_46 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_48 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_5 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_6 mux_right_track_54 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2 mux_right_track_56 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_143 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_5 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_6 mem_right_track_54 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_56 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[17] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_148 ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v new file mode 100644 index 0000000..198eb14 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v @@ -0,0 +1,2301 @@ +// +// +// +// +// +// +module sb_0__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__2__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_33 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__2__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +wire copt_net_103 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_103 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_103 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_100 ) , + .X ( mem_out[1] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__const1_32 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__const1_31 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) ) ; +endmodule + + +module sb_0__2__const1_30 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_29 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__const1_28 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module sb_0__2__const1_27 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_26 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_25 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_24 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_23 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_22 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) ) ; +endmodule + + +module sb_0__2__const1_21 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__const1_20 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_19 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__const1_18 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) ) ; +endmodule + + +module sb_0__2__const1_17 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_74 ) ) ; +endmodule + + +module sb_0__2__const1_16 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_15 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_14 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_13 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_12 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_11 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) ) ; +endmodule + + +module sb_0__2__const1_10 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) ) ; +endmodule + + +module sb_0__2__const1_9 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_8 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_7 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_6 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_190 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( copt_net_94 ) , + .X ( copt_net_92 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_92 ) , + .X ( copt_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , + .X ( copt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_93 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1351 ( .A ( copt_net_97 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1352 ( .A ( ropt_net_188 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1353 ( .A ( ropt_net_189 ) , + .X ( ropt_net_190 ) ) ; +endmodule + + +module sb_0__2__const1_5 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__2__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) ) ; +endmodule + + +module sb_0__2__const1_4 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__2__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) ) ; +endmodule + + +module sb_0__2__const1_3 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__2__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) ) ; +endmodule + + +module sb_0__2__const1_2 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__2__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__2__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_0 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__2__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + ccff_tail , SC_IN_TOP , SC_OUT_BOT , pReset_E_in , pReset_S_out , + prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input pReset_E_in ; +output pReset_S_out ; +input prog_clk_0_E_in ; + +wire ropt_net_129 ; +wire ropt_net_130 ; +wire ropt_net_131 ; +wire ropt_net_128 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__2__mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[28] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[27] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_3 mux_right_track_6 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size4 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[23] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_12 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_14 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_18 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_22 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_24 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_40 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_42 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_44 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_46 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_17 mux_right_track_48 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_18 mux_right_track_50 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_19 mux_right_track_54 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_20 mux_right_track_56 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_21 mux_right_track_58 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_22 mux_bottom_track_1 ( + .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_23 mux_bottom_track_7 ( + .in ( { chanx_right_in[25] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_24 mux_bottom_track_13 ( + .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_25 mux_bottom_track_29 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_45 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_36 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_38 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_40 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_42 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_44 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_46 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_17 mem_right_track_48 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_18 mem_right_track_50 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_19 mem_right_track_54 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_20 mem_right_track_56 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_21 mem_right_track_58 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_22 mem_bottom_track_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_23 mem_bottom_track_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_24 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_25 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_28 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size3 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_88 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[3] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[8] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[9] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[13] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[16] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[18] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[20] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[21] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[23] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( chanx_right_in[24] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[26] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[27] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( pReset_E_in ) , .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_129 ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[13] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v new file mode 100644 index 0000000..b1695aa --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v @@ -0,0 +1,2493 @@ +// +// +// +// +// +// +module sb_0__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_103 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_103 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_103 ) , + .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_100 ) , + .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_190 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( copt_net_94 ) , + .X ( copt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_92 ) , + .X ( copt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , + .X ( copt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , + .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_93 ) , + .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1351 ( .A ( copt_net_97 ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1352 ( .A ( ropt_net_188 ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1353 ( .A ( ropt_net_189 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + ccff_tail , SC_IN_TOP , SC_OUT_BOT , pReset_E_in , pReset_S_out , + prog_clk_0_E_in , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input pReset_E_in ; +output pReset_S_out ; +input prog_clk_0_E_in ; +input VDD ; +input VSS ; + +wire ropt_net_129 ; +wire ropt_net_130 ; +wire ropt_net_131 ; +wire ropt_net_128 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__2__mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[28] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[27] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_3 mux_right_track_6 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size4 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[23] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_12 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_14 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_18 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , + .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_22 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_24 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_40 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_42 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_44 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_46 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_17 mux_right_track_48 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_18 mux_right_track_50 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_19 mux_right_track_54 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_20 mux_right_track_56 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chanx_right_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_21 mux_right_track_58 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chanx_right_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_22 mux_bottom_track_1 ( + .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_23 mux_bottom_track_7 ( + .in ( { chanx_right_in[25] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_24 mux_bottom_track_13 ( + .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_25 mux_bottom_track_29 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_45 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_36 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_38 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_40 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_42 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_44 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_46 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_17 mem_right_track_48 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_18 mem_right_track_50 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_19 mem_right_track_54 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_20 mem_right_track_56 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_21 mem_right_track_58 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_22 mem_bottom_track_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_23 mem_bottom_track_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_24 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_25 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_26_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_28 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size3 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[3] ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[8] ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[9] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[13] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[16] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[18] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[20] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[21] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[23] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( chanx_right_in[24] ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[26] ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[27] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( pReset_E_in ) , .X ( pReset_S_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_129 ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v new file mode 100644 index 0000000..28a0128 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v @@ -0,0 +1,1916 @@ +// +// +// +// +// +// +module sb_0__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +wire copt_net_103 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_103 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_103 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_100 ) , + .X ( mem_out[1] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_74 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_190 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( copt_net_94 ) , + .X ( copt_net_92 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_92 ) , + .X ( copt_net_93 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , + .X ( copt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_93 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1351 ( .A ( copt_net_97 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1352 ( .A ( ropt_net_188 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1353 ( .A ( ropt_net_189 ) , + .X ( ropt_net_190 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + ccff_tail , SC_IN_TOP , SC_OUT_BOT , pReset_E_in , pReset_S_out , + prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input pReset_E_in ; +output pReset_S_out ; +input prog_clk_0_E_in ; + +wire ropt_net_129 ; +wire ropt_net_130 ; +wire ropt_net_131 ; +wire ropt_net_128 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__2__mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[28] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[27] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_3 mux_right_track_6 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size4 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[23] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_12 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_14 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_18 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_22 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_24 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_40 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_42 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_44 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_46 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_17 mux_right_track_48 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_18 mux_right_track_50 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_19 mux_right_track_54 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_20 mux_right_track_56 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_21 mux_right_track_58 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_22 mux_bottom_track_1 ( + .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_23 mux_bottom_track_7 ( + .in ( { chanx_right_in[25] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_24 mux_bottom_track_13 ( + .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_25 mux_bottom_track_29 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_45 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_36 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_38 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_40 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_42 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_44 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_46 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_17 mem_right_track_48 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_18 mem_right_track_50 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_19 mem_right_track_54 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_20 mem_right_track_56 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_21 mem_right_track_58 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_22 mem_bottom_track_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_23 mem_bottom_track_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_24 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_25 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_28 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size3 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_88 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[3] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[8] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[9] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[13] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[16] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[18] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[20] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[21] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[23] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( chanx_right_in[24] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[26] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[27] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( pReset_E_in ) , .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_129 ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[13] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..98e720e --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_0__2__icv_in_design.top_only.pt.v @@ -0,0 +1,551 @@ +// +// +// +// +// +// +module sb_0__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + ccff_tail , SC_IN_TOP , SC_OUT_BOT , pReset_E_in , pReset_S_out , + prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input pReset_E_in ; +output pReset_S_out ; +input prog_clk_0_E_in ; + +wire ropt_net_129 ; +wire ropt_net_130 ; +wire ropt_net_131 ; +wire ropt_net_128 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__2__mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[28] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[27] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_3 mux_right_track_6 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size4 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[23] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_12 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_14 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_18 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_22 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_24 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_40 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_42 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_44 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_46 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_17 mux_right_track_48 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_18 mux_right_track_50 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_19 mux_right_track_54 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_20 mux_right_track_56 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_21 mux_right_track_58 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_88 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_22 mux_bottom_track_1 ( + .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_23 mux_bottom_track_7 ( + .in ( { chanx_right_in[25] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_24 mux_bottom_track_13 ( + .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_25 mux_bottom_track_29 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_45 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_89 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_36 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_38 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_40 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_42 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_44 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_46 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_17 mem_right_track_48 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_18 mem_right_track_50 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_19 mem_right_track_54 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_20 mem_right_track_56 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_21 mem_right_track_58 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_22 mem_bottom_track_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_23 mem_bottom_track_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_24 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_25 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_28 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size3 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_88 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[3] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[8] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[9] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[13] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[16] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[18] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[20] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[21] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[23] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( chanx_right_in[24] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[26] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[27] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( pReset_E_in ) , .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_129 ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[13] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v new file mode 100644 index 0000000..c1005b9 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v @@ -0,0 +1,3842 @@ +// +// +// +// +// +// +module sb_1__0__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__0__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_148 ) ) ; +endmodule + + +module sb_1__0__const1_46 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__0__const1_46 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_45 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__0__const1_45 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_136 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1_44 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__0__const1_44 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_134 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1_43 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_1__0__const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_42 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_1__0__const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_132 ) ) ; +endmodule + + +module sb_1__0__const1_41 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_1__0__const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_130 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1_40 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) ) ; +endmodule + + +module sb_1__0__const1_39 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__const1_38 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_125 ) ) ; +endmodule + + +module sb_1__0__const1_37 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_36 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_123 ) ) ; +endmodule + + +module sb_1__0__const1_35 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_121 ) ) ; +endmodule + + +module sb_1__0__const1_34 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module sb_1__0__const1_33 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_117 ) ) ; +endmodule + + +module sb_1__0__const1_32 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_115 ) ) ; +endmodule + + +module sb_1__0__const1_31 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_30 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1_29 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__0__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_113 ) ) ; +endmodule + + +module sb_1__0__const1_28 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__0__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_111 ) ) ; +endmodule + + +module sb_1__0__const1_27 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__0__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_109 ) ) ; +endmodule + + +module sb_1__0__const1_26 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__0__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_25 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__0__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1_24 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__0__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_23 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__0__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_22 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__0__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_21 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__0__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_107 ) ) ; +endmodule + + +module sb_1__0__const1_20 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__0__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_105 ) ) ; +endmodule + + +module sb_1__0__const1_19 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__0__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1_18 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__0__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_17 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__0__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) ) ; +endmodule + + +module sb_1__0__const1_16 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__0__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_15 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__0__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__const1_14 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__0__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__const1_13 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__0__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1_12 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__0__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_11 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__0__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_10 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__0__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_193 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_159 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_160 ) , + .X ( copt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( ccff_head[0] ) , + .X ( copt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_158 ) , + .X ( copt_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_161 ) , + .X ( copt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1371 ( .A ( copt_net_162 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1372 ( .A ( ropt_net_192 ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1373 ( .A ( ropt_net_190 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1374 ( .A ( ropt_net_194 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1375 ( .A ( ropt_net_191 ) , + .X ( ropt_net_194 ) ) ; +endmodule + + +module sb_1__0__const1_9 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_8 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__const1_7 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_6 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_5 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_98 ) ) ; +endmodule + + +module sb_1__0__const1_4 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_3 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_2 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_96 ) ) ; +endmodule + + +module sb_1__0__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_1__0__const1_0 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_1__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_1_ , + right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , + right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , + right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ , + right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , + left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , + left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , + chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in , + Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , + pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , + prog_clk_3_S_in , prog_clk_3_N_out , clk_3_S_in , clk_3_N_out ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; +input [0:0] right_bottom_grid_pin_13_ ; +input [0:0] right_bottom_grid_pin_15_ ; +input [0:0] right_bottom_grid_pin_17_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] left_bottom_grid_pin_13_ ; +input [0:0] left_bottom_grid_pin_15_ ; +input [0:0] left_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_TOP ; +input Test_en_S_in ; +output Test_en_N_out ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_N_out ; +output pReset_W_out ; +output pReset_E_out ; +input Reset_S_in ; +output Reset_N_out ; +input prog_clk_0_N_in ; +input prog_clk_3_S_in ; +output prog_clk_3_N_out ; +input clk_3_S_in ; +output clk_3_N_out ; + +wire ropt_net_176 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:2] mux_tree_tapbuf_size7_9_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; + +assign pReset_S_in = pReset_E_in ; +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; + +sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] , + chanx_left_in[0] , chanx_right_out[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 ( + .in ( { chany_top_in[10] , chany_top_in[21] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_13_[0] , chanx_right_out[4] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 ( + .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 ( + .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 ( + .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] , + chanx_right_out[15] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 ( + .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] , + chanx_left_out[21] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 ( + .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] , + chanx_left_out[23] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 ( + .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , + chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 ( + .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , + chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 ( + .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , + chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size7_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_8 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_9_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_0 mux_top_track_2 ( + .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , + chanx_right_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] , + chanx_right_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 ( + .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] , + chanx_right_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_0 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_right_in[4] , chanx_left_out[8] , chanx_right_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , + SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_2 mux_right_track_36 ( + .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , + right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_3 mux_left_track_37 ( + .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , + chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_4 mux_left_track_45 ( + .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , + chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size5 mux_left_track_53 ( + .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , + chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , + SYNOPSYS_UNCONNECTED_57 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_2 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_3 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_4 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_out[13] , + chanx_right_in[17] , chanx_right_out[13] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , + SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_1 mux_top_track_14 ( + .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] , + chanx_right_out[15] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 } ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_2 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] , + chanx_right_in[25] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , + SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_3 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_out[17] , + chanx_right_in[29] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , + SYNOPSYS_UNCONNECTED_69 } ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_4 mux_right_track_44 ( + .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] , + chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , + SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4 mux_right_track_52 ( + .in ( { chany_top_in[9] , chany_top_in[20] , + right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_out[19] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_24 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_26 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 } ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size3 mux_top_track_36 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_0 mux_top_track_28 ( + .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_1 mux_top_track_30 ( + .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 } ) , + .out ( chany_top_out[15] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_2 mux_top_track_32 ( + .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_3 mux_top_track_34 ( + .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) , + .out ( chany_top_out[17] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_4 mux_top_track_40 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 } ) , + .out ( chany_top_out[20] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_5 mux_top_track_42 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) , + .out ( chany_top_out[21] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_6 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_7 mux_top_track_46 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_100 , SYNOPSYS_UNCONNECTED_101 } ) , + .out ( chany_top_out[23] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_8 mux_top_track_48 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , + .out ( chany_top_out[24] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_9 mux_top_track_50 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 } ) , + .out ( chany_top_out[25] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size2 mux_top_track_58 ( + .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 } ) , + .out ( chany_top_out[29] ) , .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_42 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_58 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] , + right_bottom_grid_pin_15_[0] , chanx_right_out[7] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , + SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , + right_bottom_grid_pin_17_[0] , chanx_right_out[8] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_112 , SYNOPSYS_UNCONNECTED_113 , + SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , + chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_116 , SYNOPSYS_UNCONNECTED_117 , + SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size10 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_13_[0] , + right_bottom_grid_pin_17_[0] , chanx_right_out[9] , + chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_120 , SYNOPSYS_UNCONNECTED_121 , + SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ; +sb_1__0__mux_tree_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_10 ( + .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_124 , SYNOPSYS_UNCONNECTED_125 , + SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_153 ) ) ; +sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 ( + .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] , + chanx_left_out[24] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , + left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_128 , SYNOPSYS_UNCONNECTED_129 , + SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 ( + .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , + chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , + left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , + SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem_1 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( top_left_grid_pin_45_[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_12 FTB_50__49 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[2] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[4] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[5] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , + .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( Test_en_S_in ) , .Y ( BUF_net_138 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_140 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( Reset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( Reset_S_in ) , .Y ( BUF_net_142 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) , + .Y ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_144 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_176 ) , + .X ( SC_OUT_TOP ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v new file mode 100644 index 0000000..34cfa8c --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v @@ -0,0 +1,4214 @@ +// +// +// +// +// +// +module sb_1__0__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_193 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_159 ) , + .X ( copt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_160 ) , + .X ( copt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( ccff_head[0] ) , + .X ( copt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_158 ) , + .X ( copt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_161 ) , + .X ( copt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1371 ( .A ( copt_net_162 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1372 ( .A ( ropt_net_192 ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1373 ( .A ( ropt_net_190 ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1374 ( .A ( ropt_net_194 ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1375 ( .A ( ropt_net_191 ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_1_ , + right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , + right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , + right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ , + right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , + left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , + left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , + chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in , + Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , + pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , + prog_clk_3_S_in , prog_clk_3_N_out , clk_3_S_in , clk_3_N_out , VDD , + VSS ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; +input [0:0] right_bottom_grid_pin_13_ ; +input [0:0] right_bottom_grid_pin_15_ ; +input [0:0] right_bottom_grid_pin_17_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] left_bottom_grid_pin_13_ ; +input [0:0] left_bottom_grid_pin_15_ ; +input [0:0] left_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_TOP ; +input Test_en_S_in ; +output Test_en_N_out ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_N_out ; +output pReset_W_out ; +output pReset_E_out ; +input Reset_S_in ; +output Reset_N_out ; +input prog_clk_0_N_in ; +input prog_clk_3_S_in ; +output prog_clk_3_N_out ; +input clk_3_S_in ; +output clk_3_N_out ; +input VDD ; +input VSS ; + +wire ropt_net_176 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:2] mux_tree_tapbuf_size7_9_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign pReset_S_in = pReset_E_in ; +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; + +sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] , + chanx_left_in[0] , chanx_right_out[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 ( + .in ( { chany_top_in[10] , chany_top_in[21] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_13_[0] , chanx_right_out[4] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 ( + .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 ( + .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 ( + .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] , + chanx_right_out[15] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 ( + .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] , + chanx_left_out[21] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 ( + .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] , + chanx_left_out[23] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 ( + .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , + chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 ( + .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , + chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 ( + .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , + chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size7_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_8 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size6_0 mux_top_track_2 ( + .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , + chanx_right_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] , + chanx_right_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 ( + .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] , + chanx_right_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size5_0 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_right_in[4] , chanx_left_out[8] , chanx_right_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , + SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_2 mux_right_track_36 ( + .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , + right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_3 mux_left_track_37 ( + .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , + chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_4 mux_left_track_45 ( + .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , + chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size5 mux_left_track_53 ( + .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , + chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , + SYNOPSYS_UNCONNECTED_57 } ) , + .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_2 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_3 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_4 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_5_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_out[13] , + chanx_right_in[17] , chanx_right_out[13] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , + SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_1 mux_top_track_14 ( + .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] , + chanx_right_out[15] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 } ) , + .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_2 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] , + chanx_right_in[25] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , + SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_3 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_out[17] , + chanx_right_in[29] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , + SYNOPSYS_UNCONNECTED_69 } ) , + .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_4 mux_right_track_44 ( + .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] , + chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , + SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4 mux_right_track_52 ( + .in ( { chany_top_in[9] , chany_top_in[20] , + right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 } ) , + .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_out[19] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 } ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) , + .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_24 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_26 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 } ) , + .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size3 mux_top_track_36 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , + .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_0 mux_top_track_28 ( + .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_1 mux_top_track_30 ( + .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 } ) , + .out ( chany_top_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_2 mux_top_track_32 ( + .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) , + .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_3 mux_top_track_34 ( + .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) , + .out ( chany_top_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_4 mux_top_track_40 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 } ) , + .out ( chany_top_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_5 mux_top_track_42 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) , + .out ( chany_top_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_6 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 } ) , + .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_7 mux_top_track_46 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_100 , SYNOPSYS_UNCONNECTED_101 } ) , + .out ( chany_top_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_8 mux_top_track_48 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , + .out ( chany_top_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_9 mux_top_track_50 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 } ) , + .out ( chany_top_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size2 mux_top_track_58 ( + .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 } ) , + .out ( chany_top_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_42 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_58 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size8_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] , + right_bottom_grid_pin_15_[0] , chanx_right_out[7] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , + SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 } ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , + right_bottom_grid_pin_17_[0] , chanx_right_out[8] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_112 , SYNOPSYS_UNCONNECTED_113 , + SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 } ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , + chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_116 , SYNOPSYS_UNCONNECTED_117 , + SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 } ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size10 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_13_[0] , + right_bottom_grid_pin_17_[0] , chanx_right_out[9] , + chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_120 , SYNOPSYS_UNCONNECTED_121 , + SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 } ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_1__0__mux_tree_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_10 ( + .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_124 , SYNOPSYS_UNCONNECTED_125 , + SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 ( + .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] , + chanx_left_out[24] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , + left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_128 , SYNOPSYS_UNCONNECTED_129 , + SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 } ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 ( + .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , + chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , + left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , + SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 } ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem_1 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , + .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , + .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( top_left_grid_pin_45_[0] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_12 FTB_50__49 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[2] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[4] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[5] ) , + .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_176 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , + .Y ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( Test_en_S_in ) , .Y ( BUF_net_138 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( pReset_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( Reset_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( Reset_S_in ) , .Y ( BUF_net_142 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) , + .Y ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( clk_3_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_176 ) , + .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v new file mode 100644 index 0000000..bcda188 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v @@ -0,0 +1,3314 @@ +// +// +// +// +// +// +module sb_1__0__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_148 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_136 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_134 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_132 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_130 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_125 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_123 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_121 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_117 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_115 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_113 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_111 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_109 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_107 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_105 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_193 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_159 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_160 ) , + .X ( copt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( ccff_head[0] ) , + .X ( copt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_158 ) , + .X ( copt_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_161 ) , + .X ( copt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1371 ( .A ( copt_net_162 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1372 ( .A ( ropt_net_192 ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1373 ( .A ( ropt_net_190 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1374 ( .A ( ropt_net_194 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1375 ( .A ( ropt_net_191 ) , + .X ( ropt_net_194 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_98 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_96 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_1__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_1_ , + right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , + right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , + right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ , + right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , + left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , + left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , + chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in , + Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , + pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , + prog_clk_3_S_in , prog_clk_3_N_out , clk_3_S_in , clk_3_N_out ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; +input [0:0] right_bottom_grid_pin_13_ ; +input [0:0] right_bottom_grid_pin_15_ ; +input [0:0] right_bottom_grid_pin_17_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] left_bottom_grid_pin_13_ ; +input [0:0] left_bottom_grid_pin_15_ ; +input [0:0] left_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_TOP ; +input Test_en_S_in ; +output Test_en_N_out ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_N_out ; +output pReset_W_out ; +output pReset_E_out ; +input Reset_S_in ; +output Reset_N_out ; +input prog_clk_0_N_in ; +input prog_clk_3_S_in ; +output prog_clk_3_N_out ; +input clk_3_S_in ; +output clk_3_N_out ; + +wire ropt_net_176 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:2] mux_tree_tapbuf_size7_9_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; + +assign pReset_E_in = pReset_S_in ; +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; + +sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] , + chanx_left_in[0] , chanx_right_out[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 ( + .in ( { chany_top_in[10] , chany_top_in[21] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_13_[0] , chanx_right_out[4] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 ( + .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 ( + .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 ( + .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] , + chanx_right_out[15] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 ( + .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] , + chanx_left_out[21] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 ( + .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] , + chanx_left_out[23] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 ( + .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , + chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 ( + .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , + chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 ( + .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , + chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size7_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_8 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_9_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_0 mux_top_track_2 ( + .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , + chanx_right_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] , + chanx_right_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 ( + .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] , + chanx_right_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_0 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_right_in[4] , chanx_left_out[8] , chanx_right_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , + SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_2 mux_right_track_36 ( + .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , + right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_3 mux_left_track_37 ( + .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , + chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_4 mux_left_track_45 ( + .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , + chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size5 mux_left_track_53 ( + .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , + chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , + SYNOPSYS_UNCONNECTED_57 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_2 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_3 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_4 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_out[13] , + chanx_right_in[17] , chanx_right_out[13] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , + SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_1 mux_top_track_14 ( + .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] , + chanx_right_out[15] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 } ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_2 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] , + chanx_right_in[25] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , + SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_3 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_out[17] , + chanx_right_in[29] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , + SYNOPSYS_UNCONNECTED_69 } ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_4 mux_right_track_44 ( + .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] , + chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , + SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4 mux_right_track_52 ( + .in ( { chany_top_in[9] , chany_top_in[20] , + right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_out[19] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_24 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_26 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 } ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size3 mux_top_track_36 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_0 mux_top_track_28 ( + .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_1 mux_top_track_30 ( + .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 } ) , + .out ( chany_top_out[15] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_2 mux_top_track_32 ( + .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_3 mux_top_track_34 ( + .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) , + .out ( chany_top_out[17] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_4 mux_top_track_40 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 } ) , + .out ( chany_top_out[20] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_5 mux_top_track_42 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) , + .out ( chany_top_out[21] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_6 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_7 mux_top_track_46 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_100 , SYNOPSYS_UNCONNECTED_101 } ) , + .out ( chany_top_out[23] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_8 mux_top_track_48 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , + .out ( chany_top_out[24] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_9 mux_top_track_50 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 } ) , + .out ( chany_top_out[25] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size2 mux_top_track_58 ( + .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 } ) , + .out ( chany_top_out[29] ) , .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_42 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_58 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] , + right_bottom_grid_pin_15_[0] , chanx_right_out[7] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , + SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , + right_bottom_grid_pin_17_[0] , chanx_right_out[8] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_112 , SYNOPSYS_UNCONNECTED_113 , + SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , + chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_116 , SYNOPSYS_UNCONNECTED_117 , + SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size10 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_13_[0] , + right_bottom_grid_pin_17_[0] , chanx_right_out[9] , + chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_120 , SYNOPSYS_UNCONNECTED_121 , + SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ; +sb_1__0__mux_tree_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_10 ( + .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_124 , SYNOPSYS_UNCONNECTED_125 , + SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_153 ) ) ; +sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 ( + .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] , + chanx_left_out[24] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , + left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_128 , SYNOPSYS_UNCONNECTED_129 , + SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 ( + .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , + chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , + left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , + SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem_1 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( top_left_grid_pin_45_[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_12 FTB_50__49 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[2] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[4] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[5] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , + .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( Test_en_S_in ) , .Y ( BUF_net_138 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_140 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( Reset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( Reset_S_in ) , .Y ( BUF_net_142 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) , + .Y ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_144 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_176 ) , + .X ( SC_OUT_TOP ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..5b7b899 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__0__icv_in_design.top_only.pt.v @@ -0,0 +1,888 @@ +// +// +// +// +// +// +module sb_1__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_1_ , + right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , + right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , + right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ , + right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , + left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , + left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , + chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in , + Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , + pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , + prog_clk_3_S_in , prog_clk_3_N_out , clk_3_S_in , clk_3_N_out ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; +input [0:0] right_bottom_grid_pin_13_ ; +input [0:0] right_bottom_grid_pin_15_ ; +input [0:0] right_bottom_grid_pin_17_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] left_bottom_grid_pin_13_ ; +input [0:0] left_bottom_grid_pin_15_ ; +input [0:0] left_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_TOP ; +input Test_en_S_in ; +output Test_en_N_out ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_N_out ; +output pReset_W_out ; +output pReset_E_out ; +input Reset_S_in ; +output Reset_N_out ; +input prog_clk_0_N_in ; +input prog_clk_3_S_in ; +output prog_clk_3_N_out ; +input clk_3_S_in ; +output clk_3_N_out ; + +wire ropt_net_176 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:2] mux_tree_tapbuf_size7_9_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; + +assign pReset_E_in = pReset_S_in ; +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; + +sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] , + chanx_left_in[0] , chanx_right_out[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 ( + .in ( { chany_top_in[10] , chany_top_in[21] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_13_[0] , chanx_right_out[4] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 ( + .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 ( + .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 ( + .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] , + chanx_right_out[15] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 ( + .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] , + chanx_left_out[21] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 ( + .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] , + chanx_left_out[23] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 ( + .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , + chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 ( + .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , + chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 ( + .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , + chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size7_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_8 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_9_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_0 mux_top_track_2 ( + .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , + chanx_right_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] , + chanx_right_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 ( + .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] , + chanx_right_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_0 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_right_in[4] , chanx_left_out[8] , chanx_right_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , + SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_2 mux_right_track_36 ( + .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , + right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_3 mux_left_track_37 ( + .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , + chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_4 mux_left_track_45 ( + .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , + chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size5 mux_left_track_53 ( + .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , + chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , + SYNOPSYS_UNCONNECTED_57 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_2 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_3 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_4 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_out[13] , + chanx_right_in[17] , chanx_right_out[13] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , + SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_1 mux_top_track_14 ( + .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] , + chanx_right_out[15] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 } ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_2 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] , + chanx_right_in[25] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , + SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_3 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_out[17] , + chanx_right_in[29] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , + SYNOPSYS_UNCONNECTED_69 } ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_4 mux_right_track_44 ( + .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] , + chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , + SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4 mux_right_track_52 ( + .in ( { chany_top_in[9] , chany_top_in[20] , + right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_out[19] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_24 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_26 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 } ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size3 mux_top_track_36 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_0 mux_top_track_28 ( + .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_1 mux_top_track_30 ( + .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 } ) , + .out ( chany_top_out[15] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_2 mux_top_track_32 ( + .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_3 mux_top_track_34 ( + .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) , + .out ( chany_top_out[17] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_4 mux_top_track_40 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 } ) , + .out ( chany_top_out[20] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_5 mux_top_track_42 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) , + .out ( chany_top_out[21] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_6 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_7 mux_top_track_46 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_100 , SYNOPSYS_UNCONNECTED_101 } ) , + .out ( chany_top_out[23] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_8 mux_top_track_48 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , + .out ( chany_top_out[24] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_9 mux_top_track_50 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 } ) , + .out ( chany_top_out[25] ) , .p0 ( optlc_net_155 ) ) ; +sb_1__0__mux_tree_tapbuf_size2 mux_top_track_58 ( + .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 } ) , + .out ( chany_top_out[29] ) , .p0 ( optlc_net_154 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_42 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_58 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] , + right_bottom_grid_pin_15_[0] , chanx_right_out[7] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , + SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , + right_bottom_grid_pin_17_[0] , chanx_right_out[8] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_112 , SYNOPSYS_UNCONNECTED_113 , + SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , + chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_116 , SYNOPSYS_UNCONNECTED_117 , + SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size10 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_13_[0] , + right_bottom_grid_pin_17_[0] , chanx_right_out[9] , + chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_120 , SYNOPSYS_UNCONNECTED_121 , + SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ; +sb_1__0__mux_tree_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_10 ( + .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_124 , SYNOPSYS_UNCONNECTED_125 , + SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_153 ) ) ; +sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 ( + .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] , + chanx_left_out[24] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , + left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_128 , SYNOPSYS_UNCONNECTED_129 , + SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 ( + .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , + chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , + left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , + SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem_1 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( top_left_grid_pin_45_[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_12 FTB_50__49 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[2] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[4] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[5] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , + .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( Test_en_S_in ) , .Y ( BUF_net_138 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_140 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( Reset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( Reset_S_in ) , .Y ( BUF_net_142 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) , + .Y ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_144 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_176 ) , + .X ( SC_OUT_TOP ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v new file mode 100644 index 0000000..e7b4459 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v @@ -0,0 +1,4604 @@ +// +// +// +// +// +// +module sb_1__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_42 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_150 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_41 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_149 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_149 ) ) ; +endmodule + + +module sb_1__1__const1_40 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_39 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_38 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_37 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_36 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__1__const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_35 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_147 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_147 ) ) ; +endmodule + + +module sb_1__1__const1_34 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_145 ) ) ; +endmodule + + +module sb_1__1__const1_33 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_32 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__const1_31 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__1__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_30 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__1__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_155 ) ) ; +endmodule + + +module sb_1__1__const1_29 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__1__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_143 ) ) ; +endmodule + + +module sb_1__1__const1_28 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__1__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__const1_27 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_26 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_25 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_141 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_24 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_23 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_140 ) ) ; +endmodule + + +module sb_1__1__const1_22 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_138 ) ) ; +endmodule + + +module sb_1__1__const1_21 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_136 ) ) ; +endmodule + + +module sb_1__1__const1_20 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_134 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__const1_19 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_18 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_132 ) ) ; +endmodule + + +module sb_1__1__const1_17 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_16 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_15 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_14 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_13 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_130 ) ) ; +endmodule + + +module sb_1__1__const1_12 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_11 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_128 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_10 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_127 ) ) ; +endmodule + + +module sb_1__1__const1_9 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_153 ) ) ; +endmodule + + +module sb_1__1__const1_8 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_176 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1366 ( .A ( copt_net_175 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_174 ) , + .X ( copt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( ropt_net_181 ) , + .X ( copt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( ccff_head[0] ) , + .X ( copt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( ropt_net_183 ) , + .X ( copt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( ropt_net_178 ) , + .X ( copt_net_176 ) ) ; +sky130_fd_sc_hd__buf_4 ropt_h_inst_1371 ( .A ( ropt_net_180 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( copt_net_173 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1368 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1369 ( .A ( copt_net_172 ) , + .X ( ropt_net_181 ) ) ; +endmodule + + +module sb_1__1__const1_7 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_125 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_6 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_5 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_124 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_4 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .Y ( BUF_net_123 ) ) ; +endmodule + + +module sb_1__1__const1_3 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_2 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .Y ( BUF_net_121 ) ) ; +endmodule + + +module sb_1__1__const1_0 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_36_ , + right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , + right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , + right_bottom_grid_pin_41_ , right_bottom_grid_pin_42_ , + right_bottom_grid_pin_43_ , chany_bottom_in , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ , + bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in , + Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , + pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , + prog_clk_1_N_in , prog_clk_1_S_in , prog_clk_1_E_out , prog_clk_1_W_out , + prog_clk_2_N_in , prog_clk_2_E_in , prog_clk_2_S_in , prog_clk_2_W_in , + prog_clk_2_W_out , prog_clk_2_S_out , prog_clk_2_N_out , + prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_S_in , + prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out , prog_clk_3_N_out , + prog_clk_3_S_out , clk_1_N_in , clk_1_S_in , clk_1_E_out , clk_1_W_out , + clk_2_N_in , clk_2_E_in , clk_2_S_in , clk_2_W_in , clk_2_W_out , + clk_2_S_out , clk_2_N_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , + clk_3_S_in , clk_3_N_in , clk_3_E_out , clk_3_W_out , clk_3_N_out , + clk_3_S_out ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input Test_en_S_in ; +output Test_en_N_out ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_N_out ; +output pReset_W_out ; +output pReset_E_out ; +input Reset_S_in ; +output Reset_N_out ; +input prog_clk_0_N_in ; +input prog_clk_1_N_in ; +input prog_clk_1_S_in ; +output prog_clk_1_E_out ; +output prog_clk_1_W_out ; +input prog_clk_2_N_in ; +input prog_clk_2_E_in ; +input prog_clk_2_S_in ; +input prog_clk_2_W_in ; +output prog_clk_2_W_out ; +output prog_clk_2_S_out ; +output prog_clk_2_N_out ; +output prog_clk_2_E_out ; +input prog_clk_3_W_in ; +input prog_clk_3_E_in ; +input prog_clk_3_S_in ; +input prog_clk_3_N_in ; +output prog_clk_3_E_out ; +output prog_clk_3_W_out ; +output prog_clk_3_N_out ; +output prog_clk_3_S_out ; +input clk_1_N_in ; +input clk_1_S_in ; +output clk_1_E_out ; +output clk_1_W_out ; +input clk_2_N_in ; +input clk_2_E_in ; +input clk_2_S_in ; +input clk_2_W_in ; +output clk_2_W_out ; +output clk_2_S_out ; +output clk_2_N_out ; +output clk_2_E_out ; +input clk_3_W_in ; +input clk_3_E_in ; +input clk_3_S_in ; +input clk_3_N_in ; +output clk_3_E_out ; +output clk_3_W_out ; +output clk_3_N_out ; +output clk_3_S_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_10_sram ; +wire [0:3] mux_tree_tapbuf_size10_11_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_9_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size11_0_sram ; +wire [0:3] mux_tree_tapbuf_size11_1_sram ; +wire [0:3] mux_tree_tapbuf_size11_2_sram ; +wire [0:3] mux_tree_tapbuf_size11_3_sram ; +wire [0:3] mux_tree_tapbuf_size11_4_sram ; +wire [0:3] mux_tree_tapbuf_size11_5_sram ; +wire [0:3] mux_tree_tapbuf_size11_6_sram ; +wire [0:3] mux_tree_tapbuf_size11_7_sram ; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_10_sram ; +wire [0:2] mux_tree_tapbuf_size6_11_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_7_sram ; +wire [0:2] mux_tree_tapbuf_size6_8_sram ; +wire [0:2] mux_tree_tapbuf_size6_9_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:3] mux_tree_tapbuf_size9_3_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail ; + +assign prog_clk_1_E_out = prog_clk_1_S_in ; +assign prog_clk_1_W_out = prog_clk_1_S_in ; +assign prog_clk_2_W_out = prog_clk_2_W_in ; +assign prog_clk_2_S_out = prog_clk_2_W_in ; +assign prog_clk_2_N_out = prog_clk_2_W_in ; +assign prog_clk_2_E_out = prog_clk_2_W_in ; +assign prog_clk_3_E_out = prog_clk_3_N_in ; +assign prog_clk_3_W_out = prog_clk_3_N_in ; +assign prog_clk_3_N_out = prog_clk_3_N_in ; +assign prog_clk_3_S_out = prog_clk_3_N_in ; +assign clk_1_E_out = clk_1_S_in ; +assign clk_1_W_out = clk_1_S_in ; +assign clk_2_W_out = clk_2_W_in ; +assign clk_2_S_out = clk_2_W_in ; +assign clk_2_N_out = clk_2_W_in ; +assign clk_2_E_out = clk_2_W_in ; +assign clk_3_E_out = clk_3_N_in ; +assign clk_3_W_out = clk_3_N_in ; +assign clk_3_N_out = clk_3_N_in ; +assign clk_3_S_out = clk_3_N_in ; +assign pReset_S_in = pReset_E_in ; +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_1_N_in = prog_clk_1_S_in ; +assign prog_clk_2_W_in = prog_clk_2_N_in ; +assign prog_clk_2_W_in = prog_clk_2_S_in ; +assign prog_clk_3_N_in = prog_clk_3_W_in ; +assign prog_clk_3_N_in = prog_clk_3_S_in ; +assign clk_1_N_in = clk_1_S_in ; +assign clk_2_W_in = clk_2_N_in ; +assign clk_2_W_in = clk_2_S_in ; +assign clk_3_N_in = clk_3_W_in ; +assign clk_3_N_in = clk_3_S_in ; +assign prog_clk_2_W_in = prog_clk_2_E_in ; +assign prog_clk_3_N_in = prog_clk_3_E_in ; +assign clk_2_W_in = clk_2_E_in ; +assign clk_3_N_in = clk_3_E_in ; + +sb_1__1__mux_tree_tapbuf_size11_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] , + chanx_left_out[20] , chany_top_out[4] , chany_top_out[20] , + chanx_left_in[0] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , + chanx_left_out[21] , chany_top_out[7] , chany_top_out[21] , + chanx_right_out[7] , chanx_right_out[21] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size11_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_2 mux_right_track_0 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chany_top_in[29] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_top_out[4] , chany_top_out[20] , + chany_bottom_in[25] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_3 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_bottom_out[7] , chany_bottom_out[21] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[7] , chany_top_out[21] , + chany_bottom_in[21] , chanx_right_out[7] , chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size11_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_4 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] , + chanx_left_out[20] , chanx_right_in[25] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[1] , chanx_right_out[4] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_5 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_left_out[7] , + chanx_left_out[21] , chanx_right_in[21] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[2] , chanx_right_out[7] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size11_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_6 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_bottom_out[20] , + chanx_left_out[4] , chanx_left_out[20] , chany_top_out[4] , + chany_top_out[20] , chany_bottom_in[29] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size11_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size11 mux_left_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chany_top_in[29] , + chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , + chany_top_out[7] , chany_top_out[21] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size11_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_1 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_2 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_3 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_4 mem_bottom_track_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_5 mem_bottom_track_3 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_0 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_right_in[4] , chanx_left_out[8] , chanx_left_out[23] , + chany_top_out[8] , chany_top_out[23] , chanx_right_out[8] , + chanx_right_out[23] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , + chanx_left_out[12] , chanx_right_in[13] , chanx_left_out[27] , + chany_top_out[12] , chany_top_out[27] , chanx_right_out[12] , + chanx_left_in[13] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_20 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , + chanx_left_out[13] , chanx_right_in[17] , chanx_left_out[28] , + chany_top_out[13] , chany_top_out[28] , chanx_left_in[9] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_bottom_out[8] , chany_bottom_out[23] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[8] , chany_bottom_in[17] , chany_top_out[23] , + chanx_right_out[8] , chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_12 ( + .in ( { chany_top_in[5] , chany_bottom_out[12] , chany_bottom_out[27] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[5] , chany_top_out[12] , chany_top_out[27] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_20 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[4] , chany_top_out[13] , chany_top_out[28] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_left_out[8] , + chanx_right_in[17] , chanx_left_out[23] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[4] , chanx_right_out[8] , chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_7 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[5] , + chanx_left_out[12] , chanx_left_out[27] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , + chanx_right_out[12] , chanx_left_in[13] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[4] , + chanx_left_out[13] , chanx_left_out[28] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , + chanx_right_out[13] , chanx_left_in[17] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chany_top_in[25] , + chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , + chany_top_out[8] , chany_top_out[23] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size10_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , + SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_13 ( + .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] , + chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] , + chany_top_out[12] , chany_top_out[27] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size10_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10 mux_left_track_21 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , + chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[9] , + chany_top_out[13] , chany_top_out[28] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size10_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , + SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_track_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_track_20 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_bottom_track_5 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_left_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , + chanx_right_in[5] , chanx_left_out[9] , chanx_left_out[24] , + chany_top_out[9] , chany_top_out[24] , chanx_right_out[9] , + chanx_left_in[21] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , + SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , + chanx_right_in[9] , chanx_left_out[11] , chanx_left_out[25] , + chany_top_out[11] , chany_top_out[25] , chanx_right_out[11] , + chanx_left_in[17] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , + SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_bottom_out[9] , chany_bottom_out[24] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , + chany_top_out[9] , chany_bottom_in[13] , chany_top_out[24] , + chanx_right_out[9] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , + SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_10 ( + .in ( { chany_top_in[4] , chany_bottom_out[11] , chany_bottom_out[25] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[9] , chany_top_out[11] , chany_top_out[25] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , + SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_left_out[9] , + chanx_right_in[13] , chanx_left_out[24] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_right_out[9] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , + SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[9] , + chanx_left_out[11] , chanx_left_out[25] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[9] , chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , + SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_7 ( + .in ( { chany_bottom_out[9] , chany_top_in[21] , chany_bottom_out[24] , + chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , + chany_top_out[9] , chany_top_out[24] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , + SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( { ropt_net_182 } ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size12 mux_left_track_11 ( + .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] , + chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] , + chany_top_out[11] , chany_top_out[25] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , + SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_track_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_bottom_track_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_0 mux_top_track_28 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_out[15] , + chanx_right_in[21] , chanx_left_out[29] , chany_top_out[15] , + chany_top_out[29] , chanx_left_in[5] , chanx_right_out[15] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , + SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_1 mux_right_track_28 ( + .in ( { chany_top_in[13] , chany_bottom_out[15] , chany_bottom_out[29] , + right_bottom_grid_pin_38_[0] , chany_bottom_in[2] , + chany_top_out[15] , chany_top_out[29] , chanx_right_out[15] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , + SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_2 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , + chanx_left_out[15] , chanx_left_out[29] , + bottom_left_grid_pin_46_[0] , chanx_right_out[15] , + chanx_left_in[21] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , + SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size9 mux_left_track_29 ( + .in ( { chany_top_in[5] , chany_bottom_out[15] , chany_bottom_out[29] , + chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[13] , + chany_top_out[15] , chany_top_out[29] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size9_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , + SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_1 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_2 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_0 mux_top_track_36 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_out[16] , + chanx_right_in[25] , chany_top_out[16] , chanx_left_in[4] , + chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , + SYNOPSYS_UNCONNECTED_131 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , + chanx_right_in[29] , chany_top_out[17] , chanx_left_in[2] , + chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , + SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_2 mux_top_track_52 ( + .in ( { top_left_grid_pin_49_[0] , chanx_right_in[0] , + chanx_left_out[19] , chany_top_out[19] , chanx_left_in[1] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 , + SYNOPSYS_UNCONNECTED_137 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_3 mux_right_track_36 ( + .in ( { chany_bottom_out[16] , chany_top_in[17] , + right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , + chany_top_out[16] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_138 , SYNOPSYS_UNCONNECTED_139 , + SYNOPSYS_UNCONNECTED_140 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_4 mux_right_track_44 ( + .in ( { chany_bottom_out[17] , chany_top_in[21] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , + chany_top_out[17] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , + SYNOPSYS_UNCONNECTED_143 } ) , + .out ( { ZBUF_6_f_0 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_5 mux_right_track_52 ( + .in ( { chany_bottom_out[19] , chany_top_in[25] , + right_bottom_grid_pin_41_[0] , chany_top_out[19] , + chany_bottom_in[29] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_144 , SYNOPSYS_UNCONNECTED_145 , + SYNOPSYS_UNCONNECTED_146 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_6 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_left_out[16] , + bottom_left_grid_pin_47_[0] , chanx_right_out[16] , + chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 , + SYNOPSYS_UNCONNECTED_149 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_7 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_left_out[17] , + bottom_left_grid_pin_48_[0] , chanx_right_out[17] , + chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size6_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_150 , SYNOPSYS_UNCONNECTED_151 , + SYNOPSYS_UNCONNECTED_152 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_8 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , chanx_left_out[19] , chanx_right_in[29] , + bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , + SYNOPSYS_UNCONNECTED_155 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_9 mux_left_track_37 ( + .in ( { chany_top_in[4] , chany_bottom_out[16] , chanx_left_out[16] , + chany_top_out[16] , chany_bottom_in[17] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size6_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_156 , SYNOPSYS_UNCONNECTED_157 , + SYNOPSYS_UNCONNECTED_158 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_10 mux_left_track_45 ( + .in ( { chany_top_in[2] , chany_bottom_out[17] , chanx_left_out[17] , + chany_top_out[17] , chany_bottom_in[21] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size6_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 , + SYNOPSYS_UNCONNECTED_161 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6 mux_left_track_53 ( + .in ( { chany_top_in[1] , chany_bottom_out[19] , chanx_left_out[19] , + chany_top_out[19] , chany_bottom_in[25] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_162 , SYNOPSYS_UNCONNECTED_163 , + SYNOPSYS_UNCONNECTED_164 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_7 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_8 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_8_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_9 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_9_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_10 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_10_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_11_sram ) ) ; +sky130_fd_sc_hd__buf_4 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , + .X ( net_net_151 ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_6 Reset_N_FTB01 ( .A ( Reset_S_in ) , + .X ( Reset_N_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_92__91 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_93__92 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_94__93 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_95__94 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_96__95 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_97__96 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_98__97 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_99__98 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_100__99 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_101__100 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_102__101 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_103__102 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_104__103 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_109__108 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_151 ( .A ( net_net_151 ) , + .X ( pReset_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1350 ( .A ( ZBUF_6_f_0 ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_4 ropt_mt_inst_1370 ( .A ( ropt_net_182 ) , + .X ( chanx_left_out[3] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v new file mode 100644 index 0000000..6c2c9ea --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v @@ -0,0 +1,5069 @@ +// +// +// +// +// +// +module sb_1__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_150 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_149 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_147 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_141 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_128 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_176 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1366 ( .A ( copt_net_175 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_174 ) , + .X ( copt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( ropt_net_181 ) , + .X ( copt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( ccff_head[0] ) , + .X ( copt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( ropt_net_183 ) , + .X ( copt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( ropt_net_178 ) , + .X ( copt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 ropt_h_inst_1371 ( .A ( ropt_net_180 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( copt_net_173 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1368 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1369 ( .A ( copt_net_172 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_125 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_124 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .Y ( BUF_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .Y ( BUF_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_36_ , + right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , + right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , + right_bottom_grid_pin_41_ , right_bottom_grid_pin_42_ , + right_bottom_grid_pin_43_ , chany_bottom_in , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ , + bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in , + Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , + pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , + prog_clk_1_N_in , prog_clk_1_S_in , prog_clk_1_E_out , prog_clk_1_W_out , + prog_clk_2_N_in , prog_clk_2_E_in , prog_clk_2_S_in , prog_clk_2_W_in , + prog_clk_2_W_out , prog_clk_2_S_out , prog_clk_2_N_out , + prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_S_in , + prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out , prog_clk_3_N_out , + prog_clk_3_S_out , clk_1_N_in , clk_1_S_in , clk_1_E_out , clk_1_W_out , + clk_2_N_in , clk_2_E_in , clk_2_S_in , clk_2_W_in , clk_2_W_out , + clk_2_S_out , clk_2_N_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , + clk_3_S_in , clk_3_N_in , clk_3_E_out , clk_3_W_out , clk_3_N_out , + clk_3_S_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input Test_en_S_in ; +output Test_en_N_out ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_N_out ; +output pReset_W_out ; +output pReset_E_out ; +input Reset_S_in ; +output Reset_N_out ; +input prog_clk_0_N_in ; +input prog_clk_1_N_in ; +input prog_clk_1_S_in ; +output prog_clk_1_E_out ; +output prog_clk_1_W_out ; +input prog_clk_2_N_in ; +input prog_clk_2_E_in ; +input prog_clk_2_S_in ; +input prog_clk_2_W_in ; +output prog_clk_2_W_out ; +output prog_clk_2_S_out ; +output prog_clk_2_N_out ; +output prog_clk_2_E_out ; +input prog_clk_3_W_in ; +input prog_clk_3_E_in ; +input prog_clk_3_S_in ; +input prog_clk_3_N_in ; +output prog_clk_3_E_out ; +output prog_clk_3_W_out ; +output prog_clk_3_N_out ; +output prog_clk_3_S_out ; +input clk_1_N_in ; +input clk_1_S_in ; +output clk_1_E_out ; +output clk_1_W_out ; +input clk_2_N_in ; +input clk_2_E_in ; +input clk_2_S_in ; +input clk_2_W_in ; +output clk_2_W_out ; +output clk_2_S_out ; +output clk_2_N_out ; +output clk_2_E_out ; +input clk_3_W_in ; +input clk_3_E_in ; +input clk_3_S_in ; +input clk_3_N_in ; +output clk_3_E_out ; +output clk_3_W_out ; +output clk_3_N_out ; +output clk_3_S_out ; +input VDD ; +input VSS ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_10_sram ; +wire [0:3] mux_tree_tapbuf_size10_11_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_9_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size11_0_sram ; +wire [0:3] mux_tree_tapbuf_size11_1_sram ; +wire [0:3] mux_tree_tapbuf_size11_2_sram ; +wire [0:3] mux_tree_tapbuf_size11_3_sram ; +wire [0:3] mux_tree_tapbuf_size11_4_sram ; +wire [0:3] mux_tree_tapbuf_size11_5_sram ; +wire [0:3] mux_tree_tapbuf_size11_6_sram ; +wire [0:3] mux_tree_tapbuf_size11_7_sram ; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_10_sram ; +wire [0:2] mux_tree_tapbuf_size6_11_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_7_sram ; +wire [0:2] mux_tree_tapbuf_size6_8_sram ; +wire [0:2] mux_tree_tapbuf_size6_9_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:3] mux_tree_tapbuf_size9_3_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_1_E_out = prog_clk_1_S_in ; +assign prog_clk_1_W_out = prog_clk_1_S_in ; +assign prog_clk_2_W_out = prog_clk_2_W_in ; +assign prog_clk_2_S_out = prog_clk_2_W_in ; +assign prog_clk_2_N_out = prog_clk_2_W_in ; +assign prog_clk_2_E_out = prog_clk_2_W_in ; +assign prog_clk_3_E_out = prog_clk_3_N_in ; +assign prog_clk_3_W_out = prog_clk_3_N_in ; +assign prog_clk_3_N_out = prog_clk_3_N_in ; +assign prog_clk_3_S_out = prog_clk_3_N_in ; +assign clk_1_E_out = clk_1_S_in ; +assign clk_1_W_out = clk_1_S_in ; +assign clk_2_W_out = clk_2_W_in ; +assign clk_2_S_out = clk_2_W_in ; +assign clk_2_N_out = clk_2_W_in ; +assign clk_2_E_out = clk_2_W_in ; +assign clk_3_E_out = clk_3_N_in ; +assign clk_3_W_out = clk_3_N_in ; +assign clk_3_N_out = clk_3_N_in ; +assign clk_3_S_out = clk_3_N_in ; +assign pReset_S_in = pReset_E_in ; +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_1_N_in = prog_clk_1_S_in ; +assign prog_clk_2_W_in = prog_clk_2_N_in ; +assign prog_clk_2_W_in = prog_clk_2_S_in ; +assign prog_clk_3_N_in = prog_clk_3_W_in ; +assign prog_clk_3_N_in = prog_clk_3_S_in ; +assign clk_1_N_in = clk_1_S_in ; +assign clk_2_W_in = clk_2_N_in ; +assign clk_2_W_in = clk_2_S_in ; +assign clk_3_N_in = clk_3_W_in ; +assign clk_3_N_in = clk_3_S_in ; +assign prog_clk_2_W_in = prog_clk_2_E_in ; +assign prog_clk_3_N_in = prog_clk_3_E_in ; +assign clk_2_W_in = clk_2_E_in ; +assign clk_3_N_in = clk_3_E_in ; + +sb_1__1__mux_tree_tapbuf_size11_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] , + chanx_left_out[20] , chany_top_out[4] , chany_top_out[20] , + chanx_left_in[0] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , + chanx_left_out[21] , chany_top_out[7] , chany_top_out[21] , + chanx_right_out[7] , chanx_right_out[21] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size11_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_2 mux_right_track_0 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chany_top_in[29] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_top_out[4] , chany_top_out[20] , + chany_bottom_in[25] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_3 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_bottom_out[7] , chany_bottom_out[21] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[7] , chany_top_out[21] , + chany_bottom_in[21] , chanx_right_out[7] , chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size11_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_4 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] , + chanx_left_out[20] , chanx_right_in[25] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[1] , chanx_right_out[4] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_5 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_left_out[7] , + chanx_left_out[21] , chanx_right_in[21] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[2] , chanx_right_out[7] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size11_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_6 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_bottom_out[20] , + chanx_left_out[4] , chanx_left_out[20] , chany_top_out[4] , + chany_top_out[20] , chany_bottom_in[29] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size11_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size11 mux_left_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chany_top_in[29] , + chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , + chany_top_out[7] , chany_top_out[21] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size11_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_1 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_2 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_3 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_4 mem_bottom_track_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_5 mem_bottom_track_3 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_0 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_right_in[4] , chanx_left_out[8] , chanx_left_out[23] , + chany_top_out[8] , chany_top_out[23] , chanx_right_out[8] , + chanx_right_out[23] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , + chanx_left_out[12] , chanx_right_in[13] , chanx_left_out[27] , + chany_top_out[12] , chany_top_out[27] , chanx_right_out[12] , + chanx_left_in[13] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_20 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , + chanx_left_out[13] , chanx_right_in[17] , chanx_left_out[28] , + chany_top_out[13] , chany_top_out[28] , chanx_left_in[9] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_bottom_out[8] , chany_bottom_out[23] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[8] , chany_bottom_in[17] , chany_top_out[23] , + chanx_right_out[8] , chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_12 ( + .in ( { chany_top_in[5] , chany_bottom_out[12] , chany_bottom_out[27] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[5] , chany_top_out[12] , chany_top_out[27] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_20 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[4] , chany_top_out[13] , chany_top_out[28] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_left_out[8] , + chanx_right_in[17] , chanx_left_out[23] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[4] , chanx_right_out[8] , chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_7 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[5] , + chanx_left_out[12] , chanx_left_out[27] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , + chanx_right_out[12] , chanx_left_in[13] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[4] , + chanx_left_out[13] , chanx_left_out[28] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , + chanx_right_out[13] , chanx_left_in[17] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chany_top_in[25] , + chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , + chany_top_out[8] , chany_top_out[23] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size10_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , + SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_13 ( + .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] , + chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] , + chany_top_out[12] , chany_top_out[27] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size10_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10 mux_left_track_21 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , + chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[9] , + chany_top_out[13] , chany_top_out[28] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size10_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , + SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_track_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_track_20 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_bottom_track_5 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_left_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , + chanx_right_in[5] , chanx_left_out[9] , chanx_left_out[24] , + chany_top_out[9] , chany_top_out[24] , chanx_right_out[9] , + chanx_left_in[21] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , + SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , + chanx_right_in[9] , chanx_left_out[11] , chanx_left_out[25] , + chany_top_out[11] , chany_top_out[25] , chanx_right_out[11] , + chanx_left_in[17] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , + SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_bottom_out[9] , chany_bottom_out[24] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , + chany_top_out[9] , chany_bottom_in[13] , chany_top_out[24] , + chanx_right_out[9] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , + SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_10 ( + .in ( { chany_top_in[4] , chany_bottom_out[11] , chany_bottom_out[25] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[9] , chany_top_out[11] , chany_top_out[25] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , + SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_left_out[9] , + chanx_right_in[13] , chanx_left_out[24] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_right_out[9] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , + SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[9] , + chanx_left_out[11] , chanx_left_out[25] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[9] , chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , + SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_7 ( + .in ( { chany_bottom_out[9] , chany_top_in[21] , chany_bottom_out[24] , + chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , + chany_top_out[9] , chany_top_out[24] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , + SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( { ropt_net_182 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size12 mux_left_track_11 ( + .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] , + chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] , + chany_top_out[11] , chany_top_out[25] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , + SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_track_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_bottom_track_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size9_0 mux_top_track_28 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_out[15] , + chanx_right_in[21] , chanx_left_out[29] , chany_top_out[15] , + chany_top_out[29] , chanx_left_in[5] , chanx_right_out[15] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , + SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_1 mux_right_track_28 ( + .in ( { chany_top_in[13] , chany_bottom_out[15] , chany_bottom_out[29] , + right_bottom_grid_pin_38_[0] , chany_bottom_in[2] , + chany_top_out[15] , chany_top_out[29] , chanx_right_out[15] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , + SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_2 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , + chanx_left_out[15] , chanx_left_out[29] , + bottom_left_grid_pin_46_[0] , chanx_right_out[15] , + chanx_left_in[21] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , + SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size9 mux_left_track_29 ( + .in ( { chany_top_in[5] , chany_bottom_out[15] , chany_bottom_out[29] , + chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[13] , + chany_top_out[15] , chany_top_out[29] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size9_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , + SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_1 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_2 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_0 mux_top_track_36 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_out[16] , + chanx_right_in[25] , chany_top_out[16] , chanx_left_in[4] , + chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , + SYNOPSYS_UNCONNECTED_131 } ) , + .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , + chanx_right_in[29] , chany_top_out[17] , chanx_left_in[2] , + chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , + SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_2 mux_top_track_52 ( + .in ( { top_left_grid_pin_49_[0] , chanx_right_in[0] , + chanx_left_out[19] , chany_top_out[19] , chanx_left_in[1] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 , + SYNOPSYS_UNCONNECTED_137 } ) , + .out ( chany_top_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_3 mux_right_track_36 ( + .in ( { chany_bottom_out[16] , chany_top_in[17] , + right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , + chany_top_out[16] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_138 , SYNOPSYS_UNCONNECTED_139 , + SYNOPSYS_UNCONNECTED_140 } ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_4 mux_right_track_44 ( + .in ( { chany_bottom_out[17] , chany_top_in[21] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , + chany_top_out[17] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , + SYNOPSYS_UNCONNECTED_143 } ) , + .out ( { ZBUF_6_f_0 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_5 mux_right_track_52 ( + .in ( { chany_bottom_out[19] , chany_top_in[25] , + right_bottom_grid_pin_41_[0] , chany_top_out[19] , + chany_bottom_in[29] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_144 , SYNOPSYS_UNCONNECTED_145 , + SYNOPSYS_UNCONNECTED_146 } ) , + .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_6 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_left_out[16] , + bottom_left_grid_pin_47_[0] , chanx_right_out[16] , + chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 , + SYNOPSYS_UNCONNECTED_149 } ) , + .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_7 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_left_out[17] , + bottom_left_grid_pin_48_[0] , chanx_right_out[17] , + chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size6_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_150 , SYNOPSYS_UNCONNECTED_151 , + SYNOPSYS_UNCONNECTED_152 } ) , + .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_8 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , chanx_left_out[19] , chanx_right_in[29] , + bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , + SYNOPSYS_UNCONNECTED_155 } ) , + .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_9 mux_left_track_37 ( + .in ( { chany_top_in[4] , chany_bottom_out[16] , chanx_left_out[16] , + chany_top_out[16] , chany_bottom_in[17] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size6_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_156 , SYNOPSYS_UNCONNECTED_157 , + SYNOPSYS_UNCONNECTED_158 } ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_10 mux_left_track_45 ( + .in ( { chany_top_in[2] , chany_bottom_out[17] , chanx_left_out[17] , + chany_top_out[17] , chany_bottom_in[21] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size6_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 , + SYNOPSYS_UNCONNECTED_161 } ) , + .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6 mux_left_track_53 ( + .in ( { chany_top_in[1] , chany_bottom_out[19] , chanx_left_out[19] , + chany_top_out[19] , chany_bottom_in[25] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_162 , SYNOPSYS_UNCONNECTED_163 , + SYNOPSYS_UNCONNECTED_164 } ) , + .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_7 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_8 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_9 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_10 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_11_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , + .X ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , + .X ( net_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 Reset_N_FTB01 ( .A ( Reset_S_in ) , + .X ( Reset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_92__91 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_93__92 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_94__93 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_95__94 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_96__95 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_97__96 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_98__97 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_99__98 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_100__99 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_101__100 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_102__101 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_103__102 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_104__103 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_109__108 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_151 ( .A ( net_net_151 ) , + .X ( pReset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , + .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , + .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , + .HI ( optlc_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1350 ( .A ( ZBUF_6_f_0 ) , + .X ( chanx_right_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 ropt_mt_inst_1370 ( .A ( ropt_net_182 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v new file mode 100644 index 0000000..de0aa55 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v @@ -0,0 +1,4120 @@ +// +// +// +// +// +// +module sb_1__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_150 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_149 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_149 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_147 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_147 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_145 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_155 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_143 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_141 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_140 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_138 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_136 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_134 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_132 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_130 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_128 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_127 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_153 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_176 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1366 ( .A ( copt_net_175 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_174 ) , + .X ( copt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( ropt_net_181 ) , + .X ( copt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( ccff_head[0] ) , + .X ( copt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( ropt_net_183 ) , + .X ( copt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( ropt_net_178 ) , + .X ( copt_net_176 ) ) ; +sky130_fd_sc_hd__buf_4 ropt_h_inst_1371 ( .A ( ropt_net_180 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( copt_net_173 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1368 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1369 ( .A ( copt_net_172 ) , + .X ( ropt_net_181 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_125 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_124 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .Y ( BUF_net_123 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .Y ( BUF_net_121 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_36_ , + right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , + right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , + right_bottom_grid_pin_41_ , right_bottom_grid_pin_42_ , + right_bottom_grid_pin_43_ , chany_bottom_in , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ , + bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in , + Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , + pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , + prog_clk_1_N_in , prog_clk_1_S_in , prog_clk_1_E_out , prog_clk_1_W_out , + prog_clk_2_N_in , prog_clk_2_E_in , prog_clk_2_S_in , prog_clk_2_W_in , + prog_clk_2_W_out , prog_clk_2_S_out , prog_clk_2_N_out , + prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_S_in , + prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out , prog_clk_3_N_out , + prog_clk_3_S_out , clk_1_N_in , clk_1_S_in , clk_1_E_out , clk_1_W_out , + clk_2_N_in , clk_2_E_in , clk_2_S_in , clk_2_W_in , clk_2_W_out , + clk_2_S_out , clk_2_N_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , + clk_3_S_in , clk_3_N_in , clk_3_E_out , clk_3_W_out , clk_3_N_out , + clk_3_S_out ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input Test_en_S_in ; +output Test_en_N_out ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_N_out ; +output pReset_W_out ; +output pReset_E_out ; +input Reset_S_in ; +output Reset_N_out ; +input prog_clk_0_N_in ; +input prog_clk_1_N_in ; +input prog_clk_1_S_in ; +output prog_clk_1_E_out ; +output prog_clk_1_W_out ; +input prog_clk_2_N_in ; +input prog_clk_2_E_in ; +input prog_clk_2_S_in ; +input prog_clk_2_W_in ; +output prog_clk_2_W_out ; +output prog_clk_2_S_out ; +output prog_clk_2_N_out ; +output prog_clk_2_E_out ; +input prog_clk_3_W_in ; +input prog_clk_3_E_in ; +input prog_clk_3_S_in ; +input prog_clk_3_N_in ; +output prog_clk_3_E_out ; +output prog_clk_3_W_out ; +output prog_clk_3_N_out ; +output prog_clk_3_S_out ; +input clk_1_N_in ; +input clk_1_S_in ; +output clk_1_E_out ; +output clk_1_W_out ; +input clk_2_N_in ; +input clk_2_E_in ; +input clk_2_S_in ; +input clk_2_W_in ; +output clk_2_W_out ; +output clk_2_S_out ; +output clk_2_N_out ; +output clk_2_E_out ; +input clk_3_W_in ; +input clk_3_E_in ; +input clk_3_S_in ; +input clk_3_N_in ; +output clk_3_E_out ; +output clk_3_W_out ; +output clk_3_N_out ; +output clk_3_S_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_10_sram ; +wire [0:3] mux_tree_tapbuf_size10_11_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_9_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size11_0_sram ; +wire [0:3] mux_tree_tapbuf_size11_1_sram ; +wire [0:3] mux_tree_tapbuf_size11_2_sram ; +wire [0:3] mux_tree_tapbuf_size11_3_sram ; +wire [0:3] mux_tree_tapbuf_size11_4_sram ; +wire [0:3] mux_tree_tapbuf_size11_5_sram ; +wire [0:3] mux_tree_tapbuf_size11_6_sram ; +wire [0:3] mux_tree_tapbuf_size11_7_sram ; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_10_sram ; +wire [0:2] mux_tree_tapbuf_size6_11_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_7_sram ; +wire [0:2] mux_tree_tapbuf_size6_8_sram ; +wire [0:2] mux_tree_tapbuf_size6_9_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:3] mux_tree_tapbuf_size9_3_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail ; + +assign prog_clk_1_E_out = prog_clk_1_S_in ; +assign prog_clk_1_W_out = prog_clk_1_S_in ; +assign prog_clk_2_W_out = prog_clk_2_W_in ; +assign prog_clk_2_S_out = prog_clk_2_W_in ; +assign prog_clk_2_N_out = prog_clk_2_W_in ; +assign prog_clk_2_E_out = prog_clk_2_W_in ; +assign prog_clk_3_E_out = prog_clk_3_N_in ; +assign prog_clk_3_W_out = prog_clk_3_N_in ; +assign prog_clk_3_N_out = prog_clk_3_N_in ; +assign prog_clk_3_S_out = prog_clk_3_N_in ; +assign clk_1_E_out = clk_1_S_in ; +assign clk_1_W_out = clk_1_S_in ; +assign clk_2_W_out = clk_2_W_in ; +assign clk_2_S_out = clk_2_W_in ; +assign clk_2_N_out = clk_2_W_in ; +assign clk_2_E_out = clk_2_W_in ; +assign clk_3_E_out = clk_3_N_in ; +assign clk_3_W_out = clk_3_N_in ; +assign clk_3_N_out = clk_3_N_in ; +assign clk_3_S_out = clk_3_N_in ; +assign pReset_E_in = pReset_S_in ; +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_1_S_in = prog_clk_1_N_in ; +assign prog_clk_2_N_in = prog_clk_2_W_in ; +assign prog_clk_2_S_in = prog_clk_2_W_in ; +assign prog_clk_3_W_in = prog_clk_3_N_in ; +assign prog_clk_3_S_in = prog_clk_3_N_in ; +assign clk_1_S_in = clk_1_N_in ; +assign clk_2_N_in = clk_2_W_in ; +assign clk_2_S_in = clk_2_W_in ; +assign clk_3_W_in = clk_3_N_in ; +assign clk_3_S_in = clk_3_N_in ; +assign prog_clk_2_E_in = prog_clk_2_W_in ; +assign prog_clk_3_E_in = prog_clk_3_N_in ; +assign clk_2_E_in = clk_2_W_in ; +assign clk_3_E_in = clk_3_N_in ; + +sb_1__1__mux_tree_tapbuf_size11_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] , + chanx_left_out[20] , chany_top_out[4] , chany_top_out[20] , + chanx_left_in[0] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , + chanx_left_out[21] , chany_top_out[7] , chany_top_out[21] , + chanx_right_out[7] , chanx_right_out[21] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size11_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_2 mux_right_track_0 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chany_top_in[29] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_top_out[4] , chany_top_out[20] , + chany_bottom_in[25] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_3 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_bottom_out[7] , chany_bottom_out[21] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[7] , chany_top_out[21] , + chany_bottom_in[21] , chanx_right_out[7] , chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size11_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_4 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] , + chanx_left_out[20] , chanx_right_in[25] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[1] , chanx_right_out[4] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_5 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_left_out[7] , + chanx_left_out[21] , chanx_right_in[21] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[2] , chanx_right_out[7] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size11_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_6 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_bottom_out[20] , + chanx_left_out[4] , chanx_left_out[20] , chany_top_out[4] , + chany_top_out[20] , chany_bottom_in[29] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size11_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size11 mux_left_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chany_top_in[29] , + chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , + chany_top_out[7] , chany_top_out[21] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size11_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_1 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_2 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_3 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_4 mem_bottom_track_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_5 mem_bottom_track_3 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_0 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_right_in[4] , chanx_left_out[8] , chanx_left_out[23] , + chany_top_out[8] , chany_top_out[23] , chanx_right_out[8] , + chanx_right_out[23] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , + chanx_left_out[12] , chanx_right_in[13] , chanx_left_out[27] , + chany_top_out[12] , chany_top_out[27] , chanx_right_out[12] , + chanx_left_in[13] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_20 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , + chanx_left_out[13] , chanx_right_in[17] , chanx_left_out[28] , + chany_top_out[13] , chany_top_out[28] , chanx_left_in[9] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_bottom_out[8] , chany_bottom_out[23] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[8] , chany_bottom_in[17] , chany_top_out[23] , + chanx_right_out[8] , chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_12 ( + .in ( { chany_top_in[5] , chany_bottom_out[12] , chany_bottom_out[27] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[5] , chany_top_out[12] , chany_top_out[27] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_20 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[4] , chany_top_out[13] , chany_top_out[28] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_left_out[8] , + chanx_right_in[17] , chanx_left_out[23] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[4] , chanx_right_out[8] , chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_7 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[5] , + chanx_left_out[12] , chanx_left_out[27] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , + chanx_right_out[12] , chanx_left_in[13] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[4] , + chanx_left_out[13] , chanx_left_out[28] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , + chanx_right_out[13] , chanx_left_in[17] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chany_top_in[25] , + chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , + chany_top_out[8] , chany_top_out[23] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size10_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , + SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_13 ( + .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] , + chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] , + chany_top_out[12] , chany_top_out[27] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size10_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10 mux_left_track_21 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , + chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[9] , + chany_top_out[13] , chany_top_out[28] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size10_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , + SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_track_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_track_20 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_bottom_track_5 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_left_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , + chanx_right_in[5] , chanx_left_out[9] , chanx_left_out[24] , + chany_top_out[9] , chany_top_out[24] , chanx_right_out[9] , + chanx_left_in[21] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , + SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , + chanx_right_in[9] , chanx_left_out[11] , chanx_left_out[25] , + chany_top_out[11] , chany_top_out[25] , chanx_right_out[11] , + chanx_left_in[17] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , + SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_bottom_out[9] , chany_bottom_out[24] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , + chany_top_out[9] , chany_bottom_in[13] , chany_top_out[24] , + chanx_right_out[9] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , + SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_10 ( + .in ( { chany_top_in[4] , chany_bottom_out[11] , chany_bottom_out[25] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[9] , chany_top_out[11] , chany_top_out[25] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , + SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_left_out[9] , + chanx_right_in[13] , chanx_left_out[24] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_right_out[9] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , + SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[9] , + chanx_left_out[11] , chanx_left_out[25] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[9] , chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , + SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_7 ( + .in ( { chany_bottom_out[9] , chany_top_in[21] , chany_bottom_out[24] , + chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , + chany_top_out[9] , chany_top_out[24] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , + SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( { ropt_net_182 } ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size12 mux_left_track_11 ( + .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] , + chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] , + chany_top_out[11] , chany_top_out[25] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , + SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_track_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_bottom_track_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_0 mux_top_track_28 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_out[15] , + chanx_right_in[21] , chanx_left_out[29] , chany_top_out[15] , + chany_top_out[29] , chanx_left_in[5] , chanx_right_out[15] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , + SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_1 mux_right_track_28 ( + .in ( { chany_top_in[13] , chany_bottom_out[15] , chany_bottom_out[29] , + right_bottom_grid_pin_38_[0] , chany_bottom_in[2] , + chany_top_out[15] , chany_top_out[29] , chanx_right_out[15] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , + SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_2 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , + chanx_left_out[15] , chanx_left_out[29] , + bottom_left_grid_pin_46_[0] , chanx_right_out[15] , + chanx_left_in[21] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , + SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size9 mux_left_track_29 ( + .in ( { chany_top_in[5] , chany_bottom_out[15] , chany_bottom_out[29] , + chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[13] , + chany_top_out[15] , chany_top_out[29] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size9_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , + SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_1 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_2 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_0 mux_top_track_36 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_out[16] , + chanx_right_in[25] , chany_top_out[16] , chanx_left_in[4] , + chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , + SYNOPSYS_UNCONNECTED_131 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , + chanx_right_in[29] , chany_top_out[17] , chanx_left_in[2] , + chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , + SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_2 mux_top_track_52 ( + .in ( { top_left_grid_pin_49_[0] , chanx_right_in[0] , + chanx_left_out[19] , chany_top_out[19] , chanx_left_in[1] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 , + SYNOPSYS_UNCONNECTED_137 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_3 mux_right_track_36 ( + .in ( { chany_bottom_out[16] , chany_top_in[17] , + right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , + chany_top_out[16] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_138 , SYNOPSYS_UNCONNECTED_139 , + SYNOPSYS_UNCONNECTED_140 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_4 mux_right_track_44 ( + .in ( { chany_bottom_out[17] , chany_top_in[21] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , + chany_top_out[17] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , + SYNOPSYS_UNCONNECTED_143 } ) , + .out ( { ZBUF_6_f_0 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_5 mux_right_track_52 ( + .in ( { chany_bottom_out[19] , chany_top_in[25] , + right_bottom_grid_pin_41_[0] , chany_top_out[19] , + chany_bottom_in[29] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_144 , SYNOPSYS_UNCONNECTED_145 , + SYNOPSYS_UNCONNECTED_146 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_6 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_left_out[16] , + bottom_left_grid_pin_47_[0] , chanx_right_out[16] , + chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 , + SYNOPSYS_UNCONNECTED_149 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_7 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_left_out[17] , + bottom_left_grid_pin_48_[0] , chanx_right_out[17] , + chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size6_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_150 , SYNOPSYS_UNCONNECTED_151 , + SYNOPSYS_UNCONNECTED_152 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_8 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , chanx_left_out[19] , chanx_right_in[29] , + bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , + SYNOPSYS_UNCONNECTED_155 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_9 mux_left_track_37 ( + .in ( { chany_top_in[4] , chany_bottom_out[16] , chanx_left_out[16] , + chany_top_out[16] , chany_bottom_in[17] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size6_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_156 , SYNOPSYS_UNCONNECTED_157 , + SYNOPSYS_UNCONNECTED_158 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_10 mux_left_track_45 ( + .in ( { chany_top_in[2] , chany_bottom_out[17] , chanx_left_out[17] , + chany_top_out[17] , chany_bottom_in[21] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size6_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 , + SYNOPSYS_UNCONNECTED_161 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6 mux_left_track_53 ( + .in ( { chany_top_in[1] , chany_bottom_out[19] , chanx_left_out[19] , + chany_top_out[19] , chany_bottom_in[25] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_162 , SYNOPSYS_UNCONNECTED_163 , + SYNOPSYS_UNCONNECTED_164 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_7 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_8 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_8_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_9 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_9_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_10 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_10_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_11_sram ) ) ; +sky130_fd_sc_hd__buf_4 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , + .X ( net_net_151 ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_6 Reset_N_FTB01 ( .A ( Reset_S_in ) , + .X ( Reset_N_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_92__91 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_93__92 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_94__93 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_95__94 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_96__95 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_97__96 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_98__97 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_99__98 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_100__99 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_101__100 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_102__101 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_103__102 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_104__103 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_109__108 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_151 ( .A ( net_net_151 ) , + .X ( pReset_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1350 ( .A ( ZBUF_6_f_0 ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_4 ropt_mt_inst_1370 ( .A ( ropt_net_182 ) , + .X ( chanx_left_out[3] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..a1ee526 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__1__icv_in_design.top_only.pt.v @@ -0,0 +1,1057 @@ +// +// +// +// +// +// +module sb_1__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_36_ , + right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , + right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , + right_bottom_grid_pin_41_ , right_bottom_grid_pin_42_ , + right_bottom_grid_pin_43_ , chany_bottom_in , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ , + bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in , + Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , + pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , + prog_clk_1_N_in , prog_clk_1_S_in , prog_clk_1_E_out , prog_clk_1_W_out , + prog_clk_2_N_in , prog_clk_2_E_in , prog_clk_2_S_in , prog_clk_2_W_in , + prog_clk_2_W_out , prog_clk_2_S_out , prog_clk_2_N_out , + prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_S_in , + prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out , prog_clk_3_N_out , + prog_clk_3_S_out , clk_1_N_in , clk_1_S_in , clk_1_E_out , clk_1_W_out , + clk_2_N_in , clk_2_E_in , clk_2_S_in , clk_2_W_in , clk_2_W_out , + clk_2_S_out , clk_2_N_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , + clk_3_S_in , clk_3_N_in , clk_3_E_out , clk_3_W_out , clk_3_N_out , + clk_3_S_out ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input Test_en_S_in ; +output Test_en_N_out ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_N_out ; +output pReset_W_out ; +output pReset_E_out ; +input Reset_S_in ; +output Reset_N_out ; +input prog_clk_0_N_in ; +input prog_clk_1_N_in ; +input prog_clk_1_S_in ; +output prog_clk_1_E_out ; +output prog_clk_1_W_out ; +input prog_clk_2_N_in ; +input prog_clk_2_E_in ; +input prog_clk_2_S_in ; +input prog_clk_2_W_in ; +output prog_clk_2_W_out ; +output prog_clk_2_S_out ; +output prog_clk_2_N_out ; +output prog_clk_2_E_out ; +input prog_clk_3_W_in ; +input prog_clk_3_E_in ; +input prog_clk_3_S_in ; +input prog_clk_3_N_in ; +output prog_clk_3_E_out ; +output prog_clk_3_W_out ; +output prog_clk_3_N_out ; +output prog_clk_3_S_out ; +input clk_1_N_in ; +input clk_1_S_in ; +output clk_1_E_out ; +output clk_1_W_out ; +input clk_2_N_in ; +input clk_2_E_in ; +input clk_2_S_in ; +input clk_2_W_in ; +output clk_2_W_out ; +output clk_2_S_out ; +output clk_2_N_out ; +output clk_2_E_out ; +input clk_3_W_in ; +input clk_3_E_in ; +input clk_3_S_in ; +input clk_3_N_in ; +output clk_3_E_out ; +output clk_3_W_out ; +output clk_3_N_out ; +output clk_3_S_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_10_sram ; +wire [0:3] mux_tree_tapbuf_size10_11_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_9_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size11_0_sram ; +wire [0:3] mux_tree_tapbuf_size11_1_sram ; +wire [0:3] mux_tree_tapbuf_size11_2_sram ; +wire [0:3] mux_tree_tapbuf_size11_3_sram ; +wire [0:3] mux_tree_tapbuf_size11_4_sram ; +wire [0:3] mux_tree_tapbuf_size11_5_sram ; +wire [0:3] mux_tree_tapbuf_size11_6_sram ; +wire [0:3] mux_tree_tapbuf_size11_7_sram ; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_10_sram ; +wire [0:2] mux_tree_tapbuf_size6_11_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_7_sram ; +wire [0:2] mux_tree_tapbuf_size6_8_sram ; +wire [0:2] mux_tree_tapbuf_size6_9_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:3] mux_tree_tapbuf_size9_3_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail ; + +assign prog_clk_1_E_out = prog_clk_1_S_in ; +assign prog_clk_1_W_out = prog_clk_1_S_in ; +assign prog_clk_2_W_out = prog_clk_2_W_in ; +assign prog_clk_2_S_out = prog_clk_2_W_in ; +assign prog_clk_2_N_out = prog_clk_2_W_in ; +assign prog_clk_2_E_out = prog_clk_2_W_in ; +assign prog_clk_3_E_out = prog_clk_3_N_in ; +assign prog_clk_3_W_out = prog_clk_3_N_in ; +assign prog_clk_3_N_out = prog_clk_3_N_in ; +assign prog_clk_3_S_out = prog_clk_3_N_in ; +assign clk_1_E_out = clk_1_S_in ; +assign clk_1_W_out = clk_1_S_in ; +assign clk_2_W_out = clk_2_W_in ; +assign clk_2_S_out = clk_2_W_in ; +assign clk_2_N_out = clk_2_W_in ; +assign clk_2_E_out = clk_2_W_in ; +assign clk_3_E_out = clk_3_N_in ; +assign clk_3_W_out = clk_3_N_in ; +assign clk_3_N_out = clk_3_N_in ; +assign clk_3_S_out = clk_3_N_in ; +assign pReset_E_in = pReset_S_in ; +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_1_S_in = prog_clk_1_N_in ; +assign prog_clk_2_N_in = prog_clk_2_W_in ; +assign prog_clk_2_S_in = prog_clk_2_W_in ; +assign prog_clk_3_W_in = prog_clk_3_N_in ; +assign prog_clk_3_S_in = prog_clk_3_N_in ; +assign clk_1_S_in = clk_1_N_in ; +assign clk_2_N_in = clk_2_W_in ; +assign clk_2_S_in = clk_2_W_in ; +assign clk_3_W_in = clk_3_N_in ; +assign clk_3_S_in = clk_3_N_in ; +assign prog_clk_2_E_in = prog_clk_2_W_in ; +assign prog_clk_3_E_in = prog_clk_3_N_in ; +assign clk_2_E_in = clk_2_W_in ; +assign clk_3_E_in = clk_3_N_in ; + +sb_1__1__mux_tree_tapbuf_size11_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] , + chanx_left_out[20] , chany_top_out[4] , chany_top_out[20] , + chanx_left_in[0] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , + chanx_left_out[21] , chany_top_out[7] , chany_top_out[21] , + chanx_right_out[7] , chanx_right_out[21] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size11_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_2 mux_right_track_0 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chany_top_in[29] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_top_out[4] , chany_top_out[20] , + chany_bottom_in[25] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_3 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_bottom_out[7] , chany_bottom_out[21] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[7] , chany_top_out[21] , + chany_bottom_in[21] , chanx_right_out[7] , chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size11_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_4 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] , + chanx_left_out[20] , chanx_right_in[25] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[1] , chanx_right_out[4] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_5 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_left_out[7] , + chanx_left_out[21] , chanx_right_in[21] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[2] , chanx_right_out[7] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size11_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_6 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_bottom_out[20] , + chanx_left_out[4] , chanx_left_out[20] , chany_top_out[4] , + chany_top_out[20] , chany_bottom_in[29] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size11_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size11 mux_left_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chany_top_in[29] , + chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , + chany_top_out[7] , chany_top_out[21] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size11_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_1 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_2 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_3 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_4 mem_bottom_track_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_5 mem_bottom_track_3 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_0 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_right_in[4] , chanx_left_out[8] , chanx_left_out[23] , + chany_top_out[8] , chany_top_out[23] , chanx_right_out[8] , + chanx_right_out[23] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , + chanx_left_out[12] , chanx_right_in[13] , chanx_left_out[27] , + chany_top_out[12] , chany_top_out[27] , chanx_right_out[12] , + chanx_left_in[13] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_20 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , + chanx_left_out[13] , chanx_right_in[17] , chanx_left_out[28] , + chany_top_out[13] , chany_top_out[28] , chanx_left_in[9] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_bottom_out[8] , chany_bottom_out[23] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[8] , chany_bottom_in[17] , chany_top_out[23] , + chanx_right_out[8] , chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_12 ( + .in ( { chany_top_in[5] , chany_bottom_out[12] , chany_bottom_out[27] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[5] , chany_top_out[12] , chany_top_out[27] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_20 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[4] , chany_top_out[13] , chany_top_out[28] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_left_out[8] , + chanx_right_in[17] , chanx_left_out[23] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[4] , chanx_right_out[8] , chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_7 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[5] , + chanx_left_out[12] , chanx_left_out[27] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , + chanx_right_out[12] , chanx_left_in[13] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[4] , + chanx_left_out[13] , chanx_left_out[28] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , + chanx_right_out[13] , chanx_left_in[17] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chany_top_in[25] , + chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , + chany_top_out[8] , chany_top_out[23] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size10_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , + SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_13 ( + .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] , + chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] , + chany_top_out[12] , chany_top_out[27] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size10_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10 mux_left_track_21 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , + chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[9] , + chany_top_out[13] , chany_top_out[28] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size10_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , + SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_track_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_track_20 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_bottom_track_5 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_left_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , + chanx_right_in[5] , chanx_left_out[9] , chanx_left_out[24] , + chany_top_out[9] , chany_top_out[24] , chanx_right_out[9] , + chanx_left_in[21] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , + SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , + chanx_right_in[9] , chanx_left_out[11] , chanx_left_out[25] , + chany_top_out[11] , chany_top_out[25] , chanx_right_out[11] , + chanx_left_in[17] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , + SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_bottom_out[9] , chany_bottom_out[24] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , + chany_top_out[9] , chany_bottom_in[13] , chany_top_out[24] , + chanx_right_out[9] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , + SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_10 ( + .in ( { chany_top_in[4] , chany_bottom_out[11] , chany_bottom_out[25] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[9] , chany_top_out[11] , chany_top_out[25] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , + SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_left_out[9] , + chanx_right_in[13] , chanx_left_out[24] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_right_out[9] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , + SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[9] , + chanx_left_out[11] , chanx_left_out[25] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[9] , chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , + SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_7 ( + .in ( { chany_bottom_out[9] , chany_top_in[21] , chany_bottom_out[24] , + chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , + chany_top_out[9] , chany_top_out[24] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , + SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( { ropt_net_182 } ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size12 mux_left_track_11 ( + .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] , + chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] , + chany_top_out[11] , chany_top_out[25] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , + SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_track_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_bottom_track_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_0 mux_top_track_28 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_out[15] , + chanx_right_in[21] , chanx_left_out[29] , chany_top_out[15] , + chany_top_out[29] , chanx_left_in[5] , chanx_right_out[15] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , + SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_1 mux_right_track_28 ( + .in ( { chany_top_in[13] , chany_bottom_out[15] , chany_bottom_out[29] , + right_bottom_grid_pin_38_[0] , chany_bottom_in[2] , + chany_top_out[15] , chany_top_out[29] , chanx_right_out[15] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , + SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_2 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , + chanx_left_out[15] , chanx_left_out[29] , + bottom_left_grid_pin_46_[0] , chanx_right_out[15] , + chanx_left_in[21] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , + SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size9 mux_left_track_29 ( + .in ( { chany_top_in[5] , chany_bottom_out[15] , chany_bottom_out[29] , + chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[13] , + chany_top_out[15] , chany_top_out[29] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size9_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , + SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_1 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_2 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_0 mux_top_track_36 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_out[16] , + chanx_right_in[25] , chany_top_out[16] , chanx_left_in[4] , + chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , + SYNOPSYS_UNCONNECTED_131 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , + chanx_right_in[29] , chany_top_out[17] , chanx_left_in[2] , + chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , + SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_2 mux_top_track_52 ( + .in ( { top_left_grid_pin_49_[0] , chanx_right_in[0] , + chanx_left_out[19] , chany_top_out[19] , chanx_left_in[1] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 , + SYNOPSYS_UNCONNECTED_137 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_3 mux_right_track_36 ( + .in ( { chany_bottom_out[16] , chany_top_in[17] , + right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , + chany_top_out[16] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_138 , SYNOPSYS_UNCONNECTED_139 , + SYNOPSYS_UNCONNECTED_140 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_4 mux_right_track_44 ( + .in ( { chany_bottom_out[17] , chany_top_in[21] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , + chany_top_out[17] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , + SYNOPSYS_UNCONNECTED_143 } ) , + .out ( { ZBUF_6_f_0 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_5 mux_right_track_52 ( + .in ( { chany_bottom_out[19] , chany_top_in[25] , + right_bottom_grid_pin_41_[0] , chany_top_out[19] , + chany_bottom_in[29] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_144 , SYNOPSYS_UNCONNECTED_145 , + SYNOPSYS_UNCONNECTED_146 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_6 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_left_out[16] , + bottom_left_grid_pin_47_[0] , chanx_right_out[16] , + chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 , + SYNOPSYS_UNCONNECTED_149 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_7 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_left_out[17] , + bottom_left_grid_pin_48_[0] , chanx_right_out[17] , + chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size6_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_150 , SYNOPSYS_UNCONNECTED_151 , + SYNOPSYS_UNCONNECTED_152 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_8 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , chanx_left_out[19] , chanx_right_in[29] , + bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , + SYNOPSYS_UNCONNECTED_155 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_9 mux_left_track_37 ( + .in ( { chany_top_in[4] , chany_bottom_out[16] , chanx_left_out[16] , + chany_top_out[16] , chany_bottom_in[17] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size6_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_156 , SYNOPSYS_UNCONNECTED_157 , + SYNOPSYS_UNCONNECTED_158 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_10 mux_left_track_45 ( + .in ( { chany_top_in[2] , chany_bottom_out[17] , chanx_left_out[17] , + chany_top_out[17] , chany_bottom_in[21] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size6_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 , + SYNOPSYS_UNCONNECTED_161 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6 mux_left_track_53 ( + .in ( { chany_top_in[1] , chany_bottom_out[19] , chanx_left_out[19] , + chany_top_out[19] , chany_bottom_in[25] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_162 , SYNOPSYS_UNCONNECTED_163 , + SYNOPSYS_UNCONNECTED_164 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_7 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_8 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_8_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_9 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_9_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_10 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_10_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_11_sram ) ) ; +sky130_fd_sc_hd__buf_4 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , + .X ( net_net_151 ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_6 Reset_N_FTB01 ( .A ( Reset_S_in ) , + .X ( Reset_N_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_92__91 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_93__92 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_94__93 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_95__94 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_96__95 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_97__96 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_98__97 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_99__98 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_100__99 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_101__100 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_102__101 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_103__102 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_104__103 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_109__108 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_151 ( .A ( net_net_151 ) , + .X ( pReset_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1350 ( .A ( ZBUF_6_f_0 ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_4 ropt_mt_inst_1370 ( .A ( ropt_net_182 ) , + .X ( chanx_left_out[3] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v new file mode 100644 index 0000000..1dcc149 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v @@ -0,0 +1,3820 @@ +// +// +// +// +// +// +module sb_1__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_46 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_46 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_45 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_45 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_44 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_44 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_43 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_42 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_41 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_134 ) ) ; +endmodule + + +module sb_1__2__const1_40 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_132 ) ) ; +endmodule + + +module sb_1__2__const1_39 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_130 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_38 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_129 ) ) ; +endmodule + + +module sb_1__2__const1_37 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_127 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1_36 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__2__const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_35 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__2__const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_34 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__2__const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_125 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_33 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__2__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_124 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1_32 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__2__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_122 ) ) ; +endmodule + + +module sb_1__2__const1_31 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__2__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_120 ) ) ; +endmodule + + +module sb_1__2__const1_30 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__2__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_118 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_29 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__2__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_117 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( copt_net_158 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( mem_out[2] ) , + .X ( copt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_153 ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_154 ) , + .X ( copt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_155 ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1_28 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_27 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_26 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_115 ) ) ; +endmodule + + +module sb_1__2__const1_25 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) ) ; +endmodule + + +module sb_1__2__const1_24 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_145 ) ) ; +endmodule + + +module sb_1__2__const1_23 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_111 ) ) ; +endmodule + + +module sb_1__2__const1_22 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_21 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1_20 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__2__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_19 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__2__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_108 ) ) ; +endmodule + + +module sb_1__2__const1_18 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__2__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_17 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__2__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_143 ) ) ; +endmodule + + +module sb_1__2__const1_16 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__2__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1_15 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__2__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_105 ) ) ; +endmodule + + +module sb_1__2__const1_14 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__2__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1_13 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__2__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_141 ) ) ; +endmodule + + +module sb_1__2__const1_12 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__2__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_103 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1_11 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_1__2__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_102 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_10 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_1__2__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_9 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_1__2__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_187 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1415 ( .A ( ccff_head[0] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1416 ( .A ( ropt_net_182 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1417 ( .A ( ropt_net_185 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1418 ( .A ( ropt_net_183 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1419 ( .A ( ropt_net_184 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1420 ( .A ( ropt_net_186 ) , + .X ( ropt_net_187 ) ) ; +endmodule + + +module sb_1__2__const1_8 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module sb_1__2__const1_7 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_99 ) ) ; +endmodule + + +module sb_1__2__const1_6 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_97 ) ) ; +endmodule + + +module sb_1__2__const1_5 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_4 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_3 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_2 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_1__2__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_1__2__const1_0 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_139 ) ) ; +endmodule + + +module sb_1__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , + bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT , + pReset_S_in , pReset_E_in , pReset_W_in , pReset_W_out , pReset_E_out , + prog_clk_0_S_in ) ; +input [0:0] pReset ; +input [0:29] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_BOT ; +output SC_OUT_BOT ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_E_out ; +input prog_clk_0_S_in ; + +wire ropt_net_166 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; + +assign pReset_S_in = pReset_E_in ; +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; + +sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[9] , + chany_bottom_in[20] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[8] , + chany_bottom_in[19] , chanx_right_out[7] , chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , + chanx_right_out[15] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 ( + .in ( { chanx_left_out[4] , chanx_left_out[20] , chany_bottom_in[10] , + chany_bottom_in[21] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 ( + .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] , + chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 ( + .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] , + chany_bottom_in[16] , chany_bottom_in[27] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 ( + .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] , + chany_bottom_in[17] , chany_bottom_in[28] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_7 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_4 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[7] , + chany_bottom_in[18] , chany_bottom_in[29] , chanx_right_out[8] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 ( + .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , + chany_bottom_in[11] , chany_bottom_in[22] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , + SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 ( + .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , + chany_bottom_in[12] , chany_bottom_in[23] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , + SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem_1 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size10_0 mux_right_track_6 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[6] , + chany_bottom_in[17] , chany_bottom_in[28] , chanx_right_out[9] , + chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 ( + .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , + chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_41_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , + SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , + SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 ( + .in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] , + chany_bottom_in[14] , chany_bottom_in[25] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_0 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , + chany_bottom_in[12] , chany_bottom_in[23] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_1 mux_right_track_44 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , + chany_bottom_in[11] , chany_bottom_in[22] , ropt_net_166 } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_2 mux_bottom_track_5 ( + .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 ( + .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_right_out[12] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size5 mux_left_track_37 ( + .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] , + chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_1 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_0 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[10] , + chany_bottom_in[21] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 , + SYNOPSYS_UNCONNECTED_73 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_13 ( + .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] , + chanx_right_out[13] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , + SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_2 mux_bottom_track_15 ( + .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] , + chanx_right_out[15] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , + SYNOPSYS_UNCONNECTED_79 } ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_3 mux_bottom_track_17 ( + .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] , + chanx_right_out[16] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 , + SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_4 mux_bottom_track_19 ( + .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , ropt_net_166 , + chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , + SYNOPSYS_UNCONNECTED_85 } ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_5 mux_bottom_track_37 ( + .in ( { chanx_left_out[29] , chanx_right_in[29] , + bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , + SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_6 mux_left_track_45 ( + .in ( { chanx_left_out[17] , chany_bottom_in[8] , chany_bottom_in[19] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , + SYNOPSYS_UNCONNECTED_91 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size4 mux_left_track_53 ( + .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 , + SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_15 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_17 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_19 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .in ( { chanx_left_out[4] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[1] , chanx_right_out[4] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 , + SYNOPSYS_UNCONNECTED_97 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 ( + .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[2] , chanx_right_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , + SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 ( + .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_right_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , + SYNOPSYS_UNCONNECTED_103 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 ( + .in ( { chanx_left_out[11] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[9] , chanx_right_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , + SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_21 ( + .in ( { chanx_left_out[19] , bottom_left_grid_pin_48_[0] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_23 ( + .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_25 ( + .in ( { chanx_left_out[21] , bottom_left_grid_pin_50_[0] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_27 ( + .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_23 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_25 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_0 mux_bottom_track_29 ( + .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_1 mux_bottom_track_31 ( + .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_2 mux_bottom_track_33 ( + .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_3 mux_bottom_track_35 ( + .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_4 mux_bottom_track_39 ( + .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_5 mux_bottom_track_41 ( + .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_6 mux_bottom_track_43 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_7 mux_bottom_track_45 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_8 mux_bottom_track_47 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_9 mux_bottom_track_49 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_51 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_31 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_33 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_35 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_39 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_41 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_43 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_47 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_49 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( net_net_137 ) ) ; +sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[0] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( net_net_137 ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_162 ( .A ( aps_rename_505_ ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1399 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[17] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v new file mode 100644 index 0000000..cdb9787 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v @@ -0,0 +1,4176 @@ +// +// +// +// +// +// +module sb_1__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_130 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_127 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_125 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_118 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( copt_net_158 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( mem_out[2] ) , + .X ( copt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_153 ) , + .X ( copt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_154 ) , + .X ( copt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_155 ) , + .X ( copt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_103 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_102 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_187 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1415 ( .A ( ccff_head[0] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1416 ( .A ( ropt_net_182 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1417 ( .A ( ropt_net_185 ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1418 ( .A ( ropt_net_183 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1419 ( .A ( ropt_net_184 ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1420 ( .A ( ropt_net_186 ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , + bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT , + pReset_S_in , pReset_E_in , pReset_W_in , pReset_W_out , pReset_E_out , + prog_clk_0_S_in , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_BOT ; +output SC_OUT_BOT ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_E_out ; +input prog_clk_0_S_in ; +input VDD ; +input VSS ; + +wire ropt_net_166 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign pReset_S_in = pReset_E_in ; +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; + +sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[9] , + chany_bottom_in[20] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[8] , + chany_bottom_in[19] , chanx_right_out[7] , chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , + chanx_right_out[15] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 ( + .in ( { chanx_left_out[4] , chanx_left_out[20] , chany_bottom_in[10] , + chany_bottom_in[21] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 ( + .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] , + chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 ( + .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] , + chany_bottom_in[16] , chany_bottom_in[27] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 ( + .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] , + chany_bottom_in[17] , chany_bottom_in[28] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_7 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_4 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[7] , + chany_bottom_in[18] , chany_bottom_in[29] , chanx_right_out[8] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 ( + .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , + chany_bottom_in[11] , chany_bottom_in[22] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , + SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 ( + .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , + chany_bottom_in[12] , chany_bottom_in[23] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , + SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem_1 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size10_0 mux_right_track_6 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[6] , + chany_bottom_in[17] , chany_bottom_in[28] , chanx_right_out[9] , + chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 ( + .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , + chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_41_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , + SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , + SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 ( + .in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] , + chany_bottom_in[14] , chany_bottom_in[25] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size5_0 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , + chany_bottom_in[12] , chany_bottom_in[23] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_1 mux_right_track_44 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , + chany_bottom_in[11] , chany_bottom_in[22] , ropt_net_166 } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_2 mux_bottom_track_5 ( + .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 ( + .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_right_out[12] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size5 mux_left_track_37 ( + .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] , + chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_1 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_0 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[10] , + chany_bottom_in[21] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 , + SYNOPSYS_UNCONNECTED_73 } ) , + .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_13 ( + .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] , + chanx_right_out[13] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , + SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_2 mux_bottom_track_15 ( + .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] , + chanx_right_out[15] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , + SYNOPSYS_UNCONNECTED_79 } ) , + .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_3 mux_bottom_track_17 ( + .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] , + chanx_right_out[16] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 , + SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_4 mux_bottom_track_19 ( + .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , ropt_net_166 , + chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , + SYNOPSYS_UNCONNECTED_85 } ) , + .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_5 mux_bottom_track_37 ( + .in ( { chanx_left_out[29] , chanx_right_in[29] , + bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , + SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_6 mux_left_track_45 ( + .in ( { chanx_left_out[17] , chany_bottom_in[8] , chany_bottom_in[19] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , + SYNOPSYS_UNCONNECTED_91 } ) , + .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size4 mux_left_track_53 ( + .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 , + SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_15 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_17 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_19 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_7_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .in ( { chanx_left_out[4] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[1] , chanx_right_out[4] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 , + SYNOPSYS_UNCONNECTED_97 } ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 ( + .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[2] , chanx_right_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , + SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 ( + .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_right_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , + SYNOPSYS_UNCONNECTED_103 } ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 ( + .in ( { chanx_left_out[11] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[9] , chanx_right_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , + SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_21 ( + .in ( { chanx_left_out[19] , bottom_left_grid_pin_48_[0] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_23 ( + .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_25 ( + .in ( { chanx_left_out[21] , bottom_left_grid_pin_50_[0] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_27 ( + .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_23 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_25 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_0 mux_bottom_track_29 ( + .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_1 mux_bottom_track_31 ( + .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chany_bottom_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_2 mux_bottom_track_33 ( + .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_3 mux_bottom_track_35 ( + .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chany_bottom_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_4 mux_bottom_track_39 ( + .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_5 mux_bottom_track_41 ( + .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chany_bottom_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_6 mux_bottom_track_43 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chany_bottom_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_7 mux_bottom_track_45 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_8 mux_bottom_track_47 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chany_bottom_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_9 mux_bottom_track_49 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chany_bottom_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_51 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , + .out ( chany_bottom_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_31 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_33 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_35 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_39 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_41 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_43 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_47 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_49 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( net_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[0] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( net_net_137 ) , + .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_162 ( .A ( aps_rename_505_ ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1399 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v new file mode 100644 index 0000000..ee14626 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v @@ -0,0 +1,3292 @@ +// +// +// +// +// +// +module sb_1__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_134 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_132 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_130 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_129 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_127 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_125 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_124 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_122 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_120 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_118 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_117 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( copt_net_158 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( mem_out[2] ) , + .X ( copt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_153 ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_154 ) , + .X ( copt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_155 ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_115 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_145 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_111 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_108 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_143 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_105 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_141 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_103 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_102 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_187 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1415 ( .A ( ccff_head[0] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1416 ( .A ( ropt_net_182 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1417 ( .A ( ropt_net_185 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1418 ( .A ( ropt_net_183 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1419 ( .A ( ropt_net_184 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1420 ( .A ( ropt_net_186 ) , + .X ( ropt_net_187 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_99 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_97 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_139 ) ) ; +endmodule + + +module sb_1__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , + bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT , + pReset_S_in , pReset_E_in , pReset_W_in , pReset_W_out , pReset_E_out , + prog_clk_0_S_in ) ; +input [0:0] pReset ; +input [0:29] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_BOT ; +output SC_OUT_BOT ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_E_out ; +input prog_clk_0_S_in ; + +wire ropt_net_166 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; + +assign pReset_E_in = pReset_S_in ; +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; + +sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[9] , + chany_bottom_in[20] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[8] , + chany_bottom_in[19] , chanx_right_out[7] , chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , + chanx_right_out[15] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 ( + .in ( { chanx_left_out[4] , chanx_left_out[20] , chany_bottom_in[10] , + chany_bottom_in[21] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 ( + .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] , + chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 ( + .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] , + chany_bottom_in[16] , chany_bottom_in[27] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 ( + .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] , + chany_bottom_in[17] , chany_bottom_in[28] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_7 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_4 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[7] , + chany_bottom_in[18] , chany_bottom_in[29] , chanx_right_out[8] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 ( + .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , + chany_bottom_in[11] , chany_bottom_in[22] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , + SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 ( + .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , + chany_bottom_in[12] , chany_bottom_in[23] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , + SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem_1 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size10_0 mux_right_track_6 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[6] , + chany_bottom_in[17] , chany_bottom_in[28] , chanx_right_out[9] , + chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 ( + .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , + chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_41_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , + SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , + SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 ( + .in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] , + chany_bottom_in[14] , chany_bottom_in[25] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_0 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , + chany_bottom_in[12] , chany_bottom_in[23] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_1 mux_right_track_44 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , + chany_bottom_in[11] , chany_bottom_in[22] , ropt_net_166 } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_2 mux_bottom_track_5 ( + .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 ( + .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_right_out[12] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size5 mux_left_track_37 ( + .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] , + chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_1 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_0 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[10] , + chany_bottom_in[21] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 , + SYNOPSYS_UNCONNECTED_73 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_13 ( + .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] , + chanx_right_out[13] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , + SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_2 mux_bottom_track_15 ( + .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] , + chanx_right_out[15] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , + SYNOPSYS_UNCONNECTED_79 } ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_3 mux_bottom_track_17 ( + .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] , + chanx_right_out[16] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 , + SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_4 mux_bottom_track_19 ( + .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , ropt_net_166 , + chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , + SYNOPSYS_UNCONNECTED_85 } ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_5 mux_bottom_track_37 ( + .in ( { chanx_left_out[29] , chanx_right_in[29] , + bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , + SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_6 mux_left_track_45 ( + .in ( { chanx_left_out[17] , chany_bottom_in[8] , chany_bottom_in[19] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , + SYNOPSYS_UNCONNECTED_91 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size4 mux_left_track_53 ( + .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 , + SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_15 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_17 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_19 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .in ( { chanx_left_out[4] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[1] , chanx_right_out[4] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 , + SYNOPSYS_UNCONNECTED_97 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 ( + .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[2] , chanx_right_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , + SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 ( + .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_right_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , + SYNOPSYS_UNCONNECTED_103 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 ( + .in ( { chanx_left_out[11] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[9] , chanx_right_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , + SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_21 ( + .in ( { chanx_left_out[19] , bottom_left_grid_pin_48_[0] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_23 ( + .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_25 ( + .in ( { chanx_left_out[21] , bottom_left_grid_pin_50_[0] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_27 ( + .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_23 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_25 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_0 mux_bottom_track_29 ( + .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_1 mux_bottom_track_31 ( + .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_2 mux_bottom_track_33 ( + .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_3 mux_bottom_track_35 ( + .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_4 mux_bottom_track_39 ( + .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_5 mux_bottom_track_41 ( + .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_6 mux_bottom_track_43 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_7 mux_bottom_track_45 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_8 mux_bottom_track_47 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_9 mux_bottom_track_49 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_51 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_31 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_33 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_35 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_39 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_41 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_43 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_47 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_49 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( net_net_137 ) ) ; +sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[0] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( net_net_137 ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_162 ( .A ( aps_rename_505_ ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1399 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[17] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..65f3e2d --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_1__2__icv_in_design.top_only.pt.v @@ -0,0 +1,862 @@ +// +// +// +// +// +// +module sb_1__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , + bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT , + pReset_S_in , pReset_E_in , pReset_W_in , pReset_W_out , pReset_E_out , + prog_clk_0_S_in ) ; +input [0:0] pReset ; +input [0:29] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_BOT ; +output SC_OUT_BOT ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_E_out ; +input prog_clk_0_S_in ; + +wire ropt_net_166 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; + +assign pReset_E_in = pReset_S_in ; +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; + +sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[9] , + chany_bottom_in[20] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[8] , + chany_bottom_in[19] , chanx_right_out[7] , chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , + chanx_right_out[15] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 ( + .in ( { chanx_left_out[4] , chanx_left_out[20] , chany_bottom_in[10] , + chany_bottom_in[21] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 ( + .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] , + chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 ( + .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] , + chany_bottom_in[16] , chany_bottom_in[27] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 ( + .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] , + chany_bottom_in[17] , chany_bottom_in[28] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_7 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_4 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[7] , + chany_bottom_in[18] , chany_bottom_in[29] , chanx_right_out[8] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 ( + .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , + chany_bottom_in[11] , chany_bottom_in[22] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , + SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 ( + .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , + chany_bottom_in[12] , chany_bottom_in[23] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , + SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem_1 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size10_0 mux_right_track_6 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[6] , + chany_bottom_in[17] , chany_bottom_in[28] , chanx_right_out[9] , + chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 ( + .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , + chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_41_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , + SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , + SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 ( + .in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] , + chany_bottom_in[14] , chany_bottom_in[25] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_0 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , + chany_bottom_in[12] , chany_bottom_in[23] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_1 mux_right_track_44 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , + chany_bottom_in[11] , chany_bottom_in[22] , ropt_net_166 } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_2 mux_bottom_track_5 ( + .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 ( + .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_right_out[12] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size5 mux_left_track_37 ( + .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] , + chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_1 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_0 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[10] , + chany_bottom_in[21] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 , + SYNOPSYS_UNCONNECTED_73 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_13 ( + .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] , + chanx_right_out[13] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , + SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_2 mux_bottom_track_15 ( + .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] , + chanx_right_out[15] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , + SYNOPSYS_UNCONNECTED_79 } ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_3 mux_bottom_track_17 ( + .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] , + chanx_right_out[16] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 , + SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_4 mux_bottom_track_19 ( + .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , ropt_net_166 , + chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , + SYNOPSYS_UNCONNECTED_85 } ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_5 mux_bottom_track_37 ( + .in ( { chanx_left_out[29] , chanx_right_in[29] , + bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , + SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_6 mux_left_track_45 ( + .in ( { chanx_left_out[17] , chany_bottom_in[8] , chany_bottom_in[19] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , + SYNOPSYS_UNCONNECTED_91 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__2__mux_tree_tapbuf_size4 mux_left_track_53 ( + .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 , + SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_15 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_17 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_19 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .in ( { chanx_left_out[4] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[1] , chanx_right_out[4] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 , + SYNOPSYS_UNCONNECTED_97 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 ( + .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[2] , chanx_right_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , + SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 ( + .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_right_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , + SYNOPSYS_UNCONNECTED_103 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_152 ) ) ; +sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 ( + .in ( { chanx_left_out[11] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[9] , chanx_right_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , + SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_21 ( + .in ( { chanx_left_out[19] , bottom_left_grid_pin_48_[0] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_23 ( + .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_25 ( + .in ( { chanx_left_out[21] , bottom_left_grid_pin_50_[0] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_27 ( + .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_23 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_25 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_0 mux_bottom_track_29 ( + .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_1 mux_bottom_track_31 ( + .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_2 mux_bottom_track_33 ( + .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_3 mux_bottom_track_35 ( + .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_4 mux_bottom_track_39 ( + .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_5 mux_bottom_track_41 ( + .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_6 mux_bottom_track_43 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_7 mux_bottom_track_45 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_8 mux_bottom_track_47 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_9 mux_bottom_track_49 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_51 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_31 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_33 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_35 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_39 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_41 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_43 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_47 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_49 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( net_net_137 ) ) ; +sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[0] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( net_net_137 ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_162 ( .A ( aps_rename_505_ ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1399 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[17] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v new file mode 100644 index 0000000..bde163a --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v @@ -0,0 +1,3429 @@ +// +// +// +// +// +// +module sb_2__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +wire copt_net_181 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_181 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_181 ) , + .X ( mem_out[1] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_124 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_159 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_51 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_34 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_51 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_122 ) ) ; +endmodule + + +module sb_2__0__const1_50 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_33 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_50 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_49 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_32 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_49 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module sb_2__0__const1_48 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_31 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_48 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_47 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_47 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_46 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_46 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_45 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_45 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_157 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_44 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_44 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_43 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_26 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_113 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_155 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_42 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_41 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_153 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_40 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_39 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_38 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_151 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_37 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_106 ) ) ; +endmodule + + +module sb_2__0__const1_36 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_35 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_34 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_33 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module sb_2__0__const1_32 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_31 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_145 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_30 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_29 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_28 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_27 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_143 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_26 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) ) ; +endmodule + + +module sb_2__0__const1_25 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_24 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_23 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_22 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_21 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_141 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_20 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_88 ) ) ; +endmodule + + +module sb_2__0__const1_19 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_139 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_18 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_137 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_17 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_135 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__const1_16 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__0__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module sb_2__0__const1_15 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__0__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_14 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__0__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_133 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_13 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__0__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_12 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__0__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_131 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_201 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( ccff_head[0] ) , + .X ( copt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1337 ( .A ( copt_net_172 ) , + .X ( copt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_170 ) , + .X ( copt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_175 ) , + .X ( copt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_173 ) , + .X ( copt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_171 ) , + .X ( copt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( copt_net_174 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_197 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_198 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_199 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1365 ( .A ( ropt_net_200 ) , + .X ( ropt_net_201 ) ) ; +endmodule + + +module sb_2__0__const1_11 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_129 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_10 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_9 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_164 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_164 ) ) ; +endmodule + + +module sb_2__0__const1_8 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) ) ; +endmodule + + +module sb_2__0__const1_7 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_67 ) ) ; +endmodule + + +module sb_2__0__const1_6 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_5 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_4 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) ) ; +endmodule + + +module sb_2__0__const1_3 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_2 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_161 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_0 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , top_right_grid_pin_1_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , + left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , + left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out , + ccff_tail , pReset_W_in , pReset_N_out , prog_clk_0_N_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] left_bottom_grid_pin_13_ ; +input [0:0] left_bottom_grid_pin_15_ ; +input [0:0] left_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input pReset_W_in ; +output pReset_N_out ; +input prog_clk_0_N_in ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_27_sram ; +wire [0:1] mux_tree_tapbuf_size2_28_sram ; +wire [0:1] mux_tree_tapbuf_size2_29_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_30_sram ; +wire [0:1] mux_tree_tapbuf_size2_31_sram ; +wire [0:1] mux_tree_tapbuf_size2_32_sram ; +wire [0:1] mux_tree_tapbuf_size2_33_sram ; +wire [0:1] mux_tree_tapbuf_size2_34_sram ; +wire [0:1] mux_tree_tapbuf_size2_35_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__0__mux_tree_tapbuf_size4_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_2 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_3 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_4 mux_top_track_8 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_5 mux_top_track_10 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_6 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_7 mux_left_track_3 ( + .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_8 mux_left_track_5 ( + .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_9 mux_left_track_7 ( + .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_10 mux_left_track_9 ( + .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size4 mux_left_track_11 ( + .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_4 mem_top_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_5 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_13 ( + .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_3 mux_left_track_29 ( + .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size3 mux_left_track_45 ( + .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_3 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_14 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_24 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_26 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_28 ( + .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_8 mux_top_track_36 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_9 mux_top_track_38 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_10 mux_top_track_40 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_top_out[20] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_11 mux_top_track_42 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chany_top_out[21] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_46 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chany_top_out[23] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_48 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chany_top_out[24] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_50 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chany_top_out[25] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_15 ( + .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_17 ( + .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_19 ( + .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_21 ( + .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_23 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_25 ( + .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_21 mux_left_track_27 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_22 mux_left_track_31 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_23 mux_left_track_33 ( + .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_24 mux_left_track_35 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_25 mux_left_track_37 ( + .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_26 mux_left_track_39 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_27 mux_left_track_41 ( + .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_27_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_28 mux_left_track_43 ( + .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_28_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_29 mux_left_track_47 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_29_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_30 mux_left_track_49 ( + .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_30_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_31 mux_left_track_51 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_31_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_32 mux_left_track_53 ( + .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_32_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_33 mux_left_track_55 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_33_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_34 mux_left_track_57 ( + .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_34_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2 mux_left_track_59 ( + .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_35_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_38 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_top_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_top_track_42 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_21 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_22 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_23 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_24 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_25 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_26 mem_left_track_39 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_27 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_27_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_28 mem_left_track_43 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_28_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_29 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_29_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_30 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_30_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_31 mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_31_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_32 mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_32_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_33 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_33_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_34 mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_34_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_165 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[2] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[3] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[4] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[13] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chanx_left_in[14] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( pReset_W_in ) , .Y ( BUF_net_126 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_167 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_168 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , + .HI ( optlc_net_169 ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v new file mode 100644 index 0000000..691301e --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v @@ -0,0 +1,3721 @@ +// +// +// +// +// +// +module sb_2__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_181 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_181 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_181 ) , + .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_159 ( .A ( BUF_net_124 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_34 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_33 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_32 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_31 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_157 ( .A ( BUF_net_116 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_26 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_155 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_153 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_151 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_145 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_143 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_141 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_139 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_137 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_135 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_133 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_131 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_201 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( ccff_head[0] ) , + .X ( copt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1337 ( .A ( copt_net_172 ) , + .X ( copt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_170 ) , + .X ( copt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_175 ) , + .X ( copt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_173 ) , + .X ( copt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_171 ) , + .X ( copt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( copt_net_174 ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_197 ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_198 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_199 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1365 ( .A ( ropt_net_200 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_129 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_164 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_161 ( .A ( BUF_net_61 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , top_right_grid_pin_1_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , + left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , + left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out , + ccff_tail , pReset_W_in , pReset_N_out , prog_clk_0_N_in , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] left_bottom_grid_pin_13_ ; +input [0:0] left_bottom_grid_pin_15_ ; +input [0:0] left_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input pReset_W_in ; +output pReset_N_out ; +input prog_clk_0_N_in ; +input VDD ; +input VSS ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_27_sram ; +wire [0:1] mux_tree_tapbuf_size2_28_sram ; +wire [0:1] mux_tree_tapbuf_size2_29_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_30_sram ; +wire [0:1] mux_tree_tapbuf_size2_31_sram ; +wire [0:1] mux_tree_tapbuf_size2_32_sram ; +wire [0:1] mux_tree_tapbuf_size2_33_sram ; +wire [0:1] mux_tree_tapbuf_size2_34_sram ; +wire [0:1] mux_tree_tapbuf_size2_35_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__0__mux_tree_tapbuf_size4_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_2 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_3 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_4 mux_top_track_8 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_5 mux_top_track_10 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_6 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_7 mux_left_track_3 ( + .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_8 mux_left_track_5 ( + .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_9 mux_left_track_7 ( + .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_10 mux_left_track_9 ( + .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size4 mux_left_track_11 ( + .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_4 mem_top_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_5 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_13 ( + .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_3 mux_left_track_29 ( + .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size3 mux_left_track_45 ( + .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_3 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_14 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_24 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_26 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_28 ( + .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_8 mux_top_track_36 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_9 mux_top_track_38 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_10 mux_top_track_40 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_top_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_11 mux_top_track_42 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chany_top_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_46 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chany_top_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_48 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chany_top_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_50 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chany_top_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_15 ( + .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_17 ( + .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_19 ( + .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_21 ( + .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_23 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_25 ( + .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_21 mux_left_track_27 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_22 mux_left_track_31 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_23 mux_left_track_33 ( + .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_24 mux_left_track_35 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_25 mux_left_track_37 ( + .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_26 mux_left_track_39 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_27 mux_left_track_41 ( + .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_27_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_left_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_28 mux_left_track_43 ( + .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_28_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_29 mux_left_track_47 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_29_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_left_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_30 mux_left_track_49 ( + .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_30_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_31 mux_left_track_51 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_31_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_32 mux_left_track_53 ( + .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_32_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_33 mux_left_track_55 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_33_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_left_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_34 mux_left_track_57 ( + .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_34_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2 mux_left_track_59 ( + .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_35_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_38 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_top_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_top_track_42 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_21 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_22 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_23 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_24 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_25 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_26 mem_left_track_39 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_26_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_27 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_27_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_28 mem_left_track_43 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_28_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_29 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_29_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_30 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_30_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_31 mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_31_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_32 mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_32_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_33 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_33_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_34 mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_34_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_35_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[2] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[3] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[4] ) , + .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[13] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chanx_left_in[14] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[15] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( pReset_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( pReset_W_in ) , .Y ( BUF_net_126 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , + .HI ( optlc_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v new file mode 100644 index 0000000..c6b2cf7 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v @@ -0,0 +1,2846 @@ +// +// +// +// +// +// +module sb_2__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +wire copt_net_181 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_181 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_181 ) , + .X ( mem_out[1] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_124 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_159 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_34 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_122 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_33 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_32 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_31 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_157 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_26 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_113 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_155 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_153 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_151 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_106 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_145 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_143 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_141 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_88 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_139 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_137 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_135 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_133 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_131 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_201 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( ccff_head[0] ) , + .X ( copt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1337 ( .A ( copt_net_172 ) , + .X ( copt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_170 ) , + .X ( copt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_175 ) , + .X ( copt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_173 ) , + .X ( copt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_171 ) , + .X ( copt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( copt_net_174 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_197 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_198 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_199 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1365 ( .A ( ropt_net_200 ) , + .X ( ropt_net_201 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_129 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_164 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_164 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_67 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_161 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , top_right_grid_pin_1_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , + left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , + left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out , + ccff_tail , pReset_W_in , pReset_N_out , prog_clk_0_N_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] left_bottom_grid_pin_13_ ; +input [0:0] left_bottom_grid_pin_15_ ; +input [0:0] left_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input pReset_W_in ; +output pReset_N_out ; +input prog_clk_0_N_in ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_27_sram ; +wire [0:1] mux_tree_tapbuf_size2_28_sram ; +wire [0:1] mux_tree_tapbuf_size2_29_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_30_sram ; +wire [0:1] mux_tree_tapbuf_size2_31_sram ; +wire [0:1] mux_tree_tapbuf_size2_32_sram ; +wire [0:1] mux_tree_tapbuf_size2_33_sram ; +wire [0:1] mux_tree_tapbuf_size2_34_sram ; +wire [0:1] mux_tree_tapbuf_size2_35_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__0__mux_tree_tapbuf_size4_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_2 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_3 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_4 mux_top_track_8 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_5 mux_top_track_10 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_6 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_7 mux_left_track_3 ( + .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_8 mux_left_track_5 ( + .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_9 mux_left_track_7 ( + .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_10 mux_left_track_9 ( + .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size4 mux_left_track_11 ( + .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_4 mem_top_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_5 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_13 ( + .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_3 mux_left_track_29 ( + .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size3 mux_left_track_45 ( + .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_3 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_14 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_24 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_26 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_28 ( + .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_8 mux_top_track_36 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_9 mux_top_track_38 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_10 mux_top_track_40 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_top_out[20] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_11 mux_top_track_42 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chany_top_out[21] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_46 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chany_top_out[23] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_48 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chany_top_out[24] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_50 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chany_top_out[25] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_15 ( + .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_17 ( + .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_19 ( + .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_21 ( + .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_23 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_25 ( + .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_21 mux_left_track_27 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_22 mux_left_track_31 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_23 mux_left_track_33 ( + .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_24 mux_left_track_35 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_25 mux_left_track_37 ( + .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_26 mux_left_track_39 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_27 mux_left_track_41 ( + .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_27_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_28 mux_left_track_43 ( + .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_28_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_29 mux_left_track_47 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_29_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_30 mux_left_track_49 ( + .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_30_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_31 mux_left_track_51 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_31_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_32 mux_left_track_53 ( + .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_32_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_33 mux_left_track_55 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_33_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_34 mux_left_track_57 ( + .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_34_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2 mux_left_track_59 ( + .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_35_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_38 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_top_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_top_track_42 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_21 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_22 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_23 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_24 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_25 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_26 mem_left_track_39 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_27 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_27_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_28 mem_left_track_43 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_28_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_29 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_29_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_30 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_30_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_31 mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_31_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_32 mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_32_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_33 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_33_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_34 mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_34_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_165 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[2] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[3] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[4] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[13] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chanx_left_in[14] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( pReset_W_in ) , .Y ( BUF_net_126 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_167 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_168 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , + .HI ( optlc_net_169 ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..b1f648d --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__0__icv_in_design.top_only.pt.v @@ -0,0 +1,744 @@ +// +// +// +// +// +// +module sb_2__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , top_right_grid_pin_1_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , + left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , + left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out , + ccff_tail , pReset_W_in , pReset_N_out , prog_clk_0_N_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] left_bottom_grid_pin_13_ ; +input [0:0] left_bottom_grid_pin_15_ ; +input [0:0] left_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input pReset_W_in ; +output pReset_N_out ; +input prog_clk_0_N_in ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_27_sram ; +wire [0:1] mux_tree_tapbuf_size2_28_sram ; +wire [0:1] mux_tree_tapbuf_size2_29_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_30_sram ; +wire [0:1] mux_tree_tapbuf_size2_31_sram ; +wire [0:1] mux_tree_tapbuf_size2_32_sram ; +wire [0:1] mux_tree_tapbuf_size2_33_sram ; +wire [0:1] mux_tree_tapbuf_size2_34_sram ; +wire [0:1] mux_tree_tapbuf_size2_35_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__0__mux_tree_tapbuf_size4_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_2 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_3 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_4 mux_top_track_8 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_5 mux_top_track_10 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_6 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_7 mux_left_track_3 ( + .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_8 mux_left_track_5 ( + .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_9 mux_left_track_7 ( + .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_10 mux_left_track_9 ( + .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size4 mux_left_track_11 ( + .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_4 mem_top_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_5 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_13 ( + .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_3 mux_left_track_29 ( + .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size3 mux_left_track_45 ( + .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_3 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_14 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_24 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_26 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_28 ( + .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_8 mux_top_track_36 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_9 mux_top_track_38 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_10 mux_top_track_40 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_top_out[20] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_11 mux_top_track_42 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chany_top_out[21] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_46 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chany_top_out[23] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_48 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chany_top_out[24] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_50 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chany_top_out[25] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_15 ( + .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_17 ( + .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_19 ( + .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_21 ( + .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_23 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_25 ( + .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_21 mux_left_track_27 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_22 mux_left_track_31 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_23 mux_left_track_33 ( + .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_166 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_24 mux_left_track_35 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_169 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_25 mux_left_track_37 ( + .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_26 mux_left_track_39 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_27 mux_left_track_41 ( + .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_27_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_28 mux_left_track_43 ( + .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_28_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_29 mux_left_track_47 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_29_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_30 mux_left_track_49 ( + .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_30_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_167 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_31 mux_left_track_51 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_31_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_165 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_32 mux_left_track_53 ( + .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_32_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_33 mux_left_track_55 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_33_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_34 mux_left_track_57 ( + .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_34_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2 mux_left_track_59 ( + .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_35_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_168 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_38 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_top_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_top_track_42 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_21 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_22 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_23 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_24 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_25 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_26 mem_left_track_39 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_27 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_27_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_28 mem_left_track_43 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_28_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_29 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_29_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_30 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_30_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_31 mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_31_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_32 mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_32_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_33 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_33_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_34 mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_34_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_165 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[2] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[3] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[4] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[13] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chanx_left_in[14] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( pReset_W_in ) , .Y ( BUF_net_126 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_167 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_168 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , + .HI ( optlc_net_169 ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v new file mode 100644 index 0000000..a3b9b50 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v @@ -0,0 +1,3885 @@ +// +// +// +// +// +// +module sb_2__1__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_47 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1_47 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_46 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1_46 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_45 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1_45 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_44 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1_44 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_43 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_42 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1_41 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_40 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_39 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_38 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_37 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_36 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_35 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_134 ) ) ; +endmodule + + +module sb_2__1__const1_34 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1_33 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_32 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_31 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_131 ) ) ; +endmodule + + +module sb_2__1__const1_30 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_129 ) ) ; +endmodule + + +module sb_2__1__const1_29 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_127 ) ) ; +endmodule + + +module sb_2__1__const1_28 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_125 ) ) ; +endmodule + + +module sb_2__1__const1_27 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_123 ) ) ; +endmodule + + +module sb_2__1__const1_26 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_121 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1_25 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_2__1__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module sb_2__1__const1_24 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_2__1__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_117 ) ) ; +endmodule + + +module sb_2__1__const1_23 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_2__1__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_22 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_2__1__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_21 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_2__1__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1_20 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_2__1__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_114 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1_19 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_2__1__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_112 ) ) ; +endmodule + + +module sb_2__1__const1_18 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_2__1__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_110 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_17 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_2__1__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_109 ) ) ; +endmodule + + +module sb_2__1__const1_16 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_2__1__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_107 ) ) ; +endmodule + + +module sb_2__1__const1_15 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_2__1__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) ) ; +endmodule + + +module sb_2__1__const1_14 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_2__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1_13 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_2__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_12 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_2__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module sb_2__1__const1_11 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_2__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1_10 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_9 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_99 ) ) ; +endmodule + + +module sb_2__1__const1_8 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_7 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_6 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_97 ) ) ; +endmodule + + +module sb_2__1__const1_5 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_95 ) ) ; +endmodule + + +module sb_2__1__const1_4 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_172 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_149 ) , + .X ( copt_net_145 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1320 ( .A ( copt_net_148 ) , + .X ( copt_net_146 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( copt_net_146 ) , + .X ( copt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( copt_net_145 ) , + .X ( copt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , + .X ( copt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( ropt_net_174 ) , + .X ( copt_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_147 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1343 ( .A ( copt_net_150 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( copt_net_158 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( ropt_net_173 ) , + .X ( ropt_net_174 ) ) ; +endmodule + + +module sb_2__1__const1_3 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_2__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_93 ) ) ; +endmodule + + +module sb_2__1__const1_2 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_2__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_91 ) ) ; +endmodule + + +module sb_2__1__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_2__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_0 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_2__1__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_2__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ , + bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chany_bottom_out , + chanx_left_out , ccff_tail , pReset_W_in , pReset_N_out , + prog_clk_0_N_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input pReset_W_in ; +output pReset_N_out ; +input prog_clk_0_N_in ; + +wire ropt_net_162 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chany_top_out[4] , chany_top_out[20] , + chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_1 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[12] , + chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_2 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[2] , chanx_left_in[13] , + chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[3] , chanx_left_in[14] , + chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_2 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chany_top_out[7] , chany_top_out[21] , + chanx_left_in[10] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chany_top_out[8] , chany_top_out[23] , + chanx_left_in[9] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , + SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , + chany_top_out[12] , chany_top_out[27] , chanx_left_in[6] , + chanx_left_in[17] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , + SYNOPSYS_UNCONNECTED_25 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_3 mux_top_track_20 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , + chany_top_out[13] , chany_top_out[28] , chanx_left_in[5] , + chanx_left_in[16] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , + SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_4 mux_top_track_28 ( + .in ( { top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , + chany_top_out[15] , chany_top_out[29] , chanx_left_in[4] , + chanx_left_in[15] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_5 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[6] , chanx_left_in[17] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , + SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[7] , chanx_left_in[18] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , + SYNOPSYS_UNCONNECTED_37 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem mem_bottom_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_0 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , + top_right_grid_pin_1_[0] , chany_top_out[9] , chany_top_out[24] , + chanx_left_in[8] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , + SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , + chany_top_out[11] , chany_top_out[25] , chanx_left_in[7] , + chanx_left_in[18] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , + SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_11 ( + .in ( { ropt_net_162 , chany_bottom_out[25] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_left_in[16] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_0 mux_top_track_36 ( + .in ( { top_left_grid_pin_47_[0] , chany_top_out[16] , chanx_left_in[3] , + chanx_left_in[14] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , + SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chany_top_out[17] , chanx_left_in[2] , + chanx_left_in[13] , chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_2 mux_top_track_52 ( + .in ( { top_left_grid_pin_49_[0] , chany_top_out[19] , chanx_left_in[1] , + chanx_left_in[12] , chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_3 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , bottom_left_grid_pin_48_[0] , + chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_4 mux_left_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_in[1] , chany_top_out[8] , + left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size5 mux_left_track_11 ( + .in ( { chany_bottom_out[12] , chany_bottom_in[5] , chany_top_out[12] , + left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_4 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[4] , chanx_left_in[15] , + chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_mem mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[8] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , + SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_1 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_top_out[4] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 , + SYNOPSYS_UNCONNECTED_77 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_2 mux_left_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_in[0] , chany_top_out[7] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , + SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_3 mux_left_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_in[2] , chany_top_out[9] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , + SYNOPSYS_UNCONNECTED_83 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6 mux_left_track_9 ( + .in ( { ropt_net_162 , chany_bottom_in[4] , chany_top_out[11] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 , + SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_2 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_3 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_0 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , bottom_left_grid_pin_46_[0] , + chanx_left_in[9] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 , + SYNOPSYS_UNCONNECTED_89 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_1 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , bottom_left_grid_pin_47_[0] , + chanx_left_in[10] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , + SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( + .in ( { chany_bottom_out[13] , chany_bottom_in[9] , chany_top_out[13] , + left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , + SYNOPSYS_UNCONNECTED_95 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_3 mux_left_track_15 ( + .in ( { chany_bottom_out[15] , chany_bottom_in[13] , chany_top_out[15] , + left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 , + SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_4 mux_left_track_17 ( + .in ( { chany_bottom_out[16] , chany_top_out[16] , chany_bottom_in[17] , + left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 , + SYNOPSYS_UNCONNECTED_101 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_5 mux_left_track_19 ( + .in ( { chany_bottom_out[17] , chany_top_out[17] , chany_bottom_in[21] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , + SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_6 mux_left_track_21 ( + .in ( { chany_bottom_out[19] , chany_top_out[19] , chany_bottom_in[25] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , + SYNOPSYS_UNCONNECTED_107 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4 mux_left_track_23 ( + .in ( { chany_bottom_out[20] , chany_top_out[20] , chany_bottom_in[29] , + chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , + SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_3 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_4 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_5 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_6 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_25 ( + .in ( { chany_bottom_out[21] , chany_top_out[21] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_27 ( + .in ( { chany_bottom_out[23] , chany_top_out[23] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_29 ( + .in ( { chany_bottom_out[24] , chany_top_out[24] , + left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_31 ( + .in ( { chany_bottom_out[25] , chany_top_out[25] , + left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_4 mux_left_track_33 ( + .in ( { chany_bottom_out[27] , chany_top_out[27] , + left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_5 mux_left_track_35 ( + .in ( { chany_bottom_out[28] , chany_top_out[28] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_6 mux_left_track_37 ( + .in ( { chany_bottom_out[29] , chany_top_out[29] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3 mux_left_track_51 ( + .in ( { chany_top_in[9] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_4 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_5 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_6 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_41 ( + .in ( { chany_top_in[29] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_45 ( + .in ( { chany_top_in[21] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_47 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_49 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_53 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_5 mux_left_track_55 ( + .in ( { chany_top_in[4] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2 mux_left_track_57 ( + .in ( { chany_top_in[2] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_5 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_6 pReset_N_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_N_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[25] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( left_bottom_grid_pin_41_[0] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_141 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_144 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_145 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1336 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[11] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v new file mode 100644 index 0000000..54ced7a --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v @@ -0,0 +1,4257 @@ +// +// +// +// +// +// +module sb_2__1__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_110 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_172 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_149 ) , + .X ( copt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1320 ( .A ( copt_net_148 ) , + .X ( copt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( copt_net_146 ) , + .X ( copt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( copt_net_145 ) , + .X ( copt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , + .X ( copt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( ropt_net_174 ) , + .X ( copt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_147 ) , + .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1343 ( .A ( copt_net_150 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( copt_net_158 ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( ropt_net_173 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ , + bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chany_bottom_out , + chanx_left_out , ccff_tail , pReset_W_in , pReset_N_out , + prog_clk_0_N_in , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input pReset_W_in ; +output pReset_N_out ; +input prog_clk_0_N_in ; +input VDD ; +input VSS ; + +wire ropt_net_162 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chany_top_out[4] , chany_top_out[20] , + chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_1 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[12] , + chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_2 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[2] , chanx_left_in[13] , + chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[3] , chanx_left_in[14] , + chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_2 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chany_top_out[7] , chany_top_out[21] , + chanx_left_in[10] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 } ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chany_top_out[8] , chany_top_out[23] , + chanx_left_in[9] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , + SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , + chany_top_out[12] , chany_top_out[27] , chanx_left_in[6] , + chanx_left_in[17] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , + SYNOPSYS_UNCONNECTED_25 } ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_3 mux_top_track_20 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , + chany_top_out[13] , chany_top_out[28] , chanx_left_in[5] , + chanx_left_in[16] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , + SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_4 mux_top_track_28 ( + .in ( { top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , + chany_top_out[15] , chany_top_out[29] , chanx_left_in[4] , + chanx_left_in[15] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 } ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_5 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[6] , chanx_left_in[17] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , + SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[7] , chanx_left_in[18] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , + SYNOPSYS_UNCONNECTED_37 } ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem mem_bottom_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size9_0 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , + top_right_grid_pin_1_[0] , chany_top_out[9] , chany_top_out[24] , + chanx_left_in[8] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , + SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , + chany_top_out[11] , chany_top_out[25] , chanx_left_in[7] , + chanx_left_in[18] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , + SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_11 ( + .in ( { ropt_net_162 , chany_bottom_out[25] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_left_in[16] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size5_0 mux_top_track_36 ( + .in ( { top_left_grid_pin_47_[0] , chany_top_out[16] , chanx_left_in[3] , + chanx_left_in[14] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , + SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chany_top_out[17] , chanx_left_in[2] , + chanx_left_in[13] , chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_2 mux_top_track_52 ( + .in ( { top_left_grid_pin_49_[0] , chany_top_out[19] , chanx_left_in[1] , + chanx_left_in[12] , chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_top_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_3 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , bottom_left_grid_pin_48_[0] , + chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_4 mux_left_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_in[1] , chany_top_out[8] , + left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size5 mux_left_track_11 ( + .in ( { chany_bottom_out[12] , chany_bottom_in[5] , chany_top_out[12] , + left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_4 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[4] , chanx_left_in[15] , + chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_mem mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[8] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , + SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_1 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_top_out[4] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 , + SYNOPSYS_UNCONNECTED_77 } ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_2 mux_left_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_in[0] , chany_top_out[7] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , + SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_3 mux_left_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_in[2] , chany_top_out[9] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , + SYNOPSYS_UNCONNECTED_83 } ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6 mux_left_track_9 ( + .in ( { ropt_net_162 , chany_bottom_in[4] , chany_top_out[11] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 , + SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_2 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_3 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_0 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , bottom_left_grid_pin_46_[0] , + chanx_left_in[9] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 , + SYNOPSYS_UNCONNECTED_89 } ) , + .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_1 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , bottom_left_grid_pin_47_[0] , + chanx_left_in[10] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , + SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( + .in ( { chany_bottom_out[13] , chany_bottom_in[9] , chany_top_out[13] , + left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , + SYNOPSYS_UNCONNECTED_95 } ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_3 mux_left_track_15 ( + .in ( { chany_bottom_out[15] , chany_bottom_in[13] , chany_top_out[15] , + left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 , + SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_4 mux_left_track_17 ( + .in ( { chany_bottom_out[16] , chany_top_out[16] , chany_bottom_in[17] , + left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 , + SYNOPSYS_UNCONNECTED_101 } ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_5 mux_left_track_19 ( + .in ( { chany_bottom_out[17] , chany_top_out[17] , chany_bottom_in[21] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , + SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_6 mux_left_track_21 ( + .in ( { chany_bottom_out[19] , chany_top_out[19] , chany_bottom_in[25] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , + SYNOPSYS_UNCONNECTED_107 } ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4 mux_left_track_23 ( + .in ( { chany_bottom_out[20] , chany_top_out[20] , chany_bottom_in[29] , + chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , + SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_3 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_4 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_5 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_6 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_25 ( + .in ( { chany_bottom_out[21] , chany_top_out[21] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_27 ( + .in ( { chany_bottom_out[23] , chany_top_out[23] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_29 ( + .in ( { chany_bottom_out[24] , chany_top_out[24] , + left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_31 ( + .in ( { chany_bottom_out[25] , chany_top_out[25] , + left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_4 mux_left_track_33 ( + .in ( { chany_bottom_out[27] , chany_top_out[27] , + left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_5 mux_left_track_35 ( + .in ( { chany_bottom_out[28] , chany_top_out[28] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_6 mux_left_track_37 ( + .in ( { chany_bottom_out[29] , chany_top_out[29] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3 mux_left_track_51 ( + .in ( { chany_top_in[9] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chanx_left_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_4 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_5 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_6 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_41 ( + .in ( { chany_top_in[29] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_left_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_45 ( + .in ( { chany_top_in[21] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_47 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chanx_left_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_49 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chanx_left_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_53 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , + .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_5 mux_left_track_55 ( + .in ( { chany_top_in[4] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , + .out ( chanx_left_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2 mux_left_track_57 ( + .in ( { chany_top_in[2] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , + .out ( chanx_left_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_5 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 pReset_N_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , + .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[25] ) , + .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( left_bottom_grid_pin_41_[0] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_144 ) , + .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_145 ) , + .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1336 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v new file mode 100644 index 0000000..27dba57 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v @@ -0,0 +1,3346 @@ +// +// +// +// +// +// +module sb_2__1__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_134 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_131 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_129 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_127 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_125 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_123 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_121 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_117 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_114 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_112 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_110 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_109 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_107 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_99 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_97 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_95 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_172 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_149 ) , + .X ( copt_net_145 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1320 ( .A ( copt_net_148 ) , + .X ( copt_net_146 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( copt_net_146 ) , + .X ( copt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( copt_net_145 ) , + .X ( copt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , + .X ( copt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( ropt_net_174 ) , + .X ( copt_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_147 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1343 ( .A ( copt_net_150 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( copt_net_158 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( ropt_net_173 ) , + .X ( ropt_net_174 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_93 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_91 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_2__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ , + bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chany_bottom_out , + chanx_left_out , ccff_tail , pReset_W_in , pReset_N_out , + prog_clk_0_N_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input pReset_W_in ; +output pReset_N_out ; +input prog_clk_0_N_in ; + +wire ropt_net_162 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chany_top_out[4] , chany_top_out[20] , + chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_1 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[12] , + chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_2 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[2] , chanx_left_in[13] , + chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[3] , chanx_left_in[14] , + chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_2 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chany_top_out[7] , chany_top_out[21] , + chanx_left_in[10] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chany_top_out[8] , chany_top_out[23] , + chanx_left_in[9] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , + SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , + chany_top_out[12] , chany_top_out[27] , chanx_left_in[6] , + chanx_left_in[17] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , + SYNOPSYS_UNCONNECTED_25 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_3 mux_top_track_20 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , + chany_top_out[13] , chany_top_out[28] , chanx_left_in[5] , + chanx_left_in[16] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , + SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_4 mux_top_track_28 ( + .in ( { top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , + chany_top_out[15] , chany_top_out[29] , chanx_left_in[4] , + chanx_left_in[15] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_5 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[6] , chanx_left_in[17] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , + SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[7] , chanx_left_in[18] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , + SYNOPSYS_UNCONNECTED_37 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem mem_bottom_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_0 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , + top_right_grid_pin_1_[0] , chany_top_out[9] , chany_top_out[24] , + chanx_left_in[8] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , + SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , + chany_top_out[11] , chany_top_out[25] , chanx_left_in[7] , + chanx_left_in[18] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , + SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_11 ( + .in ( { ropt_net_162 , chany_bottom_out[25] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_left_in[16] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_0 mux_top_track_36 ( + .in ( { top_left_grid_pin_47_[0] , chany_top_out[16] , chanx_left_in[3] , + chanx_left_in[14] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , + SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chany_top_out[17] , chanx_left_in[2] , + chanx_left_in[13] , chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_2 mux_top_track_52 ( + .in ( { top_left_grid_pin_49_[0] , chany_top_out[19] , chanx_left_in[1] , + chanx_left_in[12] , chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_3 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , bottom_left_grid_pin_48_[0] , + chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_4 mux_left_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_in[1] , chany_top_out[8] , + left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size5 mux_left_track_11 ( + .in ( { chany_bottom_out[12] , chany_bottom_in[5] , chany_top_out[12] , + left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_4 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[4] , chanx_left_in[15] , + chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_mem mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[8] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , + SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_1 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_top_out[4] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 , + SYNOPSYS_UNCONNECTED_77 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_2 mux_left_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_in[0] , chany_top_out[7] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , + SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_3 mux_left_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_in[2] , chany_top_out[9] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , + SYNOPSYS_UNCONNECTED_83 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6 mux_left_track_9 ( + .in ( { ropt_net_162 , chany_bottom_in[4] , chany_top_out[11] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 , + SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_2 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_3 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_0 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , bottom_left_grid_pin_46_[0] , + chanx_left_in[9] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 , + SYNOPSYS_UNCONNECTED_89 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_1 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , bottom_left_grid_pin_47_[0] , + chanx_left_in[10] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , + SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( + .in ( { chany_bottom_out[13] , chany_bottom_in[9] , chany_top_out[13] , + left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , + SYNOPSYS_UNCONNECTED_95 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_3 mux_left_track_15 ( + .in ( { chany_bottom_out[15] , chany_bottom_in[13] , chany_top_out[15] , + left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 , + SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_4 mux_left_track_17 ( + .in ( { chany_bottom_out[16] , chany_top_out[16] , chany_bottom_in[17] , + left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 , + SYNOPSYS_UNCONNECTED_101 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_5 mux_left_track_19 ( + .in ( { chany_bottom_out[17] , chany_top_out[17] , chany_bottom_in[21] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , + SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_6 mux_left_track_21 ( + .in ( { chany_bottom_out[19] , chany_top_out[19] , chany_bottom_in[25] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , + SYNOPSYS_UNCONNECTED_107 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4 mux_left_track_23 ( + .in ( { chany_bottom_out[20] , chany_top_out[20] , chany_bottom_in[29] , + chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , + SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_3 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_4 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_5 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_6 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_25 ( + .in ( { chany_bottom_out[21] , chany_top_out[21] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_27 ( + .in ( { chany_bottom_out[23] , chany_top_out[23] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_29 ( + .in ( { chany_bottom_out[24] , chany_top_out[24] , + left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_31 ( + .in ( { chany_bottom_out[25] , chany_top_out[25] , + left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_4 mux_left_track_33 ( + .in ( { chany_bottom_out[27] , chany_top_out[27] , + left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_5 mux_left_track_35 ( + .in ( { chany_bottom_out[28] , chany_top_out[28] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_6 mux_left_track_37 ( + .in ( { chany_bottom_out[29] , chany_top_out[29] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3 mux_left_track_51 ( + .in ( { chany_top_in[9] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_4 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_5 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_6 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_41 ( + .in ( { chany_top_in[29] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_45 ( + .in ( { chany_top_in[21] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_47 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_49 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_53 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_5 mux_left_track_55 ( + .in ( { chany_top_in[4] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2 mux_left_track_57 ( + .in ( { chany_top_in[2] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_5 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_6 pReset_N_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_N_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[25] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( left_bottom_grid_pin_41_[0] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_141 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_144 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_145 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1336 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[11] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..631f8d8 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__1__icv_in_design.top_only.pt.v @@ -0,0 +1,857 @@ +// +// +// +// +// +// +module sb_2__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ , + bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chany_bottom_out , + chanx_left_out , ccff_tail , pReset_W_in , pReset_N_out , + prog_clk_0_N_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input pReset_W_in ; +output pReset_N_out ; +input prog_clk_0_N_in ; + +wire ropt_net_162 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chany_top_out[4] , chany_top_out[20] , + chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_1 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[12] , + chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_2 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[2] , chanx_left_in[13] , + chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[3] , chanx_left_in[14] , + chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_2 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chany_top_out[7] , chany_top_out[21] , + chanx_left_in[10] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chany_top_out[8] , chany_top_out[23] , + chanx_left_in[9] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , + SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , + chany_top_out[12] , chany_top_out[27] , chanx_left_in[6] , + chanx_left_in[17] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , + SYNOPSYS_UNCONNECTED_25 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_3 mux_top_track_20 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , + chany_top_out[13] , chany_top_out[28] , chanx_left_in[5] , + chanx_left_in[16] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , + SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_4 mux_top_track_28 ( + .in ( { top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , + chany_top_out[15] , chany_top_out[29] , chanx_left_in[4] , + chanx_left_in[15] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_5 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[6] , chanx_left_in[17] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , + SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[7] , chanx_left_in[18] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , + SYNOPSYS_UNCONNECTED_37 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem mem_bottom_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_0 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , + top_right_grid_pin_1_[0] , chany_top_out[9] , chany_top_out[24] , + chanx_left_in[8] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , + SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , + chany_top_out[11] , chany_top_out[25] , chanx_left_in[7] , + chanx_left_in[18] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , + SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_11 ( + .in ( { ropt_net_162 , chany_bottom_out[25] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_left_in[16] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_0 mux_top_track_36 ( + .in ( { top_left_grid_pin_47_[0] , chany_top_out[16] , chanx_left_in[3] , + chanx_left_in[14] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , + SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chany_top_out[17] , chanx_left_in[2] , + chanx_left_in[13] , chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_2 mux_top_track_52 ( + .in ( { top_left_grid_pin_49_[0] , chany_top_out[19] , chanx_left_in[1] , + chanx_left_in[12] , chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_3 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , bottom_left_grid_pin_48_[0] , + chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_4 mux_left_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_in[1] , chany_top_out[8] , + left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size5 mux_left_track_11 ( + .in ( { chany_bottom_out[12] , chany_bottom_in[5] , chany_top_out[12] , + left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_4 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[4] , chanx_left_in[15] , + chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_mem mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[8] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , + SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_1 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_top_out[4] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 , + SYNOPSYS_UNCONNECTED_77 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_2 mux_left_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_in[0] , chany_top_out[7] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , + SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_3 mux_left_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_in[2] , chany_top_out[9] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , + SYNOPSYS_UNCONNECTED_83 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6 mux_left_track_9 ( + .in ( { ropt_net_162 , chany_bottom_in[4] , chany_top_out[11] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 , + SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_2 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_3 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_0 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , bottom_left_grid_pin_46_[0] , + chanx_left_in[9] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 , + SYNOPSYS_UNCONNECTED_89 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_1 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , bottom_left_grid_pin_47_[0] , + chanx_left_in[10] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , + SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( + .in ( { chany_bottom_out[13] , chany_bottom_in[9] , chany_top_out[13] , + left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , + SYNOPSYS_UNCONNECTED_95 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_3 mux_left_track_15 ( + .in ( { chany_bottom_out[15] , chany_bottom_in[13] , chany_top_out[15] , + left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 , + SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_4 mux_left_track_17 ( + .in ( { chany_bottom_out[16] , chany_top_out[16] , chany_bottom_in[17] , + left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 , + SYNOPSYS_UNCONNECTED_101 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_5 mux_left_track_19 ( + .in ( { chany_bottom_out[17] , chany_top_out[17] , chany_bottom_in[21] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , + SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_6 mux_left_track_21 ( + .in ( { chany_bottom_out[19] , chany_top_out[19] , chany_bottom_in[25] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , + SYNOPSYS_UNCONNECTED_107 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4 mux_left_track_23 ( + .in ( { chany_bottom_out[20] , chany_top_out[20] , chany_bottom_in[29] , + chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , + SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_3 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_4 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_5 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_6 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_25 ( + .in ( { chany_bottom_out[21] , chany_top_out[21] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_27 ( + .in ( { chany_bottom_out[23] , chany_top_out[23] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_29 ( + .in ( { chany_bottom_out[24] , chany_top_out[24] , + left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_31 ( + .in ( { chany_bottom_out[25] , chany_top_out[25] , + left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_4 mux_left_track_33 ( + .in ( { chany_bottom_out[27] , chany_top_out[27] , + left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_5 mux_left_track_35 ( + .in ( { chany_bottom_out[28] , chany_top_out[28] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_6 mux_left_track_37 ( + .in ( { chany_bottom_out[29] , chany_top_out[29] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3 mux_left_track_51 ( + .in ( { chany_top_in[9] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_4 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_5 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_6 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_41 ( + .in ( { chany_top_in[29] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_45 ( + .in ( { chany_top_in[21] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_47 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_49 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_53 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_5 mux_left_track_55 ( + .in ( { chany_top_in[4] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2 mux_left_track_57 ( + .in ( { chany_top_in[2] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_5 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_6 pReset_N_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_N_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[25] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( left_bottom_grid_pin_41_[0] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_141 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_144 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_145 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1336 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[11] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v new file mode 100644 index 0000000..a961fdf --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v @@ -0,0 +1,3436 @@ +// +// +// +// +// +// +module sb_2__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__const1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__2__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_140 ) ) ; +endmodule + + +module sb_2__2__const1_51 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__2__const1_51 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_50 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__2__const1_50 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_138 ) ) ; +endmodule + + +module sb_2__2__const1_49 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__2__const1_49 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_136 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( copt_net_165 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1335 ( .A ( mem_out[1] ) , + .X ( copt_net_165 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_35 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__const1_48 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_48 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_134 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__2__const1_47 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_35 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_47 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_46 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_34 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_46 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_132 ) ) ; +endmodule + + +module sb_2__2__const1_45 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_33 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_45 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_130 ) ) ; +endmodule + + +module sb_2__2__const1_44 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_32 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_44 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) ) ; +endmodule + + +module sb_2__2__const1_43 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_31 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_126 ) ) ; +endmodule + + +module sb_2__2__const1_42 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_124 ) ) ; +endmodule + + +module sb_2__2__const1_41 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_122 ) ) ; +endmodule + + +module sb_2__2__const1_40 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_120 ) ) ; +endmodule + + +module sb_2__2__const1_39 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_38 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_26 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_118 ) ) ; +endmodule + + +module sb_2__2__const1_37 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) ) ; +endmodule + + +module sb_2__2__const1_36 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) ) ; +endmodule + + +module sb_2__2__const1_35 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_148 ) ) ; +endmodule + + +module sb_2__2__const1_34 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_33 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__const1_32 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_31 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_109 ) ) ; +endmodule + + +module sb_2__2__const1_30 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_107 ) ) ; +endmodule + + +module sb_2__2__const1_29 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_105 ) ) ; +endmodule + + +module sb_2__2__const1_28 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_27 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) ) ; +endmodule + + +module sb_2__2__const1_26 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module sb_2__2__const1_25 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_99 ) ) ; +endmodule + + +module sb_2__2__const1_24 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_97 ) ) ; +endmodule + + +module sb_2__2__const1_23 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) ) ; +endmodule + + +module sb_2__2__const1_22 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_21 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__const1_20 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__const1_19 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_91 ) ) ; +endmodule + + +module sb_2__2__const1_18 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) ) ; +endmodule + + +module sb_2__2__const1_17 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) ) ; +endmodule + + +module sb_2__2__const1_16 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) ) ; +endmodule + + +module sb_2__2__const1_15 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) ) ; +endmodule + + +module sb_2__2__const1_14 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_81 ) ) ; +endmodule + + +module sb_2__2__const1_13 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__const1_12 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_195 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( ccff_head[0] ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_158 ) , + .X ( copt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ropt_net_198 ) , + .X ( copt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_160 ) , + .X ( copt_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_161 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_159 ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( ropt_net_196 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1368 ( .A ( ropt_net_199 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1369 ( .A ( ropt_net_197 ) , + .X ( ropt_net_199 ) ) ; +endmodule + + +module sb_2__2__const1_11 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_10 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_78 ) ) ; +endmodule + + +module sb_2__2__const1_9 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_76 ) ) ; +endmodule + + +module sb_2__2__const1_8 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_141 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__2__const1_7 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_72 ) ) ; +endmodule + + +module sb_2__2__const1_6 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__const1_5 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_4 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) ) ; +endmodule + + +module sb_2__2__const1_3 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__const1_2 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) ) ; +endmodule + + +module sb_2__2__const1_1 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) ) ; +endmodule + + +module sb_2__2__const1_0 ( const1 ) ; +output [0:0] const1 ; + +wire [0:0] const1_0 ; + +assign const1_0[0] = 1'b1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) ) ; +endmodule + + +module sb_2__2_ ( pReset , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , + bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , SC_IN_BOT , SC_OUT_BOT , pReset_W_in , prog_clk_0_S_in ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_BOT ; +output SC_OUT_BOT ; +input pReset_W_in ; +input prog_clk_0_S_in ; + +wire ropt_net_177 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_27_sram ; +wire [0:1] mux_tree_tapbuf_size2_28_sram ; +wire [0:1] mux_tree_tapbuf_size2_29_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_30_sram ; +wire [0:1] mux_tree_tapbuf_size2_31_sram ; +wire [0:1] mux_tree_tapbuf_size2_32_sram ; +wire [0:1] mux_tree_tapbuf_size2_33_sram ; +wire [0:1] mux_tree_tapbuf_size2_34_sram ; +wire [0:1] mux_tree_tapbuf_size2_35_sram ; +wire [0:1] mux_tree_tapbuf_size2_36_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_35_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__2__mux_tree_tapbuf_size4_0 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_1 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_2 mux_bottom_track_5 ( + .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_3 mux_bottom_track_7 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_4 mux_bottom_track_9 ( + .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_5 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_6 mux_left_track_1 ( + .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_7 mux_left_track_3 ( + .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_8 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_9 mux_left_track_7 ( + .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_10 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4 mux_left_track_11 ( + .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_13 ( + .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_25 ( + .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_41 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_10 mux_bottom_track_43 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_11 mux_bottom_track_47 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_12 mux_bottom_track_49 ( + .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_13 mux_bottom_track_51 ( + .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_14 mux_bottom_track_53 ( + .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_13 ( + .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_15 ( + .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_17 ( + .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_19 ( + .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_21 ( + .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_23 ( + .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_27 ( + .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_23 mux_left_track_31 ( + .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_24 mux_left_track_33 ( + .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_25 mux_left_track_35 ( + .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_26 mux_left_track_37 ( + .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_27 mux_left_track_39 ( + .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_27_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_28 mux_left_track_41 ( + .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_28_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_29 mux_left_track_43 ( + .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_29_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_30 mux_left_track_45 ( + .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_30_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_31 mux_left_track_47 ( + .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_31_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_32 mux_left_track_49 ( + .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_32_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_33 mux_left_track_51 ( + .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_33_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_34 mux_left_track_55 ( + .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_34_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_35 mux_left_track_57 ( + .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_35_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2 mux_left_track_59 ( + .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_36_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_15 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_17 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_19 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_23 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_25 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_39 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_41 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_bottom_track_43 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_bottom_track_47 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_bottom_track_49 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_bottom_track_51 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_23 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_24 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_25 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_26 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_27 mem_left_track_39 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_27_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_28 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_28_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_29 mem_left_track_43 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_29_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_30 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_30_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_31 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_31_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_32 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_32_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_33 mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_33_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_34 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_34_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_35 mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_36_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_29 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_1 mux_bottom_track_45 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] , + chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_2 mux_left_track_29 ( + .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size3 mux_left_track_53 ( + .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[0] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[17] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[18] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[19] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[28] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[29] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1347 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[15] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v new file mode 100644 index 0000000..2f2d151 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v @@ -0,0 +1,3730 @@ +// +// +// +// +// +// +module sb_2__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( copt_net_165 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1335 ( .A ( mem_out[1] ) , + .X ( copt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_35 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_134 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_35 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_34 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_33 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_32 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_31 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_26 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_195 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( ccff_head[0] ) , + .X ( copt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_158 ) , + .X ( copt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ropt_net_198 ) , + .X ( copt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_160 ) , + .X ( copt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_161 ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_159 ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( ropt_net_196 ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1368 ( .A ( ropt_net_199 ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1369 ( .A ( ropt_net_197 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_141 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2_ ( pReset , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , + bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , SC_IN_BOT , SC_OUT_BOT , pReset_W_in , prog_clk_0_S_in , VDD , + VSS ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_BOT ; +output SC_OUT_BOT ; +input pReset_W_in ; +input prog_clk_0_S_in ; +input VDD ; +input VSS ; + +wire ropt_net_177 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_27_sram ; +wire [0:1] mux_tree_tapbuf_size2_28_sram ; +wire [0:1] mux_tree_tapbuf_size2_29_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_30_sram ; +wire [0:1] mux_tree_tapbuf_size2_31_sram ; +wire [0:1] mux_tree_tapbuf_size2_32_sram ; +wire [0:1] mux_tree_tapbuf_size2_33_sram ; +wire [0:1] mux_tree_tapbuf_size2_34_sram ; +wire [0:1] mux_tree_tapbuf_size2_35_sram ; +wire [0:1] mux_tree_tapbuf_size2_36_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_35_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__2__mux_tree_tapbuf_size4_0 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_1 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_2 mux_bottom_track_5 ( + .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_3 mux_bottom_track_7 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_4 mux_bottom_track_9 ( + .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_5 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_6 mux_left_track_1 ( + .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_7 mux_left_track_3 ( + .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_8 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_9 mux_left_track_7 ( + .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_10 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4 mux_left_track_11 ( + .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_13 ( + .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_25 ( + .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_41 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chany_bottom_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_10 mux_bottom_track_43 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_bottom_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_11 mux_bottom_track_47 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_12 mux_bottom_track_49 ( + .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chany_bottom_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_13 mux_bottom_track_51 ( + .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_14 mux_bottom_track_53 ( + .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_13 ( + .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_15 ( + .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_17 ( + .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_19 ( + .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_21 ( + .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_23 ( + .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_27 ( + .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_23 mux_left_track_31 ( + .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_24 mux_left_track_33 ( + .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_25 mux_left_track_35 ( + .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_26 mux_left_track_37 ( + .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_27 mux_left_track_39 ( + .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_27_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_28 mux_left_track_41 ( + .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_28_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_29 mux_left_track_43 ( + .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_29_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_left_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_30 mux_left_track_45 ( + .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_30_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_31 mux_left_track_47 ( + .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_31_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chanx_left_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_32 mux_left_track_49 ( + .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_32_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_left_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_33 mux_left_track_51 ( + .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_33_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_34 mux_left_track_55 ( + .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_34_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_left_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_35 mux_left_track_57 ( + .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_35_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2 mux_left_track_59 ( + .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_36_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_15 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_17 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_19 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_23 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_25 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_39 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_41 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_bottom_track_43 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_bottom_track_47 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_bottom_track_49 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_bottom_track_51 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_23 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_24 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_25 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_26 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_26_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_27 mem_left_track_39 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_27_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_28 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_28_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_29 mem_left_track_43 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_29_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_30 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_30_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_31 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_31_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_32 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_32_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_33 mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_33_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_34 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_34_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_35 mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_35_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_36_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_29 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_1 mux_bottom_track_45 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] , + chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_2 mux_left_track_29 ( + .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size3 mux_left_track_53 ( + .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[0] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[17] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[18] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[19] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[28] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[29] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , + .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1347 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v new file mode 100644 index 0000000..29c3334 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v @@ -0,0 +1,2853 @@ +// +// +// +// +// +// +module sb_2__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_140 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_138 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_136 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( copt_net_165 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1335 ( .A ( mem_out[1] ) , + .X ( copt_net_165 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_35 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_134 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_35 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_34 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_132 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_33 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_130 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_32 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_31 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_126 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_124 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_122 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_120 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_26 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_118 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_148 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_109 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_107 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_105 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_99 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_97 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_91 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_81 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_195 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( ccff_head[0] ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_158 ) , + .X ( copt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ropt_net_198 ) , + .X ( copt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_160 ) , + .X ( copt_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_161 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_159 ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( ropt_net_196 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1368 ( .A ( ropt_net_199 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1369 ( .A ( ropt_net_197 ) , + .X ( ropt_net_199 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_78 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_76 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_141 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_72 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) ) ; +endmodule + + +module sb_2__2_ ( pReset , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , + bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , SC_IN_BOT , SC_OUT_BOT , pReset_W_in , prog_clk_0_S_in ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_BOT ; +output SC_OUT_BOT ; +input pReset_W_in ; +input prog_clk_0_S_in ; + +wire ropt_net_177 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_27_sram ; +wire [0:1] mux_tree_tapbuf_size2_28_sram ; +wire [0:1] mux_tree_tapbuf_size2_29_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_30_sram ; +wire [0:1] mux_tree_tapbuf_size2_31_sram ; +wire [0:1] mux_tree_tapbuf_size2_32_sram ; +wire [0:1] mux_tree_tapbuf_size2_33_sram ; +wire [0:1] mux_tree_tapbuf_size2_34_sram ; +wire [0:1] mux_tree_tapbuf_size2_35_sram ; +wire [0:1] mux_tree_tapbuf_size2_36_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_35_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__2__mux_tree_tapbuf_size4_0 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_1 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_2 mux_bottom_track_5 ( + .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_3 mux_bottom_track_7 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_4 mux_bottom_track_9 ( + .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_5 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_6 mux_left_track_1 ( + .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_7 mux_left_track_3 ( + .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_8 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_9 mux_left_track_7 ( + .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_10 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4 mux_left_track_11 ( + .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_13 ( + .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_25 ( + .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_41 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_10 mux_bottom_track_43 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_11 mux_bottom_track_47 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_12 mux_bottom_track_49 ( + .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_13 mux_bottom_track_51 ( + .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_14 mux_bottom_track_53 ( + .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_13 ( + .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_15 ( + .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_17 ( + .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_19 ( + .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_21 ( + .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_23 ( + .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_27 ( + .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_23 mux_left_track_31 ( + .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_24 mux_left_track_33 ( + .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_25 mux_left_track_35 ( + .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_26 mux_left_track_37 ( + .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_27 mux_left_track_39 ( + .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_27_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_28 mux_left_track_41 ( + .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_28_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_29 mux_left_track_43 ( + .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_29_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_30 mux_left_track_45 ( + .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_30_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_31 mux_left_track_47 ( + .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_31_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_32 mux_left_track_49 ( + .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_32_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_33 mux_left_track_51 ( + .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_33_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_34 mux_left_track_55 ( + .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_34_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_35 mux_left_track_57 ( + .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_35_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2 mux_left_track_59 ( + .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_36_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_15 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_17 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_19 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_23 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_25 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_39 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_41 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_bottom_track_43 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_bottom_track_47 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_bottom_track_49 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_bottom_track_51 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_23 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_24 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_25 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_26 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_27 mem_left_track_39 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_27_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_28 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_28_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_29 mem_left_track_43 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_29_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_30 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_30_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_31 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_31_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_32 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_32_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_33 mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_33_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_34 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_34_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_35 mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_36_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_29 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_1 mux_bottom_track_45 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] , + chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_2 mux_left_track_29 ( + .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size3 mux_left_track_53 ( + .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[0] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[17] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[18] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[19] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[28] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[29] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1347 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[15] ) ) ; +endmodule + + diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.top_only.pt.v b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.top_only.pt.v new file mode 100644 index 0000000..77ab7a8 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/modules/verilog/sb_2__2__icv_in_design.top_only.pt.v @@ -0,0 +1,747 @@ +// +// +// +// +// +// +module sb_2__2_ ( pReset , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , + bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , SC_IN_BOT , SC_OUT_BOT , pReset_W_in , prog_clk_0_S_in ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_BOT ; +output SC_OUT_BOT ; +input pReset_W_in ; +input prog_clk_0_S_in ; + +wire ropt_net_177 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_27_sram ; +wire [0:1] mux_tree_tapbuf_size2_28_sram ; +wire [0:1] mux_tree_tapbuf_size2_29_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_30_sram ; +wire [0:1] mux_tree_tapbuf_size2_31_sram ; +wire [0:1] mux_tree_tapbuf_size2_32_sram ; +wire [0:1] mux_tree_tapbuf_size2_33_sram ; +wire [0:1] mux_tree_tapbuf_size2_34_sram ; +wire [0:1] mux_tree_tapbuf_size2_35_sram ; +wire [0:1] mux_tree_tapbuf_size2_36_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_35_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__2__mux_tree_tapbuf_size4_0 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_1 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_2 mux_bottom_track_5 ( + .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_3 mux_bottom_track_7 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_4 mux_bottom_track_9 ( + .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_5 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_6 mux_left_track_1 ( + .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_7 mux_left_track_3 ( + .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_8 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_9 mux_left_track_7 ( + .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_10 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4 mux_left_track_11 ( + .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_13 ( + .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_25 ( + .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_41 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_10 mux_bottom_track_43 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_11 mux_bottom_track_47 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_12 mux_bottom_track_49 ( + .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_13 mux_bottom_track_51 ( + .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_14 mux_bottom_track_53 ( + .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_13 ( + .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_15 ( + .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_17 ( + .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_19 ( + .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_21 ( + .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_23 ( + .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_27 ( + .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_23 mux_left_track_31 ( + .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_24 mux_left_track_33 ( + .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_25 mux_left_track_35 ( + .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_26 mux_left_track_37 ( + .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_27 mux_left_track_39 ( + .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_27_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_28 mux_left_track_41 ( + .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_28_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_29 mux_left_track_43 ( + .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_29_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_30 mux_left_track_45 ( + .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_30_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_31 mux_left_track_47 ( + .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_31_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_32 mux_left_track_49 ( + .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_32_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_33 mux_left_track_51 ( + .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_33_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_34 mux_left_track_55 ( + .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_34_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_35 mux_left_track_57 ( + .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_35_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2 mux_left_track_59 ( + .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_36_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_15 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_17 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_19 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_23 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_25 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_39 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_41 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_bottom_track_43 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_bottom_track_47 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_bottom_track_49 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_bottom_track_51 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_23 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_24 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_25 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_26 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_27 mem_left_track_39 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_27_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_28 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_28_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_29 mem_left_track_43 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_29_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_30 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_30_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_31 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_31_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_32 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_32_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_33 mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_33_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_34 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_34_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_35 mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_36_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_29 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_1 mux_bottom_track_45 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] , + chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_2 mux_left_track_29 ( + .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size3 mux_left_track_53 ( + .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[0] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[17] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[18] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[19] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[28] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[29] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1347 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[15] ) ) ; +endmodule + +