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Merge pull request #66 from lnis-uofu/xt_dev 

FPGA I/O cell Update
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tangxifan 2020-12-11 18:08:18 -07:00 committed by GitHub
parent 00b1740b44 b38a948a56
commit 8def618a52
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GPG Key ID: 4AEE18F83AFDEB23
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*.gds filter=lfs diff=lfs merge=lfs -text
*.spef filter=lfs diff=lfs merge=lfs -text
TESTBENCH/**/*.v filter=lfs diff=lfs merge=lfs -text
TESTBENCH/*/pnr/verilog_testbench/*_tb.v filter=lfs diff=lfs merge=lfs -text

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DOC/source/datasheet/sofa_hd/figures/sofa_hd_embedded_io_test_waveform.svg Normal file
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DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst
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@ -21,7 +21,7 @@ As shown in :numref:`fig_sofa_hd_embedded_io_schematic`, the I/O circuit used in
- An internal configurable memory element to control the direction of I/O cell
The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where
The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC (which requires an active-low signal to enable output directionality), where
- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode
@ -35,6 +35,21 @@ The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC,
Schematic of embedded I/O cell used in FPGA
:numref:`fig_sofa_hd_embedded_io_test_waveform` shows an example waveform about how the I/O cell works:
- When ``IO_ISOL_N`` is enabled/disabled
- When operates in input mode
- When operates in output mode
.. _fig_sofa_hd_embedded_io_test_waveform:
.. figure:: ./figures/sofa_hd_embedded_io_test_waveform.svg
:scale: 30%
:alt: Schematic of embedded I/O cell used in FPGA
An example of waveforms of embedded I/O cell used in FPGA
.. _sofa_hd_circuit_design_mux:
Multiplexer

2
HDL/common/digital_io_hd.v
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@ -37,7 +37,7 @@ module EMBEDDED_IO_HD (
sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (.B_N(IO_ISOL_N),
.A(FPGA_DIR),
.X(SOC_DIR)
);
);
// Use drive-strength 4 for a high fan-out from global routing architecture
sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR), .Y(SOC_DIR_N));

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