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[HDL] Update caravel include netlist to use simulation without power pins

This commit is contained in:
tangxifan 2020-12-16 20:26:53 -07:00
parent 2d8b4b59db
commit 9c2764723f
1 changed files with 5 additions and 1 deletions
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6
HDL/common/caravel_qlsofa_hd_rtl_include_netlists.v
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@ -50,4 +50,8 @@
// Use Post-PnR netlists of QLSOFA HD FPGA
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/user_project_wrapper.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v"
`ifdef USE_POWER_PINS
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v"
`else
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`endif