From 9c2764723f7682d4173e02258ead80c5fc727e9f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 16 Dec 2020 20:26:53 -0700 Subject: [PATCH] [HDL] Update caravel include netlist to use simulation without power pins --- HDL/common/caravel_qlsofa_hd_rtl_include_netlists.v | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/HDL/common/caravel_qlsofa_hd_rtl_include_netlists.v b/HDL/common/caravel_qlsofa_hd_rtl_include_netlists.v index e4cb2d4..456fd0b 100644 --- a/HDL/common/caravel_qlsofa_hd_rtl_include_netlists.v +++ b/HDL/common/caravel_qlsofa_hd_rtl_include_netlists.v @@ -50,4 +50,8 @@ // Use Post-PnR netlists of QLSOFA HD FPGA `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/user_project_wrapper.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v" +`ifdef USE_POWER_PINS + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v" +`else + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`endif