mirror of https://github.com/lnis-uofu/SOFA.git
Merge pull request #61 from lnis-uofu/ganesh_dev
SOFA CHD Post-PnR Netlist
This commit is contained in:
tangxifan
GitHub
commit
0c761ebc05
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@ -0,0 +1,20 @@
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#!/bin/bash
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SCAN_SOFA_HD_KEY="FPGA1212_FLAT_HD_SKY_PNR"
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SCAN_QLSOFA_HD_KEY="FPGA1212_RESET_HD_SKY_PNR"
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SCAN_SOFA_CHD_KEY="FPGA1212_SOFA_CHD_PNR"
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SCAN_QLAP3_KEY="FPGA1212_QLAP3_PNR"
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# TODO: Strip comments while reading using yq
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# TODO: Add SOFA_CHD and QLAP3 for later
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for repo in SOFA_HD QLSOFA_HD ; do
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ScanDir=$(eval "echo \$SCAN_${repo}_KEY")
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action_filename=$(echo "$repo" | awk '{print tolower($0)}')
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repo_name=$(echo "$repo" | sed "s/_/-/")
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echo $ScanDir $action_filename $repo_name
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cat deploy_sofa.yaml | \
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sed -e "s/SOFA_HD/${repo}/" \
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-e "s/SOFA-HD/${repo_name}/" \
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-e "s/FPGA1212_FLAT_HD_SKY_PNR/${ScanDir}/" | \
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yq r - -X > ./workflows/deploy_${action_filename}.yaml
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done
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@ -14,11 +14,11 @@ env:
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PROJ_SUFFIX: &PROJ_SUFFIX
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SOFA_HD
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DEST_DIR: &DEST_DIR
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Caravel-SOFA_HD
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Caravel-SOFA-HD
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DEST_REPO: &DEST_REPO
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lnis-uofu/actions_test_repo
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lnis-uofu/Caravel-SOFA-HD
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REPO_KEY: &REPO_KEY
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${{ secrets.TEST_REPO_KEY }}
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${{ secrets.SOFA_HD_KEY }}
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on:
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push:
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@ -26,6 +26,8 @@ on:
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- '.github/**'
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- 'SynRepoConfig/**'
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- '$SCAN_DIRECTORY'
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branches:
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- ganesh_dev
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pull_request:
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types: closed
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branches:
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@ -65,10 +67,12 @@ jobs:
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run: cd /usr/local/workspace && pwd && ls && bash ./SOFA-Chips/.github/workflows/perform_precheck.sh
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- name: Deploy files
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# if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }}
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run: bash ./SOFA-Chips/.github/workflows/sync_repo.sh
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- name: Deploy Changes
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uses: peaceiris/actions-gh-pages@v3
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# if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }}
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with:
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user_name: "lnis.uofu"
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user_email: "lnis.uofu@gmail.com"
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@ -78,3 +82,19 @@ jobs:
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publish_branch: master
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disable_nojekyll: true
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commit_message: '[Deployment] ${{ github.event.head_commit.message }}'
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# - name: Deploy files to localbranch
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# if: ${{! (github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged') }}
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# run: bash ./SOFA-Chips/.github/workflows/sync_repo.sh
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# - name: Deploy Changes localbranch
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# uses: peaceiris/actions-gh-pages@v3
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# if: ${{! (github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged') }}
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# with:
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# user_name: "lnis.uofu"
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# user_email: "lnis.uofu@gmail.com"
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# github_token: ${{ secrets.GITHUB_TOKEN }}
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# publish_dir: ./SOFA-Chips/local_checks/Caravel-SOFA_HD
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# publish_branch: master
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# disable_nojekyll: true
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# commit_message: '[Deployment] ${{ github.event.head_commit.message }}'
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@ -0,0 +1,68 @@
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name: Caravel-QLSOFA_HD Deployment
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# = = = Env Variable = = = = =
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# secrets.TEST_REPO_KEY
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# secrets.QLSOFA_HD_KEY
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# secrets.SOFA_CHD_KEY
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# secrets.QLQLSOFA_HD_KEY
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# secrets.QLAP3_KEY
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# yq r -X deploy_sofa.yaml > ./workflows/deploy_sofa_hd.yaml
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env:
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SCAN_DIRECTORY: 'FPGA1212_RESET_HD_SKY_PNR/**'
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PROJ_SUFFIX: QLSOFA_HD
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DEST_DIR: Caravel-QLSOFA-HD
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DEST_REPO: lnis-uofu/Caravel-QLSOFA-HD
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REPO_KEY: ${{ secrets.QLSOFA_HD_KEY }}
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on:
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push:
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paths:
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- '.github/**'
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- 'SynRepoConfig/**'
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- '$SCAN_DIRECTORY'
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branches:
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- ganesh_dev
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pull_request:
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types: closed
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branches:
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- master
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jobs:
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linux:
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name: Updating release repository
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runs-on: ubuntu-latest
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steps:
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- name: Checkout SOFA-Chips
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uses: actions/checkout@v2
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with:
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path: SOFA-Chips
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- name: Checkout caravel repo
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uses: actions/checkout@master
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with:
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repository: lnis-uofu/Caravel-QLSOFA-HD
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path: Caravel-QLSOFA-HD
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- name: Checkout open_mpw_precheck repo
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uses: actions/checkout@master
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with:
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repository: efabless/open_mpw_precheck
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path: open_mpw_precheck
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- name: Perform checks with open_mpw_precheck
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uses: ganeshgore/docker-run-action@49cd3a1
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with:
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image: goreganesh/open_mpw_prechecker
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options: >
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-v ${{github.workspace}}/open_mpw_precheck:/usr/local/bin -v ${{github.workspace}}:/usr/local/workspace -e DEST_DIR=$DEST_DIR -e SCAN_DIRECTORY=$SCAN_DIRECTORY --workdir /usr/local/workspace
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run: cd /usr/local/workspace && pwd && ls && bash ./SOFA-Chips/.github/workflows/perform_precheck.sh
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- name: Deploy files
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# if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }}
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run: bash ./SOFA-Chips/.github/workflows/sync_repo.sh
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- name: Deploy Changes
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uses: peaceiris/actions-gh-pages@v3
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# if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }}
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with:
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user_name: "lnis.uofu"
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user_email: "lnis.uofu@gmail.com"
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deploy_key: ${{ secrets.QLSOFA_HD_KEY }}
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external_repository: lnis-uofu/Caravel-QLSOFA-HD
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publish_dir: Caravel-QLSOFA-HD
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publish_branch: master
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disable_nojekyll: true
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commit_message: '[Deployment] ${{ github.event.head_commit.message }}'
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@ -9,15 +9,17 @@ name: Caravel-SOFA_HD Deployment
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env:
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SCAN_DIRECTORY: 'FPGA1212_FLAT_HD_SKY_PNR/**'
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PROJ_SUFFIX: SOFA_HD
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DEST_DIR: Caravel-SOFA_HD
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DEST_REPO: lnis-uofu/actions_test_repo
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REPO_KEY: ${{ secrets.TEST_REPO_KEY }}
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DEST_DIR: Caravel-SOFA-HD
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DEST_REPO: lnis-uofu/Caravel-SOFA-HD
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REPO_KEY: ${{ secrets.SOFA_HD_KEY }}
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on:
|
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push:
|
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paths:
|
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- '.github/**'
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- 'SynRepoConfig/**'
|
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- '$SCAN_DIRECTORY'
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branches:
|
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- ganesh_dev
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pull_request:
|
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types: closed
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branches:
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@ -34,8 +36,8 @@ jobs:
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- name: Checkout caravel repo
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uses: actions/checkout@master
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with:
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repository: lnis-uofu/actions_test_repo
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path: Caravel-SOFA_HD
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repository: lnis-uofu/Caravel-SOFA-HD
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path: Caravel-SOFA-HD
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- name: Checkout open_mpw_precheck repo
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uses: actions/checkout@master
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with:
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@ -50,15 +52,17 @@ jobs:
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|
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run: cd /usr/local/workspace && pwd && ls && bash ./SOFA-Chips/.github/workflows/perform_precheck.sh
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- name: Deploy files
|
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# if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }}
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run: bash ./SOFA-Chips/.github/workflows/sync_repo.sh
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- name: Deploy Changes
|
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uses: peaceiris/actions-gh-pages@v3
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# if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }}
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with:
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user_name: "lnis.uofu"
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user_email: "lnis.uofu@gmail.com"
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deploy_key: ${{ secrets.TEST_REPO_KEY }}
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external_repository: lnis-uofu/actions_test_repo
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publish_dir: Caravel-SOFA_HD
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deploy_key: ${{ secrets.SOFA_HD_KEY }}
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external_repository: lnis-uofu/Caravel-SOFA-HD
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publish_dir: Caravel-SOFA-HD
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publish_branch: master
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disable_nojekyll: true
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commit_message: '[Deployment] ${{ github.event.head_commit.message }}'
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@ -16,33 +16,47 @@ AddLine="use fpga_top fpga_top_uut\n"\
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"transform 1 0 0 0 1 0\n"\
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"box 0 0 2500 3000"
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sed -i "s/<< properties >>/${AddLine}\n<< properties >>/" ./mag/user_project_wrapper.mag
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# Running magic to merge fpga_top
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echo "[Info] Merged with user_project_wrapper"
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# = = = Running magic to merge fpga_top with user_project_wrapper = = = = = = =
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MAGTYPE=mag \
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magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/current/sky130A.magicrc \
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-noconsole -dnull \
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../SOFA-Chips/SCRIPT/merge_fpga_top.tcl </dev/null | tee magic_drc.log
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../SOFA-Chips/SCRIPT/merge_fpga_top.tcl </dev/null > \
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/usr/local/workspace/${DEST_DIR}/checks/magic_merge_user_project_wrapper.log
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echo "[Info] merge fpga-top"
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# = = = = = = = = = = = = = Build Caravel = = = = = = = = = = = = = = = = = = =
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for i in {1..30}; do sleep 1m; echo "Still shipping"; done & # 30 min timeout for merge GDS
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make ship
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kill %1
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echo "[Info] Finished shiping chip"
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rm -f gds/caravel.old.gds
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# = = = = = = = = = = Build Caravel with Klayout = = = = = = = = = = = = = = =
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klayout -r ../SOFA-Chips/SCRIPT/merge_caravel_klayout.py -zz
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echo "[Info] Finished shiping chip with Klayout"
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rm -rf ./gds/fpga_top*
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rm -rf ./gds/user_project_wrapper_empty.gds
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rm -rf ./gds/user_proj_example.gds
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mv ./gds/caravel_merged.gds ./gds/caravel.gds
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# = = = = = = = = = Build Caravel with Magic = = = = = = = = = = = = = = = = =
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# for i in {1..30}; do sleep 1m; echo "Still shipping"; done & # 30 min timeout for merge GDS
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# make ship
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# kill %1
|
||||
# echo "[Info] Finished shiping chip with Magic "
|
||||
# rm -f gds/caravel.old.gds
|
||||
|
||||
# = = = = = = = = = = = = = Perform Open MPW Checks = = = = = = = = = = = = = =
|
||||
python3 /usr/local/bin/open_mpw_prechecker.py \
|
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cd /usr/local/bin
|
||||
python3 open_mpw_prechecker.py \
|
||||
--target_path /usr/local/workspace/${DEST_DIR} \
|
||||
--pdk_root $PDK_ROOT
|
||||
echo "[Info] Finished MPW Prechecker"
|
||||
|
||||
# = = = = = = = Convert DRC Errors to RDB = = = = = = = = = = = = = = = = = = =
|
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cd /usr/local/workspace/${DEST_DIR}
|
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if test -f "./checks/caravel.magic.drc"; then
|
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python3 ../SOFA-Chips/SCRIPT/magic_drc_to_rdb.py \
|
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-magic_drc_in ./checks/caravel.magic.drc
|
||||
-rdb_out ./checks/caravel.magic.rdb
|
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echo "[Info] Converted errors in RDB format"
|
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fi
|
||||
echo "[Info] Converted errors in RDB format"
|
||||
|
||||
# = = = = = = = Clean up repo = = = = = = = = = = = = = = = = = = =
|
||||
rm -rf user_project_wrapper.mag
|
||||
|
|
|
|||
|
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@ -17,3 +17,7 @@ cd ${DEST_DIR}
|
|||
sed -i -e "s/^/\n/" source_commit_hash.txt
|
||||
sed -i -e "s/^/${GITHUB_SHA}\n/" source_commit_hash.txt
|
||||
sed -i -e "s/^/$(date)\n/" source_commit_hash.txt
|
||||
|
||||
|
||||
# Clean up file from repo
|
||||
git checkout master qflow
|
||||
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BIN
FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef (Stored with Git LFS)
BIN
FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef (Stored with Git LFS)
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|
|
@ -0,0 +1,18 @@
|
|||
| Module | Util| Area| Sites| Insts| Std_Cells
|
||||
|--------------------|----------|-----------------|-------|-------|-------
|
||||
|fpga_core_uut/sb_0__0_ | 31.45 | 8728.371200 | 6976 | 1 | 868
|
||||
|fpga_core_uut/sb_0__11_ | 47.54 | 9449.062400 | 7552 | 11 | 945
|
||||
|fpga_core_uut/sb_0__12_ | 31.62 | 8728.371200 | 6976 | 1 | 865
|
||||
|fpga_core_uut/sb_11__0_ | 47.53 | 10970.521600 | 8768 | 11 | 1033
|
||||
|fpga_core_uut/sb_11__11_ | 64.3 | 11691.212800 | 9344 | 121 | 999
|
||||
|fpga_core_uut/sb_11__12_ | 47.15 | 10970.521600 | 8768 | 11 | 1021
|
||||
|fpga_core_uut/sb_12__0_ | 42.63 | 8728.371200 | 6976 | 1 | 827
|
||||
|fpga_core_uut/sb_12__11_ | 54.85 | 9449.062400 | 7552 | 11 | 931
|
||||
|fpga_core_uut/sb_12__12_ | 43.81 | 8728.371200 | 6976 | 1 | 823
|
||||
|fpga_core_uut/cbx_12__0_ | 63.67 | 5765.529600 | 4608 | 12 | 558
|
||||
|fpga_core_uut/cbx_12__11_ | 78.43 | 5765.529600 | 4608 | 132 | 372
|
||||
|fpga_core_uut/cbx_12__12_ | 77.47 | 5765.529600 | 4608 | 12 | 366
|
||||
|fpga_core_uut/cby_0__12_ | 20.51 | 5044.838400 | 4032 | 12 | 556
|
||||
|fpga_core_uut/cby_11__12_ | 82.22 | 5044.838400 | 4032 | 132 | 291
|
||||
|fpga_core_uut/cby_12__12_ | 83.28 | 5044.838400 | 4032 | 12 | 267
|
||||
|fpga_core_uut/grid_clb_12__12_ | 77.94 | 11531.059200 | 9216 | 144 | 597
|
||||
|
|
|
@ -0,0 +1,35 @@
|
|||
Ref Name Total Area Utilization_% Instance Count
|
||||
----------------------------------------------------------------------------------------------------
|
||||
sky130_fd_sc_hd__dfxtp_4 1330730.025600 12.95 55977
|
||||
sky130_fd_sc_hd__mux2_1 1314450.662400 12.79 116728
|
||||
sky130_fd_sc_hd__buf_8 304882.406400 2.97 20306
|
||||
sky130_fd_sc_hd__dfxtp_1 237007.308800 2.31 11839
|
||||
sky130_fd_sc_hd__buf_6 156502.598400 1.52 13898
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 71628.697600 0.70 7156
|
||||
sky130_fd_sc_hd__buf_1 71340.921600 0.69 19006
|
||||
sky130_fd_sc_hd__sdfxtp_1 60538.060800 0.59 2304
|
||||
sky130_fd_sc_hd__inv_8 44953.113600 0.44 3992
|
||||
sky130_fd_sc_hd__bufbuf_16 43331.558400 0.42 1332
|
||||
sky130_fd_sc_hd__inv_1 40520.112000 0.39 10795
|
||||
sky130_fd_sc_hd__conb_1 23561.347200 0.23 6277
|
||||
sky130_fd_sc_hd__buf_4 10089.676800 0.10 1344
|
||||
sky130_fd_sc_hd__mux2_8 7567.257600 0.07 288
|
||||
sky130_fd_sc_hd__or2_0 7206.912000 0.07 1152
|
||||
sky130_fd_sc_hd__ebufn_4 5758.022400 0.06 354
|
||||
sky130_fd_sc_hd__buf_12 5525.299200 0.05 276
|
||||
sky130_fd_sc_hd__inv_6 4195.273600 0.04 479
|
||||
sky130_fd_sc_hd__clkbuf_1 3828.672000 0.04 1020
|
||||
sky130_fd_sc_hd__dfxtp_2 3062.937600 0.03 144
|
||||
sky130_fd_sc_hd__bufbuf_8 2477.376000 0.02 132
|
||||
sky130_fd_sc_hd__buf_2 2342.246400 0.02 468
|
||||
sky130_fd_sc_hd__inv_2 2207.116800 0.02 588
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 1366.310400 0.01 156
|
||||
sky130_fd_sc_hd__nand2b_1 825.792000 0.01 132
|
||||
sky130_fd_sc_hd__inv_4 675.648000 0.01 108
|
||||
sky130_fd_sc_hd__buf_16 330.316800 0.00 12
|
||||
sky130_fd_sc_hd__dlygate4sd1_1 324.060800 0.00 37
|
||||
sky130_fd_sc_hd__clkbuf_8 165.158400 0.00 12
|
||||
sky130_fd_sc_hd__or2b_4 135.129600 0.00 12
|
||||
FPGA_BBOX_AREA 5973088.6656
|
||||
CORE_BBOX_AREA 10276128.1216
|
||||
FPGA_BBOX_UTIL 58.1258679818
|
||||
|
Can't render this file because it has a wrong number of fields in line 2.
|
|
|
@ -0,0 +1,75 @@
|
|||
****************************************
|
||||
Report : clock timing
|
||||
-type latency
|
||||
-launch
|
||||
-nworst 1
|
||||
-setup
|
||||
Design : fpga_top
|
||||
Version: P-2019.03-SP4
|
||||
Date : Mon Dec 7 11:48:29 2020
|
||||
****************************************
|
||||
Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
|
||||
|
||||
Mode: full_chip
|
||||
Clock: PROG_CLK
|
||||
|
||||
--- Latency ---
|
||||
Clock Pin Trans Source Offset Network Total Corner
|
||||
---------------------------------------------------------------------------------------------------
|
||||
fpga_core_uut/sb_11__1_/mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_/CLK 4.283 0.000 -- 9.187 9.187 rp-+ nominal
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
Mode: full_chip
|
||||
Clock: CLK
|
||||
|
||||
--- Latency ---
|
||||
Clock Pin Trans Source Offset Network Total Corner
|
||||
---------------------------------------------------------------------------------------------------
|
||||
fpga_core_uut/grid_clb_11__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.625 0.000 -- 6.546 6.546 rp-+ nominal
|
||||
---------------------------------------------------------------------------------------------------
|
||||
****************************************
|
||||
Report : clock timing
|
||||
-type skew
|
||||
-nworst 1
|
||||
-setup
|
||||
Design : fpga_top
|
||||
Version: P-2019.03-SP4
|
||||
Date : Mon Dec 7 11:48:29 2020
|
||||
****************************************
|
||||
Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
|
||||
|
||||
Mode: full_chip
|
||||
Clock: PROG_CLK
|
||||
|
||||
Clock Pin Latency Skew Corner
|
||||
---------------------------------------------------------------------------------------------------
|
||||
fpga_core_uut/sb_10__5_/mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_/CLK 7.995 rp-+ nominal
|
||||
fpga_core_uut/cbx_10__5_/mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_/CLK 5.257 2.737 rp-+ nominal
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
Mode: full_chip
|
||||
Clock: CLK
|
||||
|
||||
Clock Pin Latency Skew Corner
|
||||
---------------------------------------------------------------------------------------------------
|
||||
fpga_core_uut/grid_clb_8__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 5.962 rp-+ nominal
|
||||
fpga_core_uut/grid_clb_8__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 5.241 0.721 rp-+ nominal
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
|
||||
****************************************
|
||||
Report : global timing
|
||||
-format { narrow }
|
||||
Design : fpga_top
|
||||
Version: P-2019.03-SP4
|
||||
Date : Mon Dec 7 11:48:31 2020
|
||||
****************************************
|
||||
|
||||
No setup violations found.
|
||||
|
||||
|
||||
No hold violations found.
|
||||
|
||||
|
||||
1
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
commit c5d9bac1266a187b223f47da8014f66de8936f72
|
||||
Merge: 2eaff52c d11a3d9f
|
||||
Author: Laboratory for Nano Integrated Systems (LNIS) <40280375+LNIS-Projects@users.noreply.github.com>
|
||||
Date: Sun Dec 6 15:44:37 2020 -0700
|
||||
|
||||
Merge pull request #150 from lnis-uofu/dev
|
||||
|
||||
Misc Updates
|
||||
|
||||
commit d11a3d9fef8e8e2805622c2f8dd19f9f03052ca2
|
||||
Author: tangxifan <tangxifan@gmail.com>
|
||||
Date: Sun Dec 6 14:29:16 2020 -0700
|
||||
|
||||
[Tool] Avoid outputting signal initialization codes because they are bulky
|
||||
|
||||
commit cb2bd2e31cfe7c47f69f477b2cf602c41112e8ac
|
||||
Author: tangxifan <tangxifan@gmail.com>
|
||||
Date: Sun Dec 6 14:21:54 2020 -0700
|
||||
|
||||
[Tool] Remove register ports for mini local encoders (1-bit data out)
|
||||
|
||||
commit 2eaff52c1370f95ea86f7cc32077abd362208f88
|
||||
Merge: e1563c93 6bdfcb01
|
||||
Author: Laboratory for Nano Integrated Systems (LNIS) <40280375+LNIS-Projects@users.noreply.github.com>
|
||||
Date: Sat Dec 5 13:44:20 2020 -0700
|
||||
|
||||
Merge pull request #149 from lnis-uofu/dev
|
||||
|
||||
Netlist/Module size Reduction for Routing Multiplexers
|
||||
|
||||
commit 6bdfcb01474b2481229abe6179fd464488ce37e8
|
||||
Author: tangxifan <tangxifan@gmail.com>
|
||||
Date: Sat Dec 5 12:44:09 2020 -0700
|
||||
|
||||
[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
|
||||
On branch master
|
||||
Your branch is up to date with 'origin/master'.
|
||||
|
||||
Changes not staged for commit:
|
||||
(use "git add <file>..." to update what will be committed)
|
||||
(use "git restore <file>..." to discard changes in working directory)
|
||||
modified: openfpga_flow/scripts/run_fpga_flow.py
|
||||
modified: openfpga_flow/scripts/run_fpga_task.py
|
||||
|
||||
Untracked files:
|
||||
(use "git add <file>..." to include in what will be committed)
|
||||
openfpga/openfpga
|
||||
openfpga_flow/tasks/FPGA1212_FC_HD_SKY_task
|
||||
openfpga_flow/tasks/FPGA1212_FLAT_HD_SKY_task
|
||||
openfpga_flow/tasks/FPGA1212_HIER_SKY_SC_MS_task
|
||||
openfpga_flow/tasks/FPGA1212_RESET_HD_SKY_task
|
||||
openfpga_flow/tasks/FPGA1212_SOFA_CHD_task
|
||||
openfpga_flow/tasks/FPGA128128_FLAT_task
|
||||
openfpga_flow/tasks/FPGA1616_FLAT_task
|
||||
openfpga_flow/tasks/FPGA1616_RESET_HD_SKY_task
|
||||
openfpga_flow/tasks/FPGA22_FLAT_SKY_task
|
||||
openfpga_flow/tasks/FPGA22_FLAT_task
|
||||
openfpga_flow/tasks/FPGA22_FRAME_task
|
||||
openfpga_flow/tasks/FPGA22_HIER_SKY_SC_MS_task
|
||||
openfpga_flow/tasks/FPGA22_HIER_SKY_task
|
||||
openfpga_flow/tasks/FPGA22_HIER_task
|
||||
openfpga_flow/tasks/FPGA22_MB_task
|
||||
openfpga_flow/tasks/FPGA22_MODULAR_task
|
||||
openfpga_flow/tasks/FPGA22_RESET_HD_SKY_task
|
||||
openfpga_flow/tasks/FPGA22_SPY_task
|
||||
openfpga_flow/tasks/FPGA3232_FLAT_task
|
||||
openfpga_flow/tasks/FPGA44_FLAT_task
|
||||
openfpga_flow/tasks/FPGA6464_FLAT_task
|
||||
openfpga_flow/tasks/FPGA66_FLAT_task
|
||||
openfpga_flow/tasks/FPGA88_FLAT_HD_SKY_task
|
||||
openfpga_flow/tasks/FPGA88_FLAT_task
|
||||
openfpga_flow/tasks/routing_test/
|
||||
openfpga_flow/tasks/skywater_openfpga_task
|
||||
vpr/vpr
|
||||
|
||||
no changes added to commit (use "git add" and/or "git commit -a")
|
||||
|
|
@ -0,0 +1,182 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[21] -to fpga_top/cbx_1__0_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[21] -to fpga_top/cbx_1__0_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[22] -to fpga_top/cbx_1__0_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[22] -to fpga_top/cbx_1__0_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[23] -to fpga_top/cbx_1__0_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[23] -to fpga_top/cbx_1__0_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[27] -to fpga_top/cbx_1__0_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[27] -to fpga_top/cbx_1__0_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[28] -to fpga_top/cbx_1__0_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[28] -to fpga_top/cbx_1__0_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[29] -to fpga_top/cbx_1__0_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[29] -to fpga_top/cbx_1__0_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[21] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[21] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[27] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[27] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[22] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[22] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[28] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[28] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[23] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[23] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[29] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[29] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,262 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[20] -to fpga_top/cbx_1__12_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[20] -to fpga_top/cbx_1__12_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[22] -to fpga_top/cbx_1__12_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[22] -to fpga_top/cbx_1__12_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[24] -to fpga_top/cbx_1__12_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[24] -to fpga_top/cbx_1__12_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[26] -to fpga_top/cbx_1__12_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[26] -to fpga_top/cbx_1__12_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[28] -to fpga_top/cbx_1__12_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[28] -to fpga_top/cbx_1__12_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[24] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[24] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[26] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[26] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[28] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[28] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[20] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[20] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[22] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[22] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,250 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[21] -to fpga_top/cbx_1__1_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[21] -to fpga_top/cbx_1__1_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[23] -to fpga_top/cbx_1__1_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[23] -to fpga_top/cbx_1__1_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[25] -to fpga_top/cbx_1__1_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[25] -to fpga_top/cbx_1__1_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[27] -to fpga_top/cbx_1__1_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[27] -to fpga_top/cbx_1__1_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[29] -to fpga_top/cbx_1__1_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[29] -to fpga_top/cbx_1__1_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[25] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[25] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[27] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[27] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[29] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[29] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[21] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[21] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[13] -to fpga_top/cby_0__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[13] -to fpga_top/cby_0__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[14] -to fpga_top/cby_0__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[14] -to fpga_top/cby_0__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[15] -to fpga_top/cby_0__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[15] -to fpga_top/cby_0__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[17] -to fpga_top/cby_0__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[17] -to fpga_top/cby_0__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[19] -to fpga_top/cby_0__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[19] -to fpga_top/cby_0__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[20] -to fpga_top/cby_0__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[20] -to fpga_top/cby_0__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[21] -to fpga_top/cby_0__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[21] -to fpga_top/cby_0__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[22] -to fpga_top/cby_0__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[22] -to fpga_top/cby_0__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[23] -to fpga_top/cby_0__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[23] -to fpga_top/cby_0__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[24] -to fpga_top/cby_0__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[24] -to fpga_top/cby_0__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[25] -to fpga_top/cby_0__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[25] -to fpga_top/cby_0__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[26] -to fpga_top/cby_0__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[26] -to fpga_top/cby_0__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[27] -to fpga_top/cby_0__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[27] -to fpga_top/cby_0__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[28] -to fpga_top/cby_0__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[28] -to fpga_top/cby_0__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[29] -to fpga_top/cby_0__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[29] -to fpga_top/cby_0__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[24] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[24] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,262 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[20] -to fpga_top/cby_12__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[20] -to fpga_top/cby_12__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[22] -to fpga_top/cby_12__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[22] -to fpga_top/cby_12__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[24] -to fpga_top/cby_12__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[24] -to fpga_top/cby_12__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[26] -to fpga_top/cby_12__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[26] -to fpga_top/cby_12__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[28] -to fpga_top/cby_12__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[28] -to fpga_top/cby_12__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[24] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[24] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[26] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[26] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[28] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[28] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[20] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[20] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[22] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[22] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,250 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[21] -to fpga_top/cby_1__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[21] -to fpga_top/cby_1__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[23] -to fpga_top/cby_1__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[23] -to fpga_top/cby_1__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[25] -to fpga_top/cby_1__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[25] -to fpga_top/cby_1__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[27] -to fpga_top/cby_1__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[27] -to fpga_top/cby_1__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[29] -to fpga_top/cby_1__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[29] -to fpga_top/cby_1__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[25] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[25] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[27] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[27] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[29] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[29] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[21] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[21] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable configurable memory outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_bottom_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_logic_out_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_lut*_*_in_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_fabric_out_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_ff_*_D_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_left_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
|
|
@ -0,0 +1,253 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable configuration outputs of all the programmable cells for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram_inv
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/mode
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/mode_inv
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/sram
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/sram
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_lut*_*_in_*/sram
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/sram
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_lut*_*_in_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR
|
||||
set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR
|
||||
set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR
|
||||
set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable routing multiplexer outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_lut*_*_in_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/out
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable Switch Block outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Clock contraints for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}]
|
||||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 8.319719358e-10 -waveform {0 4.159859679e-10} [get_ports {clk[0]}]
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_reg_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_reg_in[0] 1.599999994e-10
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_sc_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_sc_in[0] 1.599999994e-10
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_cin[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_cin[0] 1.599999994e-10
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_reg_in[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 4.500000025e-11
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_io__0_/io_inpad[0] 4.243000049e-11
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_io__0_/io_outpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[13] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[14] -to fpga_top/sb_0__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[15] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[16] -to fpga_top/sb_0__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[17] -to fpga_top/sb_0__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[18] -to fpga_top/sb_0__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[19] -to fpga_top/sb_0__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[20] -to fpga_top/sb_0__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[21] -to fpga_top/sb_0__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[22] -to fpga_top/sb_0__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[23] -to fpga_top/sb_0__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[24] -to fpga_top/sb_0__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[25] -to fpga_top/sb_0__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[26] -to fpga_top/sb_0__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[27] -to fpga_top/sb_0__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[28] -to fpga_top/sb_0__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[29] -to fpga_top/sb_0__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[29] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[13] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[14] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[15] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[16] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[17] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[18] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[19] -to fpga_top/sb_0__0_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[20] -to fpga_top/sb_0__0_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[21] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[22] -to fpga_top/sb_0__0_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[23] -to fpga_top/sb_0__0_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[24] -to fpga_top/sb_0__0_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[25] -to fpga_top/sb_0__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[26] -to fpga_top/sb_0__0_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[27] -to fpga_top/sb_0__0_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[28] -to fpga_top/sb_0__0_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[29] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[28] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[27] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[26] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[25] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[24] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[23] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[22] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[21] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[20] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[19] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[18] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[17] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[16] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[15] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[14] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[13] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[12] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[11] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[10] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[9] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[8] -to fpga_top/sb_0__12_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[7] -to fpga_top/sb_0__12_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[6] -to fpga_top/sb_0__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[5] -to fpga_top/sb_0__12_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[4] -to fpga_top/sb_0__12_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[3] -to fpga_top/sb_0__12_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[2] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[1] -to fpga_top/sb_0__12_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[0] -to fpga_top/sb_0__12_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[29] -to fpga_top/sb_0__12_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[28] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[27] -to fpga_top/sb_0__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[26] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[25] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[24] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[23] -to fpga_top/sb_0__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[22] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[21] -to fpga_top/sb_0__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[20] -to fpga_top/sb_0__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[19] -to fpga_top/sb_0__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[18] -to fpga_top/sb_0__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[17] -to fpga_top/sb_0__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[16] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[15] -to fpga_top/sb_0__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[14] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[13] -to fpga_top/sb_0__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[12] -to fpga_top/sb_0__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[11] -to fpga_top/sb_0__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[10] -to fpga_top/sb_0__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[9] -to fpga_top/sb_0__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[8] -to fpga_top/sb_0__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[7] -to fpga_top/sb_0__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[6] -to fpga_top/sb_0__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[5] -to fpga_top/sb_0__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[4] -to fpga_top/sb_0__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[3] -to fpga_top/sb_0__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[2] -to fpga_top/sb_0__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[1] -to fpga_top/sb_0__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[0] -to fpga_top/sb_0__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[29] -to fpga_top/sb_0__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[23] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[24] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[20] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[25] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[22] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[26] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[23] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[27] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[24] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[28] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[26] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[29] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[27] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[28] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[20] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[21] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[22] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[21] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[25] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[29] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[20] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[20] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[22] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[22] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[23] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[23] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[24] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[24] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[26] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[26] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[27] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[27] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[28] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[28] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[29] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[25] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[21] -to fpga_top/sb_0__1_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[20] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[20] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[22] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[29] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[23] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[28] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[24] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[27] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[26] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[26] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[27] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[25] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[28] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[24] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[23] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[22] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[21] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[29] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[28] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[27] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[26] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[25] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[24] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[23] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[22] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[21] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[20] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[19] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[18] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[17] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[16] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[15] -to fpga_top/sb_12__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[14] -to fpga_top/sb_12__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[13] -to fpga_top/sb_12__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[12] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[11] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[10] -to fpga_top/sb_12__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[9] -to fpga_top/sb_12__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[8] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[7] -to fpga_top/sb_12__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[6] -to fpga_top/sb_12__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[5] -to fpga_top/sb_12__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[4] -to fpga_top/sb_12__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[3] -to fpga_top/sb_12__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[2] -to fpga_top/sb_12__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[1] -to fpga_top/sb_12__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[29] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[28] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[27] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[26] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[25] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[24] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[23] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[22] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[21] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[20] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[19] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[18] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[17] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[16] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[15] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[14] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[13] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[12] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[11] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[10] -to fpga_top/sb_12__0_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[9] -to fpga_top/sb_12__0_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[8] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[7] -to fpga_top/sb_12__0_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[6] -to fpga_top/sb_12__0_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[5] -to fpga_top/sb_12__0_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[4] -to fpga_top/sb_12__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[3] -to fpga_top/sb_12__0_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[2] -to fpga_top/sb_12__0_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[1] -to fpga_top/sb_12__0_/chanx_left_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,155 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[1] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[2] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[3] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[4] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[5] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[6] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[7] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[8] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[9] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[10] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[11] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[12] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[13] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[14] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[15] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[16] -to fpga_top/sb_12__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[17] -to fpga_top/sb_12__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[18] -to fpga_top/sb_12__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[19] -to fpga_top/sb_12__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[20] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[21] -to fpga_top/sb_12__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[22] -to fpga_top/sb_12__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[23] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[24] -to fpga_top/sb_12__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[25] -to fpga_top/sb_12__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[26] -to fpga_top/sb_12__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[27] -to fpga_top/sb_12__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[28] -to fpga_top/sb_12__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[29] -to fpga_top/sb_12__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[0] -to fpga_top/sb_12__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[29] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[1] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[2] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[3] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[4] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[5] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[6] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[7] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[8] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[9] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[10] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[11] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[12] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[13] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[14] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[15] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[16] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[17] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[18] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[19] -to fpga_top/sb_12__12_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[20] -to fpga_top/sb_12__12_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[21] -to fpga_top/sb_12__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[22] -to fpga_top/sb_12__12_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[23] -to fpga_top/sb_12__12_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[24] -to fpga_top/sb_12__12_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[25] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[26] -to fpga_top/sb_12__12_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[27] -to fpga_top/sb_12__12_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[28] -to fpga_top/sb_12__12_/chanx_left_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,265 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[22] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[20] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[21] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[22] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[20] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[23] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[24] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[29] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[26] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[28] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[27] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[27] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[28] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[26] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[25] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[24] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[23] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[23] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[20] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[24] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[22] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[25] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[23] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[26] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[24] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[27] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[26] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[28] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[27] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[29] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[28] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[20] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[21] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[22] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[1] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[21] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[25] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[29] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[20] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[20] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[22] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[22] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[23] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[23] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[24] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[24] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[26] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[26] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[27] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[27] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[28] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[28] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[29] -to fpga_top/sb_12__1_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[25] -to fpga_top/sb_12__1_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[21] -to fpga_top/sb_12__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[1] -to fpga_top/sb_12__1_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[21] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[25] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[29] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[20] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[20] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[22] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[22] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[23] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[23] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[24] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[24] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[26] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[26] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[27] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[27] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[28] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[28] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[29] -to fpga_top/sb_1__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[25] -to fpga_top/sb_1__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[21] -to fpga_top/sb_1__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[21] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[22] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[20] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[23] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[22] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[24] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[23] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[25] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[24] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[26] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[26] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[27] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[27] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[28] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[28] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[29] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[20] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[22] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[21] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[20] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[20] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[22] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[23] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[29] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[24] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[28] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[26] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[27] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[27] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[26] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[28] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[25] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[24] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[23] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[20] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[20] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[29] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[22] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[28] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[23] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[27] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[24] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[26] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[26] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[25] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[27] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[24] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[28] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[23] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[22] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[21] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[21] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[25] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[29] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[20] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[20] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[22] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[22] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[23] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[23] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[24] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[24] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[26] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[26] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[27] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[27] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[28] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[29] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[28] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[25] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[21] -to fpga_top/sb_1__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[21] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[20] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[22] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[22] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[23] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[23] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[24] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[24] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[25] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[26] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[26] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[27] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[27] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[28] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[28] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[29] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[20] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,426 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[29] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[25] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[21] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[21] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[25] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[29] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[29] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[25] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[21] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[21] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[25] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[29] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[25] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[21] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[21] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[25] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[29] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[29] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[29] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[29] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[25] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[21] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[21] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[25] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,18 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
`define INITIAL_SIMULATION 1
|
||||
|
||||
`define AUTOCHECKED_SIMULATION 1
|
||||
|
||||
`define ENABLE_FORMAL_VERIFICATION 1
|
||||
|
||||
`define FORMAL_SIMULATION 1
|
||||
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
`include "./SRC/fpga_defines.v"
|
||||
|
||||
//
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/sky130_fd_sc_hd_wrapper.v"
|
||||
//
|
||||
`include "./SRC/sub_module/inv_buf_passgate.v"
|
||||
`include "./SRC/sub_module/arch_encoder.v"
|
||||
`include "./SRC/sub_module/local_encoder.v"
|
||||
`include "./SRC/sub_module/mux_primitives.v"
|
||||
`include "./SRC/sub_module/muxes.v"
|
||||
`include "./SRC/sub_module/luts.v"
|
||||
`include "./SRC/sub_module/wires.v"
|
||||
`include "./SRC/sub_module/memories.v"
|
||||
|
||||
//
|
||||
`include "./SRC/lb/logical_tile_io_mode_physical__iopad.v"
|
||||
`include "./SRC/lb/logical_tile_io_mode_io_.v"
|
||||
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v"
|
||||
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v"
|
||||
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v"
|
||||
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v"
|
||||
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v"
|
||||
`include "./SRC/lb/logical_tile_clb_mode_default__fle.v"
|
||||
`include "./SRC/lb/logical_tile_clb_mode_clb_.v"
|
||||
`include "./SRC/lb/grid_io_top_top.v"
|
||||
`include "./SRC/lb/grid_io_right_right.v"
|
||||
`include "./SRC/lb/grid_io_bottom_bottom.v"
|
||||
`include "./SRC/lb/grid_io_left_left.v"
|
||||
`include "./SRC/lb/grid_clb.v"
|
||||
|
||||
//
|
||||
`include "./SRC/routing/sb_0__0_.v"
|
||||
`include "./SRC/routing/sb_0__1_.v"
|
||||
`include "./SRC/routing/sb_0__12_.v"
|
||||
`include "./SRC/routing/sb_1__0_.v"
|
||||
`include "./SRC/routing/sb_1__1_.v"
|
||||
`include "./SRC/routing/sb_1__12_.v"
|
||||
`include "./SRC/routing/sb_12__0_.v"
|
||||
`include "./SRC/routing/sb_12__1_.v"
|
||||
`include "./SRC/routing/sb_12__12_.v"
|
||||
`include "./SRC/routing/cbx_1__0_.v"
|
||||
`include "./SRC/routing/cbx_1__1_.v"
|
||||
`include "./SRC/routing/cbx_1__12_.v"
|
||||
`include "./SRC/routing/cby_0__1_.v"
|
||||
`include "./SRC/routing/cby_1__1_.v"
|
||||
`include "./SRC/routing/cby_12__1_.v"
|
||||
|
||||
//
|
||||
`include "./SRC/fpga_top.v"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,10 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,272 @@
|
|||
|
||||
|
||||
module grid_clb
|
||||
( pReset, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_1_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_3_, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_5_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_7_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_9_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_11_, top_width_0_height_0__pin_12_, top_width_0_height_0__pin_13_, top_width_0_height_0__pin_14_, top_width_0_height_0__pin_15_, top_width_0_height_0__pin_32_, top_width_0_height_0__pin_33_, top_width_0_height_0__pin_34_, right_width_0_height_0__pin_16_, right_width_0_height_0__pin_17_, right_width_0_height_0__pin_18_, right_width_0_height_0__pin_19_, right_width_0_height_0__pin_20_, right_width_0_height_0__pin_21_, right_width_0_height_0__pin_22_, right_width_0_height_0__pin_23_, right_width_0_height_0__pin_24_, right_width_0_height_0__pin_25_, right_width_0_height_0__pin_26_, right_width_0_height_0__pin_27_, right_width_0_height_0__pin_28_, right_width_0_height_0__pin_29_, right_width_0_height_0__pin_30_, right_width_0_height_0__pin_31_, Reset, ccff_head, top_width_0_height_0__pin_36_upper, top_width_0_height_0__pin_36_lower, top_width_0_height_0__pin_37_upper, top_width_0_height_0__pin_37_lower, top_width_0_height_0__pin_38_upper, top_width_0_height_0__pin_38_lower, top_width_0_height_0__pin_39_upper, top_width_0_height_0__pin_39_lower, top_width_0_height_0__pin_40_upper, top_width_0_height_0__pin_40_lower, top_width_0_height_0__pin_41_upper, top_width_0_height_0__pin_41_lower, top_width_0_height_0__pin_42_upper, top_width_0_height_0__pin_42_lower, top_width_0_height_0__pin_43_upper, top_width_0_height_0__pin_43_lower, right_width_0_height_0__pin_44_upper, right_width_0_height_0__pin_44_lower, right_width_0_height_0__pin_45_upper, right_width_0_height_0__pin_45_lower, right_width_0_height_0__pin_46_upper, right_width_0_height_0__pin_46_lower, right_width_0_height_0__pin_47_upper, right_width_0_height_0__pin_47_lower, right_width_0_height_0__pin_48_upper, right_width_0_height_0__pin_48_lower, right_width_0_height_0__pin_49_upper, right_width_0_height_0__pin_49_lower, right_width_0_height_0__pin_50_upper, right_width_0_height_0__pin_50_lower, right_width_0_height_0__pin_51_upper, right_width_0_height_0__pin_51_lower, bottom_width_0_height_0__pin_52_, bottom_width_0_height_0__pin_53_, bottom_width_0_height_0__pin_54_, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT, Test_en_E_in, Test_en_W_in, Test_en_W_out, Test_en_E_out, pReset_N_in, Reset_E_in, Reset_W_in, Reset_W_out, Reset_E_out, prog_clk_0_N_in, prog_clk_0_S_in, prog_clk_0_S_out, prog_clk_0_E_out, prog_clk_0_W_out, prog_clk_0_N_out, clk_0_N_in, clk_0_S_in );
|
||||
input [0:0] pReset;
|
||||
input [0:0] top_width_0_height_0__pin_0_;
|
||||
input [0:0] top_width_0_height_0__pin_1_;
|
||||
input [0:0] top_width_0_height_0__pin_2_;
|
||||
input [0:0] top_width_0_height_0__pin_3_;
|
||||
input [0:0] top_width_0_height_0__pin_4_;
|
||||
input [0:0] top_width_0_height_0__pin_5_;
|
||||
input [0:0] top_width_0_height_0__pin_6_;
|
||||
input [0:0] top_width_0_height_0__pin_7_;
|
||||
input [0:0] top_width_0_height_0__pin_8_;
|
||||
input [0:0] top_width_0_height_0__pin_9_;
|
||||
input [0:0] top_width_0_height_0__pin_10_;
|
||||
input [0:0] top_width_0_height_0__pin_11_;
|
||||
input [0:0] top_width_0_height_0__pin_12_;
|
||||
input [0:0] top_width_0_height_0__pin_13_;
|
||||
input [0:0] top_width_0_height_0__pin_14_;
|
||||
input [0:0] top_width_0_height_0__pin_15_;
|
||||
input [0:0] top_width_0_height_0__pin_32_;
|
||||
input [0:0] top_width_0_height_0__pin_33_;
|
||||
input [0:0] top_width_0_height_0__pin_34_;
|
||||
input [0:0] right_width_0_height_0__pin_16_;
|
||||
input [0:0] right_width_0_height_0__pin_17_;
|
||||
input [0:0] right_width_0_height_0__pin_18_;
|
||||
input [0:0] right_width_0_height_0__pin_19_;
|
||||
input [0:0] right_width_0_height_0__pin_20_;
|
||||
input [0:0] right_width_0_height_0__pin_21_;
|
||||
input [0:0] right_width_0_height_0__pin_22_;
|
||||
input [0:0] right_width_0_height_0__pin_23_;
|
||||
input [0:0] right_width_0_height_0__pin_24_;
|
||||
input [0:0] right_width_0_height_0__pin_25_;
|
||||
input [0:0] right_width_0_height_0__pin_26_;
|
||||
input [0:0] right_width_0_height_0__pin_27_;
|
||||
input [0:0] right_width_0_height_0__pin_28_;
|
||||
input [0:0] right_width_0_height_0__pin_29_;
|
||||
input [0:0] right_width_0_height_0__pin_30_;
|
||||
input [0:0] right_width_0_height_0__pin_31_;
|
||||
input [0:0] Reset;
|
||||
input [0:0] ccff_head;
|
||||
output [0:0] top_width_0_height_0__pin_36_upper;
|
||||
output [0:0] top_width_0_height_0__pin_36_lower;
|
||||
output [0:0] top_width_0_height_0__pin_37_upper;
|
||||
output [0:0] top_width_0_height_0__pin_37_lower;
|
||||
output [0:0] top_width_0_height_0__pin_38_upper;
|
||||
output [0:0] top_width_0_height_0__pin_38_lower;
|
||||
output [0:0] top_width_0_height_0__pin_39_upper;
|
||||
output [0:0] top_width_0_height_0__pin_39_lower;
|
||||
output [0:0] top_width_0_height_0__pin_40_upper;
|
||||
output [0:0] top_width_0_height_0__pin_40_lower;
|
||||
output [0:0] top_width_0_height_0__pin_41_upper;
|
||||
output [0:0] top_width_0_height_0__pin_41_lower;
|
||||
output [0:0] top_width_0_height_0__pin_42_upper;
|
||||
output [0:0] top_width_0_height_0__pin_42_lower;
|
||||
output [0:0] top_width_0_height_0__pin_43_upper;
|
||||
output [0:0] top_width_0_height_0__pin_43_lower;
|
||||
output [0:0] right_width_0_height_0__pin_44_upper;
|
||||
output [0:0] right_width_0_height_0__pin_44_lower;
|
||||
output [0:0] right_width_0_height_0__pin_45_upper;
|
||||
output [0:0] right_width_0_height_0__pin_45_lower;
|
||||
output [0:0] right_width_0_height_0__pin_46_upper;
|
||||
output [0:0] right_width_0_height_0__pin_46_lower;
|
||||
output [0:0] right_width_0_height_0__pin_47_upper;
|
||||
output [0:0] right_width_0_height_0__pin_47_lower;
|
||||
output [0:0] right_width_0_height_0__pin_48_upper;
|
||||
output [0:0] right_width_0_height_0__pin_48_lower;
|
||||
output [0:0] right_width_0_height_0__pin_49_upper;
|
||||
output [0:0] right_width_0_height_0__pin_49_lower;
|
||||
output [0:0] right_width_0_height_0__pin_50_upper;
|
||||
output [0:0] right_width_0_height_0__pin_50_lower;
|
||||
output [0:0] right_width_0_height_0__pin_51_upper;
|
||||
output [0:0] right_width_0_height_0__pin_51_lower;
|
||||
output [0:0] bottom_width_0_height_0__pin_52_;
|
||||
output [0:0] bottom_width_0_height_0__pin_53_;
|
||||
output [0:0] bottom_width_0_height_0__pin_54_;
|
||||
output [0:0] ccff_tail;
|
||||
input SC_IN_TOP;
|
||||
input SC_IN_BOT;
|
||||
output SC_OUT_TOP;
|
||||
output SC_OUT_BOT;
|
||||
input Test_en_E_in;
|
||||
input Test_en_W_in;
|
||||
output Test_en_W_out;
|
||||
output Test_en_E_out;
|
||||
input pReset_N_in;
|
||||
input Reset_E_in;
|
||||
input Reset_W_in;
|
||||
output Reset_W_out;
|
||||
output Reset_E_out;
|
||||
input prog_clk_0_N_in;
|
||||
input prog_clk_0_S_in;
|
||||
output prog_clk_0_S_out;
|
||||
output prog_clk_0_E_out;
|
||||
output prog_clk_0_W_out;
|
||||
output prog_clk_0_N_out;
|
||||
input clk_0_N_in;
|
||||
input clk_0_S_in;
|
||||
|
||||
wire prog_clk_0;
|
||||
wire clk_0;
|
||||
wire [0:0] Test_en;
|
||||
wire [0:0] clk;
|
||||
wire [0:0] prog_clk;
|
||||
assign top_width_0_height_0__pin_36_lower[0] = top_width_0_height_0__pin_36_upper[0];
|
||||
assign top_width_0_height_0__pin_37_lower[0] = top_width_0_height_0__pin_37_upper[0];
|
||||
assign top_width_0_height_0__pin_38_lower[0] = top_width_0_height_0__pin_38_upper[0];
|
||||
assign top_width_0_height_0__pin_39_lower[0] = top_width_0_height_0__pin_39_upper[0];
|
||||
assign top_width_0_height_0__pin_40_lower[0] = top_width_0_height_0__pin_40_upper[0];
|
||||
assign top_width_0_height_0__pin_41_lower[0] = top_width_0_height_0__pin_41_upper[0];
|
||||
assign top_width_0_height_0__pin_42_lower[0] = top_width_0_height_0__pin_42_upper[0];
|
||||
assign top_width_0_height_0__pin_43_lower[0] = top_width_0_height_0__pin_43_upper[0];
|
||||
assign right_width_0_height_0__pin_44_lower[0] = right_width_0_height_0__pin_44_upper[0];
|
||||
assign right_width_0_height_0__pin_45_lower[0] = right_width_0_height_0__pin_45_upper[0];
|
||||
assign right_width_0_height_0__pin_46_lower[0] = right_width_0_height_0__pin_46_upper[0];
|
||||
assign right_width_0_height_0__pin_47_lower[0] = right_width_0_height_0__pin_47_upper[0];
|
||||
assign right_width_0_height_0__pin_48_lower[0] = right_width_0_height_0__pin_48_upper[0];
|
||||
assign right_width_0_height_0__pin_49_lower[0] = right_width_0_height_0__pin_49_upper[0];
|
||||
assign right_width_0_height_0__pin_50_lower[0] = right_width_0_height_0__pin_50_upper[0];
|
||||
assign right_width_0_height_0__pin_51_lower[0] = right_width_0_height_0__pin_51_upper[0];
|
||||
assign SC_IN_TOP = SC_IN_BOT;
|
||||
assign SC_OUT_TOP = SC_OUT_BOT;
|
||||
assign Test_en_E_in = Test_en_W_in;
|
||||
assign Reset_E_in = Reset_W_in;
|
||||
assign prog_clk_0 = prog_clk;
|
||||
assign prog_clk_0_N_in = prog_clk_0_S_in;
|
||||
assign clk = clk_0;
|
||||
assign clk_0_N_in = clk_0_S_in;
|
||||
|
||||
logical_tile_clb_mode_clb_
|
||||
logical_tile_clb_mode_clb__0
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.Test_en(Test_en[0]),
|
||||
.clb_I0({ top_width_0_height_0__pin_0_[0], top_width_0_height_0__pin_1_[0] }),
|
||||
.clb_I0i({ top_width_0_height_0__pin_2_[0], top_width_0_height_0__pin_3_[0] }),
|
||||
.clb_I1({ top_width_0_height_0__pin_4_[0], top_width_0_height_0__pin_5_[0] }),
|
||||
.clb_I1i({ top_width_0_height_0__pin_6_[0], top_width_0_height_0__pin_7_[0] }),
|
||||
.clb_I2({ top_width_0_height_0__pin_8_[0], top_width_0_height_0__pin_9_[0] }),
|
||||
.clb_I2i({ top_width_0_height_0__pin_10_[0], top_width_0_height_0__pin_11_[0] }),
|
||||
.clb_I3({ top_width_0_height_0__pin_12_[0], top_width_0_height_0__pin_13_[0] }),
|
||||
.clb_I3i({ top_width_0_height_0__pin_14_[0], top_width_0_height_0__pin_15_[0] }),
|
||||
.clb_I4({ right_width_0_height_0__pin_16_[0], right_width_0_height_0__pin_17_[0] }),
|
||||
.clb_I4i({ right_width_0_height_0__pin_18_[0], right_width_0_height_0__pin_19_[0] }),
|
||||
.clb_I5({ right_width_0_height_0__pin_20_[0], right_width_0_height_0__pin_21_[0] }),
|
||||
.clb_I5i({ right_width_0_height_0__pin_22_[0], right_width_0_height_0__pin_23_[0] }),
|
||||
.clb_I6({ right_width_0_height_0__pin_24_[0], right_width_0_height_0__pin_25_[0] }),
|
||||
.clb_I6i({ right_width_0_height_0__pin_26_[0], right_width_0_height_0__pin_27_[0] }),
|
||||
.clb_I7({ right_width_0_height_0__pin_28_[0], right_width_0_height_0__pin_29_[0] }),
|
||||
.clb_I7i({ right_width_0_height_0__pin_30_[0], right_width_0_height_0__pin_31_[0] }),
|
||||
.clb_reg_in(top_width_0_height_0__pin_32_[0]),
|
||||
.clb_sc_in(SC_IN_TOP),
|
||||
.clb_cin(top_width_0_height_0__pin_34_[0]),
|
||||
.clb_reset(Reset[0]),
|
||||
.clb_clk(clk[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.clb_O({ top_width_0_height_0__pin_36_upper[0], top_width_0_height_0__pin_37_upper[0], top_width_0_height_0__pin_38_upper[0], top_width_0_height_0__pin_39_upper[0], top_width_0_height_0__pin_40_upper[0], top_width_0_height_0__pin_41_upper[0], top_width_0_height_0__pin_42_upper[0], top_width_0_height_0__pin_43_upper[0], right_width_0_height_0__pin_44_upper[0], right_width_0_height_0__pin_45_upper[0], right_width_0_height_0__pin_46_upper[0], right_width_0_height_0__pin_47_upper[0], right_width_0_height_0__pin_48_upper[0], right_width_0_height_0__pin_49_upper[0], right_width_0_height_0__pin_50_upper[0], right_width_0_height_0__pin_51_upper[0] }),
|
||||
.clb_reg_out(bottom_width_0_height_0__pin_52_[0]),
|
||||
.clb_sc_out(SC_OUT_BOT),
|
||||
.clb_cout(bottom_width_0_height_0__pin_54_[0]),
|
||||
.ccff_tail(ccff_tail[0])
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
Test_en_FTB00
|
||||
(
|
||||
.A(Test_en_E_in),
|
||||
.X(Test_en)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
Test_en_W_FTB01
|
||||
(
|
||||
.A(Test_en_E_in),
|
||||
.X(Test_en_W_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
Test_en_E_FTB01
|
||||
(
|
||||
.A(Test_en_E_in),
|
||||
.X(Test_en_E_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
pReset_FTB00
|
||||
(
|
||||
.A(pReset_N_in),
|
||||
.X(pReset)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
Reset_FTB00
|
||||
(
|
||||
.A(Reset_E_in),
|
||||
.X(Reset)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
Reset_W_FTB01
|
||||
(
|
||||
.A(Reset_E_in),
|
||||
.X(Reset_W_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
Reset_E_FTB01
|
||||
(
|
||||
.A(Reset_E_in),
|
||||
.X(Reset_E_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
prog_clk_0_FTB00
|
||||
(
|
||||
.A(prog_clk_0_N_in),
|
||||
.X(prog_clk_0)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_0_S_FTB01
|
||||
(
|
||||
.A(prog_clk_0_N_in),
|
||||
.X(prog_clk_0_S_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_0_E_FTB01
|
||||
(
|
||||
.A(prog_clk_0_N_in),
|
||||
.X(prog_clk_0_E_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_0_W_FTB01
|
||||
(
|
||||
.A(prog_clk_0_N_in),
|
||||
.X(prog_clk_0_W_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_0_N_FTB01
|
||||
(
|
||||
.A(prog_clk_0_N_in),
|
||||
.X(prog_clk_0_N_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
clk_0_FTB00
|
||||
(
|
||||
.A(clk_0_N_in),
|
||||
.X(clk_0)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,758 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
//
|
||||
module logical_tile_clb_mode_clb_(pReset,
|
||||
prog_clk,
|
||||
Test_en,
|
||||
clb_I0,
|
||||
clb_I0i,
|
||||
clb_I1,
|
||||
clb_I1i,
|
||||
clb_I2,
|
||||
clb_I2i,
|
||||
clb_I3,
|
||||
clb_I3i,
|
||||
clb_I4,
|
||||
clb_I4i,
|
||||
clb_I5,
|
||||
clb_I5i,
|
||||
clb_I6,
|
||||
clb_I6i,
|
||||
clb_I7,
|
||||
clb_I7i,
|
||||
clb_reg_in,
|
||||
clb_sc_in,
|
||||
clb_cin,
|
||||
clb_reset,
|
||||
clb_clk,
|
||||
ccff_head,
|
||||
clb_O,
|
||||
clb_reg_out,
|
||||
clb_sc_out,
|
||||
clb_cout,
|
||||
ccff_tail);
|
||||
//
|
||||
input [0:0] pReset;
|
||||
//
|
||||
input [0:0] prog_clk;
|
||||
//
|
||||
input [0:0] Test_en;
|
||||
//
|
||||
input [0:1] clb_I0;
|
||||
//
|
||||
input [0:1] clb_I0i;
|
||||
//
|
||||
input [0:1] clb_I1;
|
||||
//
|
||||
input [0:1] clb_I1i;
|
||||
//
|
||||
input [0:1] clb_I2;
|
||||
//
|
||||
input [0:1] clb_I2i;
|
||||
//
|
||||
input [0:1] clb_I3;
|
||||
//
|
||||
input [0:1] clb_I3i;
|
||||
//
|
||||
input [0:1] clb_I4;
|
||||
//
|
||||
input [0:1] clb_I4i;
|
||||
//
|
||||
input [0:1] clb_I5;
|
||||
//
|
||||
input [0:1] clb_I5i;
|
||||
//
|
||||
input [0:1] clb_I6;
|
||||
//
|
||||
input [0:1] clb_I6i;
|
||||
//
|
||||
input [0:1] clb_I7;
|
||||
//
|
||||
input [0:1] clb_I7i;
|
||||
//
|
||||
input [0:0] clb_reg_in;
|
||||
//
|
||||
input [0:0] clb_sc_in;
|
||||
//
|
||||
input [0:0] clb_cin;
|
||||
//
|
||||
input [0:0] clb_reset;
|
||||
//
|
||||
input [0:0] clb_clk;
|
||||
//
|
||||
input [0:0] ccff_head;
|
||||
//
|
||||
output [0:15] clb_O;
|
||||
//
|
||||
output [0:0] clb_reg_out;
|
||||
//
|
||||
output [0:0] clb_sc_out;
|
||||
//
|
||||
output [0:0] clb_cout;
|
||||
//
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//
|
||||
wire [0:1] clb_I0;
|
||||
wire [0:1] clb_I0i;
|
||||
wire [0:1] clb_I1;
|
||||
wire [0:1] clb_I1i;
|
||||
wire [0:1] clb_I2;
|
||||
wire [0:1] clb_I2i;
|
||||
wire [0:1] clb_I3;
|
||||
wire [0:1] clb_I3i;
|
||||
wire [0:1] clb_I4;
|
||||
wire [0:1] clb_I4i;
|
||||
wire [0:1] clb_I5;
|
||||
wire [0:1] clb_I5i;
|
||||
wire [0:1] clb_I6;
|
||||
wire [0:1] clb_I6i;
|
||||
wire [0:1] clb_I7;
|
||||
wire [0:1] clb_I7i;
|
||||
wire [0:0] clb_reg_in;
|
||||
wire [0:0] clb_sc_in;
|
||||
wire [0:0] clb_cin;
|
||||
wire [0:0] clb_reset;
|
||||
wire [0:0] clb_clk;
|
||||
wire [0:15] clb_O;
|
||||
wire [0:0] clb_reg_out;
|
||||
wire [0:0] clb_sc_out;
|
||||
wire [0:0] clb_cout;
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
wire [0:0] direct_interc_19_out;
|
||||
wire [0:0] direct_interc_20_out;
|
||||
wire [0:0] direct_interc_21_out;
|
||||
wire [0:0] direct_interc_22_out;
|
||||
wire [0:0] direct_interc_23_out;
|
||||
wire [0:0] direct_interc_24_out;
|
||||
wire [0:0] direct_interc_25_out;
|
||||
wire [0:0] direct_interc_26_out;
|
||||
wire [0:0] direct_interc_27_out;
|
||||
wire [0:0] direct_interc_28_out;
|
||||
wire [0:0] direct_interc_29_out;
|
||||
wire [0:0] direct_interc_30_out;
|
||||
wire [0:0] direct_interc_31_out;
|
||||
wire [0:0] direct_interc_32_out;
|
||||
wire [0:0] direct_interc_33_out;
|
||||
wire [0:0] direct_interc_34_out;
|
||||
wire [0:0] direct_interc_35_out;
|
||||
wire [0:0] direct_interc_36_out;
|
||||
wire [0:0] direct_interc_37_out;
|
||||
wire [0:0] direct_interc_38_out;
|
||||
wire [0:0] direct_interc_39_out;
|
||||
wire [0:0] direct_interc_40_out;
|
||||
wire [0:0] direct_interc_41_out;
|
||||
wire [0:0] direct_interc_42_out;
|
||||
wire [0:0] direct_interc_43_out;
|
||||
wire [0:0] direct_interc_44_out;
|
||||
wire [0:0] direct_interc_45_out;
|
||||
wire [0:0] direct_interc_46_out;
|
||||
wire [0:0] direct_interc_47_out;
|
||||
wire [0:0] direct_interc_48_out;
|
||||
wire [0:0] direct_interc_49_out;
|
||||
wire [0:0] direct_interc_50_out;
|
||||
wire [0:0] direct_interc_51_out;
|
||||
wire [0:0] direct_interc_52_out;
|
||||
wire [0:0] direct_interc_53_out;
|
||||
wire [0:0] direct_interc_54_out;
|
||||
wire [0:0] direct_interc_55_out;
|
||||
wire [0:0] direct_interc_56_out;
|
||||
wire [0:0] direct_interc_57_out;
|
||||
wire [0:0] direct_interc_58_out;
|
||||
wire [0:0] direct_interc_59_out;
|
||||
wire [0:0] direct_interc_60_out;
|
||||
wire [0:0] direct_interc_61_out;
|
||||
wire [0:0] direct_interc_62_out;
|
||||
wire [0:0] direct_interc_63_out;
|
||||
wire [0:0] direct_interc_64_out;
|
||||
wire [0:0] direct_interc_65_out;
|
||||
wire [0:0] direct_interc_66_out;
|
||||
wire [0:0] direct_interc_67_out;
|
||||
wire [0:0] direct_interc_68_out;
|
||||
wire [0:0] direct_interc_69_out;
|
||||
wire [0:0] direct_interc_70_out;
|
||||
wire [0:0] direct_interc_71_out;
|
||||
wire [0:0] direct_interc_72_out;
|
||||
wire [0:0] direct_interc_73_out;
|
||||
wire [0:0] direct_interc_74_out;
|
||||
wire [0:0] direct_interc_75_out;
|
||||
wire [0:0] direct_interc_76_out;
|
||||
wire [0:0] direct_interc_77_out;
|
||||
wire [0:0] direct_interc_78_out;
|
||||
wire [0:0] direct_interc_79_out;
|
||||
wire [0:0] direct_interc_80_out;
|
||||
wire [0:0] direct_interc_81_out;
|
||||
wire [0:0] direct_interc_82_out;
|
||||
wire [0:0] direct_interc_83_out;
|
||||
wire [0:0] direct_interc_84_out;
|
||||
wire [0:0] direct_interc_85_out;
|
||||
wire [0:0] direct_interc_86_out;
|
||||
wire [0:0] direct_interc_87_out;
|
||||
wire [0:0] direct_interc_88_out;
|
||||
wire [0:0] direct_interc_89_out;
|
||||
wire [0:0] direct_interc_90_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_cout;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_0_fle_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_reg_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_cout;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_1_fle_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_reg_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_cout;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_2_fle_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_reg_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_cout;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_reg_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_cout;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_4_fle_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_reg_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_cout;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_5_fle_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_reg_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_cout;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_6_fle_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_reg_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_7_fle_cout;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_7_fle_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_7_fle_reg_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.Test_en(Test_en[0]),
|
||||
.fle_in({direct_interc_19_out[0], direct_interc_20_out[0], direct_interc_21_out[0], direct_interc_22_out[0]}),
|
||||
.fle_reg_in(direct_interc_23_out[0]),
|
||||
.fle_sc_in(direct_interc_24_out[0]),
|
||||
.fle_cin(direct_interc_25_out[0]),
|
||||
.fle_reset(direct_interc_26_out[0]),
|
||||
.fle_clk(direct_interc_27_out[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_0_fle_out[0:1]),
|
||||
.fle_reg_out(logical_tile_clb_mode_default__fle_0_fle_reg_out[0]),
|
||||
.fle_sc_out(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]),
|
||||
.fle_cout(logical_tile_clb_mode_default__fle_0_fle_cout[0]),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail[0]));
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.Test_en(Test_en[0]),
|
||||
.fle_in({direct_interc_28_out[0], direct_interc_29_out[0], direct_interc_30_out[0], direct_interc_31_out[0]}),
|
||||
.fle_reg_in(direct_interc_32_out[0]),
|
||||
.fle_sc_in(direct_interc_33_out[0]),
|
||||
.fle_cin(direct_interc_34_out[0]),
|
||||
.fle_reset(direct_interc_35_out[0]),
|
||||
.fle_clk(direct_interc_36_out[0]),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail[0]),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_1_fle_out[0:1]),
|
||||
.fle_reg_out(logical_tile_clb_mode_default__fle_1_fle_reg_out[0]),
|
||||
.fle_sc_out(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]),
|
||||
.fle_cout(logical_tile_clb_mode_default__fle_1_fle_cout[0]),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail[0]));
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.Test_en(Test_en[0]),
|
||||
.fle_in({direct_interc_37_out[0], direct_interc_38_out[0], direct_interc_39_out[0], direct_interc_40_out[0]}),
|
||||
.fle_reg_in(direct_interc_41_out[0]),
|
||||
.fle_sc_in(direct_interc_42_out[0]),
|
||||
.fle_cin(direct_interc_43_out[0]),
|
||||
.fle_reset(direct_interc_44_out[0]),
|
||||
.fle_clk(direct_interc_45_out[0]),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail[0]),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_2_fle_out[0:1]),
|
||||
.fle_reg_out(logical_tile_clb_mode_default__fle_2_fle_reg_out[0]),
|
||||
.fle_sc_out(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]),
|
||||
.fle_cout(logical_tile_clb_mode_default__fle_2_fle_cout[0]),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail[0]));
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.Test_en(Test_en[0]),
|
||||
.fle_in({direct_interc_46_out[0], direct_interc_47_out[0], direct_interc_48_out[0], direct_interc_49_out[0]}),
|
||||
.fle_reg_in(direct_interc_50_out[0]),
|
||||
.fle_sc_in(direct_interc_51_out[0]),
|
||||
.fle_cin(direct_interc_52_out[0]),
|
||||
.fle_reset(direct_interc_53_out[0]),
|
||||
.fle_clk(direct_interc_54_out[0]),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail[0]),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_3_fle_out[0:1]),
|
||||
.fle_reg_out(logical_tile_clb_mode_default__fle_3_fle_reg_out[0]),
|
||||
.fle_sc_out(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]),
|
||||
.fle_cout(logical_tile_clb_mode_default__fle_3_fle_cout[0]),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail[0]));
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.Test_en(Test_en[0]),
|
||||
.fle_in({direct_interc_55_out[0], direct_interc_56_out[0], direct_interc_57_out[0], direct_interc_58_out[0]}),
|
||||
.fle_reg_in(direct_interc_59_out[0]),
|
||||
.fle_sc_in(direct_interc_60_out[0]),
|
||||
.fle_cin(direct_interc_61_out[0]),
|
||||
.fle_reset(direct_interc_62_out[0]),
|
||||
.fle_clk(direct_interc_63_out[0]),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail[0]),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_4_fle_out[0:1]),
|
||||
.fle_reg_out(logical_tile_clb_mode_default__fle_4_fle_reg_out[0]),
|
||||
.fle_sc_out(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]),
|
||||
.fle_cout(logical_tile_clb_mode_default__fle_4_fle_cout[0]),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail[0]));
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.Test_en(Test_en[0]),
|
||||
.fle_in({direct_interc_64_out[0], direct_interc_65_out[0], direct_interc_66_out[0], direct_interc_67_out[0]}),
|
||||
.fle_reg_in(direct_interc_68_out[0]),
|
||||
.fle_sc_in(direct_interc_69_out[0]),
|
||||
.fle_cin(direct_interc_70_out[0]),
|
||||
.fle_reset(direct_interc_71_out[0]),
|
||||
.fle_clk(direct_interc_72_out[0]),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail[0]),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_5_fle_out[0:1]),
|
||||
.fle_reg_out(logical_tile_clb_mode_default__fle_5_fle_reg_out[0]),
|
||||
.fle_sc_out(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]),
|
||||
.fle_cout(logical_tile_clb_mode_default__fle_5_fle_cout[0]),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail[0]));
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.Test_en(Test_en[0]),
|
||||
.fle_in({direct_interc_73_out[0], direct_interc_74_out[0], direct_interc_75_out[0], direct_interc_76_out[0]}),
|
||||
.fle_reg_in(direct_interc_77_out[0]),
|
||||
.fle_sc_in(direct_interc_78_out[0]),
|
||||
.fle_cin(direct_interc_79_out[0]),
|
||||
.fle_reset(direct_interc_80_out[0]),
|
||||
.fle_clk(direct_interc_81_out[0]),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail[0]),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_6_fle_out[0:1]),
|
||||
.fle_reg_out(logical_tile_clb_mode_default__fle_6_fle_reg_out[0]),
|
||||
.fle_sc_out(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]),
|
||||
.fle_cout(logical_tile_clb_mode_default__fle_6_fle_cout[0]),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail[0]));
|
||||
|
||||
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.Test_en(Test_en[0]),
|
||||
.fle_in({direct_interc_82_out[0], direct_interc_83_out[0], direct_interc_84_out[0], direct_interc_85_out[0]}),
|
||||
.fle_reg_in(direct_interc_86_out[0]),
|
||||
.fle_sc_in(direct_interc_87_out[0]),
|
||||
.fle_cin(direct_interc_88_out[0]),
|
||||
.fle_reset(direct_interc_89_out[0]),
|
||||
.fle_clk(direct_interc_90_out[0]),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail[0]),
|
||||
.fle_out(logical_tile_clb_mode_default__fle_7_fle_out[0:1]),
|
||||
.fle_reg_out(logical_tile_clb_mode_default__fle_7_fle_reg_out[0]),
|
||||
.fle_sc_out(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]),
|
||||
.fle_cout(logical_tile_clb_mode_default__fle_7_fle_cout[0]),
|
||||
.ccff_tail(ccff_tail[0]));
|
||||
|
||||
direct_interc direct_interc_0_ (
|
||||
.in(logical_tile_clb_mode_default__fle_0_fle_out[1]),
|
||||
.out(clb_O[0]));
|
||||
|
||||
direct_interc direct_interc_1_ (
|
||||
.in(logical_tile_clb_mode_default__fle_0_fle_out[0]),
|
||||
.out(clb_O[1]));
|
||||
|
||||
direct_interc direct_interc_2_ (
|
||||
.in(logical_tile_clb_mode_default__fle_1_fle_out[1]),
|
||||
.out(clb_O[2]));
|
||||
|
||||
direct_interc direct_interc_3_ (
|
||||
.in(logical_tile_clb_mode_default__fle_1_fle_out[0]),
|
||||
.out(clb_O[3]));
|
||||
|
||||
direct_interc direct_interc_4_ (
|
||||
.in(logical_tile_clb_mode_default__fle_2_fle_out[1]),
|
||||
.out(clb_O[4]));
|
||||
|
||||
direct_interc direct_interc_5_ (
|
||||
.in(logical_tile_clb_mode_default__fle_2_fle_out[0]),
|
||||
.out(clb_O[5]));
|
||||
|
||||
direct_interc direct_interc_6_ (
|
||||
.in(logical_tile_clb_mode_default__fle_3_fle_out[1]),
|
||||
.out(clb_O[6]));
|
||||
|
||||
direct_interc direct_interc_7_ (
|
||||
.in(logical_tile_clb_mode_default__fle_3_fle_out[0]),
|
||||
.out(clb_O[7]));
|
||||
|
||||
direct_interc direct_interc_8_ (
|
||||
.in(logical_tile_clb_mode_default__fle_4_fle_out[1]),
|
||||
.out(clb_O[8]));
|
||||
|
||||
direct_interc direct_interc_9_ (
|
||||
.in(logical_tile_clb_mode_default__fle_4_fle_out[0]),
|
||||
.out(clb_O[9]));
|
||||
|
||||
direct_interc direct_interc_10_ (
|
||||
.in(logical_tile_clb_mode_default__fle_5_fle_out[1]),
|
||||
.out(clb_O[10]));
|
||||
|
||||
direct_interc direct_interc_11_ (
|
||||
.in(logical_tile_clb_mode_default__fle_5_fle_out[0]),
|
||||
.out(clb_O[11]));
|
||||
|
||||
direct_interc direct_interc_12_ (
|
||||
.in(logical_tile_clb_mode_default__fle_6_fle_out[1]),
|
||||
.out(clb_O[12]));
|
||||
|
||||
direct_interc direct_interc_13_ (
|
||||
.in(logical_tile_clb_mode_default__fle_6_fle_out[0]),
|
||||
.out(clb_O[13]));
|
||||
|
||||
direct_interc direct_interc_14_ (
|
||||
.in(logical_tile_clb_mode_default__fle_7_fle_out[1]),
|
||||
.out(clb_O[14]));
|
||||
|
||||
direct_interc direct_interc_15_ (
|
||||
.in(logical_tile_clb_mode_default__fle_7_fle_out[0]),
|
||||
.out(clb_O[15]));
|
||||
|
||||
direct_interc direct_interc_16_ (
|
||||
.in(logical_tile_clb_mode_default__fle_7_fle_reg_out[0]),
|
||||
.out(clb_reg_out[0]));
|
||||
|
||||
direct_interc direct_interc_17_ (
|
||||
.in(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]),
|
||||
.out(clb_sc_out[0]));
|
||||
|
||||
direct_interc direct_interc_18_ (
|
||||
.in(logical_tile_clb_mode_default__fle_7_fle_cout[0]),
|
||||
.out(clb_cout[0]));
|
||||
|
||||
direct_interc direct_interc_19_ (
|
||||
.in(clb_I0[0]),
|
||||
.out(direct_interc_19_out[0]));
|
||||
|
||||
direct_interc direct_interc_20_ (
|
||||
.in(clb_I0[1]),
|
||||
.out(direct_interc_20_out[0]));
|
||||
|
||||
direct_interc direct_interc_21_ (
|
||||
.in(clb_I0i[0]),
|
||||
.out(direct_interc_21_out[0]));
|
||||
|
||||
direct_interc direct_interc_22_ (
|
||||
.in(clb_I0i[1]),
|
||||
.out(direct_interc_22_out[0]));
|
||||
|
||||
direct_interc direct_interc_23_ (
|
||||
.in(clb_reg_in[0]),
|
||||
.out(direct_interc_23_out[0]));
|
||||
|
||||
direct_interc direct_interc_24_ (
|
||||
.in(clb_sc_in[0]),
|
||||
.out(direct_interc_24_out[0]));
|
||||
|
||||
direct_interc direct_interc_25_ (
|
||||
.in(clb_cin[0]),
|
||||
.out(direct_interc_25_out[0]));
|
||||
|
||||
direct_interc direct_interc_26_ (
|
||||
.in(clb_reset[0]),
|
||||
.out(direct_interc_26_out[0]));
|
||||
|
||||
direct_interc direct_interc_27_ (
|
||||
.in(clb_clk[0]),
|
||||
.out(direct_interc_27_out[0]));
|
||||
|
||||
direct_interc direct_interc_28_ (
|
||||
.in(clb_I1[0]),
|
||||
.out(direct_interc_28_out[0]));
|
||||
|
||||
direct_interc direct_interc_29_ (
|
||||
.in(clb_I1[1]),
|
||||
.out(direct_interc_29_out[0]));
|
||||
|
||||
direct_interc direct_interc_30_ (
|
||||
.in(clb_I1i[0]),
|
||||
.out(direct_interc_30_out[0]));
|
||||
|
||||
direct_interc direct_interc_31_ (
|
||||
.in(clb_I1i[1]),
|
||||
.out(direct_interc_31_out[0]));
|
||||
|
||||
direct_interc direct_interc_32_ (
|
||||
.in(logical_tile_clb_mode_default__fle_0_fle_reg_out[0]),
|
||||
.out(direct_interc_32_out[0]));
|
||||
|
||||
direct_interc direct_interc_33_ (
|
||||
.in(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]),
|
||||
.out(direct_interc_33_out[0]));
|
||||
|
||||
direct_interc direct_interc_34_ (
|
||||
.in(logical_tile_clb_mode_default__fle_0_fle_cout[0]),
|
||||
.out(direct_interc_34_out[0]));
|
||||
|
||||
direct_interc direct_interc_35_ (
|
||||
.in(clb_reset[0]),
|
||||
.out(direct_interc_35_out[0]));
|
||||
|
||||
direct_interc direct_interc_36_ (
|
||||
.in(clb_clk[0]),
|
||||
.out(direct_interc_36_out[0]));
|
||||
|
||||
direct_interc direct_interc_37_ (
|
||||
.in(clb_I2[0]),
|
||||
.out(direct_interc_37_out[0]));
|
||||
|
||||
direct_interc direct_interc_38_ (
|
||||
.in(clb_I2[1]),
|
||||
.out(direct_interc_38_out[0]));
|
||||
|
||||
direct_interc direct_interc_39_ (
|
||||
.in(clb_I2i[0]),
|
||||
.out(direct_interc_39_out[0]));
|
||||
|
||||
direct_interc direct_interc_40_ (
|
||||
.in(clb_I2i[1]),
|
||||
.out(direct_interc_40_out[0]));
|
||||
|
||||
direct_interc direct_interc_41_ (
|
||||
.in(logical_tile_clb_mode_default__fle_1_fle_reg_out[0]),
|
||||
.out(direct_interc_41_out[0]));
|
||||
|
||||
direct_interc direct_interc_42_ (
|
||||
.in(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]),
|
||||
.out(direct_interc_42_out[0]));
|
||||
|
||||
direct_interc direct_interc_43_ (
|
||||
.in(logical_tile_clb_mode_default__fle_1_fle_cout[0]),
|
||||
.out(direct_interc_43_out[0]));
|
||||
|
||||
direct_interc direct_interc_44_ (
|
||||
.in(clb_reset[0]),
|
||||
.out(direct_interc_44_out[0]));
|
||||
|
||||
direct_interc direct_interc_45_ (
|
||||
.in(clb_clk[0]),
|
||||
.out(direct_interc_45_out[0]));
|
||||
|
||||
direct_interc direct_interc_46_ (
|
||||
.in(clb_I3[0]),
|
||||
.out(direct_interc_46_out[0]));
|
||||
|
||||
direct_interc direct_interc_47_ (
|
||||
.in(clb_I3[1]),
|
||||
.out(direct_interc_47_out[0]));
|
||||
|
||||
direct_interc direct_interc_48_ (
|
||||
.in(clb_I3i[0]),
|
||||
.out(direct_interc_48_out[0]));
|
||||
|
||||
direct_interc direct_interc_49_ (
|
||||
.in(clb_I3i[1]),
|
||||
.out(direct_interc_49_out[0]));
|
||||
|
||||
direct_interc direct_interc_50_ (
|
||||
.in(logical_tile_clb_mode_default__fle_2_fle_reg_out[0]),
|
||||
.out(direct_interc_50_out[0]));
|
||||
|
||||
direct_interc direct_interc_51_ (
|
||||
.in(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]),
|
||||
.out(direct_interc_51_out[0]));
|
||||
|
||||
direct_interc direct_interc_52_ (
|
||||
.in(logical_tile_clb_mode_default__fle_2_fle_cout[0]),
|
||||
.out(direct_interc_52_out[0]));
|
||||
|
||||
direct_interc direct_interc_53_ (
|
||||
.in(clb_reset[0]),
|
||||
.out(direct_interc_53_out[0]));
|
||||
|
||||
direct_interc direct_interc_54_ (
|
||||
.in(clb_clk[0]),
|
||||
.out(direct_interc_54_out[0]));
|
||||
|
||||
direct_interc direct_interc_55_ (
|
||||
.in(clb_I4[0]),
|
||||
.out(direct_interc_55_out[0]));
|
||||
|
||||
direct_interc direct_interc_56_ (
|
||||
.in(clb_I4[1]),
|
||||
.out(direct_interc_56_out[0]));
|
||||
|
||||
direct_interc direct_interc_57_ (
|
||||
.in(clb_I4i[0]),
|
||||
.out(direct_interc_57_out[0]));
|
||||
|
||||
direct_interc direct_interc_58_ (
|
||||
.in(clb_I4i[1]),
|
||||
.out(direct_interc_58_out[0]));
|
||||
|
||||
direct_interc direct_interc_59_ (
|
||||
.in(logical_tile_clb_mode_default__fle_3_fle_reg_out[0]),
|
||||
.out(direct_interc_59_out[0]));
|
||||
|
||||
direct_interc direct_interc_60_ (
|
||||
.in(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]),
|
||||
.out(direct_interc_60_out[0]));
|
||||
|
||||
direct_interc direct_interc_61_ (
|
||||
.in(logical_tile_clb_mode_default__fle_3_fle_cout[0]),
|
||||
.out(direct_interc_61_out[0]));
|
||||
|
||||
direct_interc direct_interc_62_ (
|
||||
.in(clb_reset[0]),
|
||||
.out(direct_interc_62_out[0]));
|
||||
|
||||
direct_interc direct_interc_63_ (
|
||||
.in(clb_clk[0]),
|
||||
.out(direct_interc_63_out[0]));
|
||||
|
||||
direct_interc direct_interc_64_ (
|
||||
.in(clb_I5[0]),
|
||||
.out(direct_interc_64_out[0]));
|
||||
|
||||
direct_interc direct_interc_65_ (
|
||||
.in(clb_I5[1]),
|
||||
.out(direct_interc_65_out[0]));
|
||||
|
||||
direct_interc direct_interc_66_ (
|
||||
.in(clb_I5i[0]),
|
||||
.out(direct_interc_66_out[0]));
|
||||
|
||||
direct_interc direct_interc_67_ (
|
||||
.in(clb_I5i[1]),
|
||||
.out(direct_interc_67_out[0]));
|
||||
|
||||
direct_interc direct_interc_68_ (
|
||||
.in(logical_tile_clb_mode_default__fle_4_fle_reg_out[0]),
|
||||
.out(direct_interc_68_out[0]));
|
||||
|
||||
direct_interc direct_interc_69_ (
|
||||
.in(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]),
|
||||
.out(direct_interc_69_out[0]));
|
||||
|
||||
direct_interc direct_interc_70_ (
|
||||
.in(logical_tile_clb_mode_default__fle_4_fle_cout[0]),
|
||||
.out(direct_interc_70_out[0]));
|
||||
|
||||
direct_interc direct_interc_71_ (
|
||||
.in(clb_reset[0]),
|
||||
.out(direct_interc_71_out[0]));
|
||||
|
||||
direct_interc direct_interc_72_ (
|
||||
.in(clb_clk[0]),
|
||||
.out(direct_interc_72_out[0]));
|
||||
|
||||
direct_interc direct_interc_73_ (
|
||||
.in(clb_I6[0]),
|
||||
.out(direct_interc_73_out[0]));
|
||||
|
||||
direct_interc direct_interc_74_ (
|
||||
.in(clb_I6[1]),
|
||||
.out(direct_interc_74_out[0]));
|
||||
|
||||
direct_interc direct_interc_75_ (
|
||||
.in(clb_I6i[0]),
|
||||
.out(direct_interc_75_out[0]));
|
||||
|
||||
direct_interc direct_interc_76_ (
|
||||
.in(clb_I6i[1]),
|
||||
.out(direct_interc_76_out[0]));
|
||||
|
||||
direct_interc direct_interc_77_ (
|
||||
.in(logical_tile_clb_mode_default__fle_5_fle_reg_out[0]),
|
||||
.out(direct_interc_77_out[0]));
|
||||
|
||||
direct_interc direct_interc_78_ (
|
||||
.in(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]),
|
||||
.out(direct_interc_78_out[0]));
|
||||
|
||||
direct_interc direct_interc_79_ (
|
||||
.in(logical_tile_clb_mode_default__fle_5_fle_cout[0]),
|
||||
.out(direct_interc_79_out[0]));
|
||||
|
||||
direct_interc direct_interc_80_ (
|
||||
.in(clb_reset[0]),
|
||||
.out(direct_interc_80_out[0]));
|
||||
|
||||
direct_interc direct_interc_81_ (
|
||||
.in(clb_clk[0]),
|
||||
.out(direct_interc_81_out[0]));
|
||||
|
||||
direct_interc direct_interc_82_ (
|
||||
.in(clb_I7[0]),
|
||||
.out(direct_interc_82_out[0]));
|
||||
|
||||
direct_interc direct_interc_83_ (
|
||||
.in(clb_I7[1]),
|
||||
.out(direct_interc_83_out[0]));
|
||||
|
||||
direct_interc direct_interc_84_ (
|
||||
.in(clb_I7i[0]),
|
||||
.out(direct_interc_84_out[0]));
|
||||
|
||||
direct_interc direct_interc_85_ (
|
||||
.in(clb_I7i[1]),
|
||||
.out(direct_interc_85_out[0]));
|
||||
|
||||
direct_interc direct_interc_86_ (
|
||||
.in(logical_tile_clb_mode_default__fle_6_fle_reg_out[0]),
|
||||
.out(direct_interc_86_out[0]));
|
||||
|
||||
direct_interc direct_interc_87_ (
|
||||
.in(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]),
|
||||
.out(direct_interc_87_out[0]));
|
||||
|
||||
direct_interc direct_interc_88_ (
|
||||
.in(logical_tile_clb_mode_default__fle_6_fle_cout[0]),
|
||||
.out(direct_interc_88_out[0]));
|
||||
|
||||
direct_interc direct_interc_89_ (
|
||||
.in(clb_reset[0]),
|
||||
.out(direct_interc_89_out[0]));
|
||||
|
||||
direct_interc direct_interc_90_ (
|
||||
.in(clb_clk[0]),
|
||||
.out(direct_interc_90_out[0]));
|
||||
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
//
|
||||
module logical_tile_clb_mode_default__fle(pReset,
|
||||
prog_clk,
|
||||
Test_en,
|
||||
fle_in,
|
||||
fle_reg_in,
|
||||
fle_sc_in,
|
||||
fle_cin,
|
||||
fle_reset,
|
||||
fle_clk,
|
||||
ccff_head,
|
||||
fle_out,
|
||||
fle_reg_out,
|
||||
fle_sc_out,
|
||||
fle_cout,
|
||||
ccff_tail);
|
||||
//
|
||||
input [0:0] pReset;
|
||||
//
|
||||
input [0:0] prog_clk;
|
||||
//
|
||||
input [0:0] Test_en;
|
||||
//
|
||||
input [0:3] fle_in;
|
||||
//
|
||||
input [0:0] fle_reg_in;
|
||||
//
|
||||
input [0:0] fle_sc_in;
|
||||
//
|
||||
input [0:0] fle_cin;
|
||||
//
|
||||
input [0:0] fle_reset;
|
||||
//
|
||||
input [0:0] fle_clk;
|
||||
//
|
||||
input [0:0] ccff_head;
|
||||
//
|
||||
output [0:1] fle_out;
|
||||
//
|
||||
output [0:0] fle_reg_out;
|
||||
//
|
||||
output [0:0] fle_sc_out;
|
||||
//
|
||||
output [0:0] fle_cout;
|
||||
//
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//
|
||||
wire [0:3] fle_in;
|
||||
wire [0:0] fle_reg_in;
|
||||
wire [0:0] fle_sc_in;
|
||||
wire [0:0] fle_cin;
|
||||
wire [0:0] fle_reset;
|
||||
wire [0:0] fle_clk;
|
||||
wire [0:1] fle_out;
|
||||
wire [0:0] fle_reg_out;
|
||||
wire [0:0] fle_sc_out;
|
||||
wire [0:0] fle_cout;
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
wire [0:0] direct_interc_10_out;
|
||||
wire [0:0] direct_interc_11_out;
|
||||
wire [0:0] direct_interc_12_out;
|
||||
wire [0:0] direct_interc_13_out;
|
||||
wire [0:0] direct_interc_5_out;
|
||||
wire [0:0] direct_interc_6_out;
|
||||
wire [0:0] direct_interc_7_out;
|
||||
wire [0:0] direct_interc_8_out;
|
||||
wire [0:0] direct_interc_9_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out;
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.Test_en(Test_en[0]),
|
||||
.fabric_in({direct_interc_5_out[0], direct_interc_6_out[0], direct_interc_7_out[0], direct_interc_8_out[0]}),
|
||||
.fabric_reg_in(direct_interc_9_out[0]),
|
||||
.fabric_sc_in(direct_interc_10_out[0]),
|
||||
.fabric_cin(direct_interc_11_out[0]),
|
||||
.fabric_reset(direct_interc_12_out[0]),
|
||||
.fabric_clk(direct_interc_13_out[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0:1]),
|
||||
.fabric_reg_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out[0]),
|
||||
.fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]),
|
||||
.fabric_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout[0]),
|
||||
.ccff_tail(ccff_tail[0]));
|
||||
|
||||
direct_interc direct_interc_0_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]),
|
||||
.out(fle_out[0]));
|
||||
|
||||
direct_interc direct_interc_1_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]),
|
||||
.out(fle_out[1]));
|
||||
|
||||
direct_interc direct_interc_2_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out[0]),
|
||||
.out(fle_reg_out[0]));
|
||||
|
||||
direct_interc direct_interc_3_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]),
|
||||
.out(fle_sc_out[0]));
|
||||
|
||||
direct_interc direct_interc_4_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout[0]),
|
||||
.out(fle_cout[0]));
|
||||
|
||||
direct_interc direct_interc_5_ (
|
||||
.in(fle_in[0]),
|
||||
.out(direct_interc_5_out[0]));
|
||||
|
||||
direct_interc direct_interc_6_ (
|
||||
.in(fle_in[1]),
|
||||
.out(direct_interc_6_out[0]));
|
||||
|
||||
direct_interc direct_interc_7_ (
|
||||
.in(fle_in[2]),
|
||||
.out(direct_interc_7_out[0]));
|
||||
|
||||
direct_interc direct_interc_8_ (
|
||||
.in(fle_in[3]),
|
||||
.out(direct_interc_8_out[0]));
|
||||
|
||||
direct_interc direct_interc_9_ (
|
||||
.in(fle_reg_in[0]),
|
||||
.out(direct_interc_9_out[0]));
|
||||
|
||||
direct_interc direct_interc_10_ (
|
||||
.in(fle_sc_in[0]),
|
||||
.out(direct_interc_10_out[0]));
|
||||
|
||||
direct_interc direct_interc_11_ (
|
||||
.in(fle_cin[0]),
|
||||
.out(direct_interc_11_out[0]));
|
||||
|
||||
direct_interc direct_interc_12_ (
|
||||
.in(fle_reset[0]),
|
||||
.out(direct_interc_12_out[0]));
|
||||
|
||||
direct_interc direct_interc_13_ (
|
||||
.in(fle_clk[0]),
|
||||
.out(direct_interc_13_out[0]));
|
||||
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
|
|
@ -0,0 +1,242 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
//
|
||||
module logical_tile_clb_mode_default__fle_mode_physical__fabric(pReset,
|
||||
prog_clk,
|
||||
Test_en,
|
||||
fabric_in,
|
||||
fabric_reg_in,
|
||||
fabric_sc_in,
|
||||
fabric_cin,
|
||||
fabric_reset,
|
||||
fabric_clk,
|
||||
ccff_head,
|
||||
fabric_out,
|
||||
fabric_reg_out,
|
||||
fabric_sc_out,
|
||||
fabric_cout,
|
||||
ccff_tail);
|
||||
//
|
||||
input [0:0] pReset;
|
||||
//
|
||||
input [0:0] prog_clk;
|
||||
//
|
||||
input [0:0] Test_en;
|
||||
//
|
||||
input [0:3] fabric_in;
|
||||
//
|
||||
input [0:0] fabric_reg_in;
|
||||
//
|
||||
input [0:0] fabric_sc_in;
|
||||
//
|
||||
input [0:0] fabric_cin;
|
||||
//
|
||||
input [0:0] fabric_reset;
|
||||
//
|
||||
input [0:0] fabric_clk;
|
||||
//
|
||||
input [0:0] ccff_head;
|
||||
//
|
||||
output [0:1] fabric_out;
|
||||
//
|
||||
output [0:0] fabric_reg_out;
|
||||
//
|
||||
output [0:0] fabric_sc_out;
|
||||
//
|
||||
output [0:0] fabric_cout;
|
||||
//
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//
|
||||
wire [0:3] fabric_in;
|
||||
wire [0:0] fabric_reg_in;
|
||||
wire [0:0] fabric_sc_in;
|
||||
wire [0:0] fabric_cin;
|
||||
wire [0:0] fabric_reset;
|
||||
wire [0:0] fabric_clk;
|
||||
wire [0:1] fabric_out;
|
||||
wire [0:0] fabric_reg_out;
|
||||
wire [0:0] fabric_sc_out;
|
||||
wire [0:0] fabric_cout;
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
wire [0:0] direct_interc_10_out;
|
||||
wire [0:0] direct_interc_11_out;
|
||||
wire [0:0] direct_interc_2_out;
|
||||
wire [0:0] direct_interc_3_out;
|
||||
wire [0:0] direct_interc_4_out;
|
||||
wire [0:0] direct_interc_5_out;
|
||||
wire [0:0] direct_interc_6_out;
|
||||
wire [0:0] direct_interc_7_out;
|
||||
wire [0:0] direct_interc_8_out;
|
||||
wire [0:0] direct_interc_9_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cout;
|
||||
wire [0:0] mux_1level_size2_0_out;
|
||||
wire [0:1] mux_1level_size2_0_sram;
|
||||
wire [0:0] mux_1level_size2_1_out;
|
||||
wire [0:1] mux_1level_size2_1_sram;
|
||||
wire [0:0] mux_1level_size2_mem_0_ccff_tail;
|
||||
wire [0:1] mux_1level_tapbuf_size2_0_sram;
|
||||
wire [0:1] mux_1level_tapbuf_size2_1_sram;
|
||||
wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail;
|
||||
wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail;
|
||||
wire [0:1] mux_fabric_out_0_undriven_sram_inv;
|
||||
wire [0:1] mux_fabric_out_1_undriven_sram_inv;
|
||||
wire [0:1] mux_ff_0_D_0_undriven_sram_inv;
|
||||
wire [0:1] mux_ff_1_D_0_undriven_sram_inv;
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.frac_logic_in({direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0], direct_interc_5_out[0]}),
|
||||
.frac_logic_cin(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0:1]),
|
||||
.frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cout[0]),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]));
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
|
||||
.Test_en(Test_en[0]),
|
||||
.ff_D(mux_1level_size2_0_out[0]),
|
||||
.ff_DI(direct_interc_6_out[0]),
|
||||
.ff_reset(direct_interc_7_out[0]),
|
||||
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
|
||||
.ff_clk(direct_interc_8_out[0]));
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
|
||||
.Test_en(Test_en[0]),
|
||||
.ff_D(mux_1level_size2_1_out[0]),
|
||||
.ff_DI(direct_interc_9_out[0]),
|
||||
.ff_reset(direct_interc_10_out[0]),
|
||||
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
|
||||
.ff_clk(direct_interc_11_out[0]));
|
||||
|
||||
mux_1level_tapbuf_size2 mux_fabric_out_0 (
|
||||
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}),
|
||||
.sram(mux_1level_tapbuf_size2_0_sram[0:1]),
|
||||
.sram_inv(mux_fabric_out_0_undriven_sram_inv[0:1]),
|
||||
.out(fabric_out[0]));
|
||||
|
||||
mux_1level_tapbuf_size2 mux_fabric_out_1 (
|
||||
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}),
|
||||
.sram(mux_1level_tapbuf_size2_1_sram[0:1]),
|
||||
.sram_inv(mux_fabric_out_1_undriven_sram_inv[0:1]),
|
||||
.out(fabric_out[1]));
|
||||
|
||||
mux_1level_tapbuf_size2_mem mem_fabric_out_0 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_1level_tapbuf_size2_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_1level_tapbuf_size2_0_sram[0:1]));
|
||||
|
||||
mux_1level_tapbuf_size2_mem mem_fabric_out_1 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_1level_tapbuf_size2_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_1level_tapbuf_size2_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_1level_tapbuf_size2_1_sram[0:1]));
|
||||
|
||||
direct_interc direct_interc_0_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
|
||||
.out(fabric_reg_out[0]));
|
||||
|
||||
direct_interc direct_interc_1_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
|
||||
.out(fabric_sc_out[0]));
|
||||
|
||||
direct_interc direct_interc_2_ (
|
||||
.in(fabric_in[0]),
|
||||
.out(direct_interc_2_out[0]));
|
||||
|
||||
direct_interc direct_interc_3_ (
|
||||
.in(fabric_in[1]),
|
||||
.out(direct_interc_3_out[0]));
|
||||
|
||||
direct_interc direct_interc_4_ (
|
||||
.in(fabric_in[2]),
|
||||
.out(direct_interc_4_out[0]));
|
||||
|
||||
direct_interc direct_interc_5_ (
|
||||
.in(fabric_in[3]),
|
||||
.out(direct_interc_5_out[0]));
|
||||
|
||||
direct_interc direct_interc_6_ (
|
||||
.in(fabric_sc_in[0]),
|
||||
.out(direct_interc_6_out[0]));
|
||||
|
||||
direct_interc direct_interc_7_ (
|
||||
.in(fabric_reset[0]),
|
||||
.out(direct_interc_7_out[0]));
|
||||
|
||||
direct_interc direct_interc_8_ (
|
||||
.in(fabric_clk[0]),
|
||||
.out(direct_interc_8_out[0]));
|
||||
|
||||
direct_interc direct_interc_9_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
|
||||
.out(direct_interc_9_out[0]));
|
||||
|
||||
direct_interc direct_interc_10_ (
|
||||
.in(fabric_reset[0]),
|
||||
.out(direct_interc_10_out[0]));
|
||||
|
||||
direct_interc direct_interc_11_ (
|
||||
.in(fabric_clk[0]),
|
||||
.out(direct_interc_11_out[0]));
|
||||
|
||||
mux_1level_size2 mux_ff_0_D_0 (
|
||||
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_reg_in[0]}),
|
||||
.sram(mux_1level_size2_0_sram[0:1]),
|
||||
.sram_inv(mux_ff_0_D_0_undriven_sram_inv[0:1]),
|
||||
.out(mux_1level_size2_0_out[0]));
|
||||
|
||||
mux_1level_size2 mux_ff_1_D_0 (
|
||||
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]}),
|
||||
.sram(mux_1level_size2_1_sram[0:1]),
|
||||
.sram_inv(mux_ff_1_D_0_undriven_sram_inv[0:1]),
|
||||
.out(mux_1level_size2_1_out[0]));
|
||||
|
||||
mux_1level_size2_mem mem_ff_0_D_0 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_1level_tapbuf_size2_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_1level_size2_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_1level_size2_0_sram[0:1]));
|
||||
|
||||
mux_1level_size2_mem mem_ff_1_D_0 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_1level_size2_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail[0]),
|
||||
.mem_out(mux_1level_size2_1_sram[0:1]));
|
||||
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff(Test_en,
|
||||
ff_D,
|
||||
ff_DI,
|
||||
ff_reset,
|
||||
ff_Q,
|
||||
ff_clk);
|
||||
//
|
||||
input [0:0] Test_en;
|
||||
//
|
||||
input [0:0] ff_D;
|
||||
//
|
||||
input [0:0] ff_DI;
|
||||
//
|
||||
input [0:0] ff_reset;
|
||||
//
|
||||
output [0:0] ff_Q;
|
||||
//
|
||||
input [0:0] ff_clk;
|
||||
|
||||
//
|
||||
wire [0:0] ff_D;
|
||||
wire [0:0] ff_DI;
|
||||
wire [0:0] ff_reset;
|
||||
wire [0:0] ff_Q;
|
||||
wire [0:0] ff_clk;
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ (
|
||||
.SCE(Test_en[0]),
|
||||
.D(ff_D[0]),
|
||||
.SCD(ff_DI[0]),
|
||||
.RESET_B(ff_reset[0]),
|
||||
.CLK(ff_clk[0]),
|
||||
.Q(ff_Q[0]));
|
||||
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
//
|
||||
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic(pReset,
|
||||
prog_clk,
|
||||
frac_logic_in,
|
||||
frac_logic_cin,
|
||||
ccff_head,
|
||||
frac_logic_out,
|
||||
frac_logic_cout,
|
||||
ccff_tail);
|
||||
//
|
||||
input [0:0] pReset;
|
||||
//
|
||||
input [0:0] prog_clk;
|
||||
//
|
||||
input [0:3] frac_logic_in;
|
||||
//
|
||||
input [0:0] frac_logic_cin;
|
||||
//
|
||||
input [0:0] ccff_head;
|
||||
//
|
||||
output [0:1] frac_logic_out;
|
||||
//
|
||||
output [0:0] frac_logic_cout;
|
||||
//
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//
|
||||
wire [0:3] frac_logic_in;
|
||||
wire [0:0] frac_logic_cin;
|
||||
wire [0:1] frac_logic_out;
|
||||
wire [0:0] frac_logic_cout;
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
wire [0:0] direct_interc_2_out;
|
||||
wire [0:0] direct_interc_3_out;
|
||||
wire [0:0] direct_interc_4_out;
|
||||
wire [0:0] direct_interc_5_out;
|
||||
wire [0:0] direct_interc_6_out;
|
||||
wire [0:0] direct_interc_7_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out;
|
||||
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out;
|
||||
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out;
|
||||
wire [0:1] mux_1level_size2_0_sram;
|
||||
wire [0:0] mux_1level_size2_1_out;
|
||||
wire [0:1] mux_1level_size2_1_sram;
|
||||
wire [0:0] mux_1level_size2_mem_0_ccff_tail;
|
||||
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv;
|
||||
wire [0:1] mux_frac_lut4_0_in_2_undriven_sram_inv;
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.frac_lut4_in({direct_interc_2_out[0], direct_interc_3_out[0], mux_1level_size2_1_out[0], direct_interc_4_out[0]}),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.frac_lut4_lut2_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[0:1]),
|
||||
.frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0:1]),
|
||||
.frac_lut4_lut4_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0]),
|
||||
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail[0]));
|
||||
|
||||
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 (
|
||||
.carry_follower_a(direct_interc_5_out[0]),
|
||||
.carry_follower_b(direct_interc_6_out[0]),
|
||||
.carry_follower_cin(direct_interc_7_out[0]),
|
||||
.carry_follower_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout[0]));
|
||||
|
||||
mux_1level_size2 mux_frac_logic_out_0 (
|
||||
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}),
|
||||
.sram(mux_1level_size2_0_sram[0:1]),
|
||||
.sram_inv(mux_frac_logic_out_0_undriven_sram_inv[0:1]),
|
||||
.out(frac_logic_out[0]));
|
||||
|
||||
mux_1level_size2 mux_frac_lut4_0_in_2 (
|
||||
.in({frac_logic_cin[0], frac_logic_in[2]}),
|
||||
.sram(mux_1level_size2_1_sram[0:1]),
|
||||
.sram_inv(mux_frac_lut4_0_in_2_undriven_sram_inv[0:1]),
|
||||
.out(mux_1level_size2_1_out[0]));
|
||||
|
||||
mux_1level_size2_mem mem_frac_logic_out_0 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_1level_size2_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_1level_size2_0_sram[0:1]));
|
||||
|
||||
mux_1level_size2_mem mem_frac_lut4_0_in_2 (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_1level_size2_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail[0]),
|
||||
.mem_out(mux_1level_size2_1_sram[0:1]));
|
||||
|
||||
direct_interc direct_interc_0_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]),
|
||||
.out(frac_logic_out[1]));
|
||||
|
||||
direct_interc direct_interc_1_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0_carry_follower_cout[0]),
|
||||
.out(frac_logic_cout[0]));
|
||||
|
||||
direct_interc direct_interc_2_ (
|
||||
.in(frac_logic_in[0]),
|
||||
.out(direct_interc_2_out[0]));
|
||||
|
||||
direct_interc direct_interc_3_ (
|
||||
.in(frac_logic_in[1]),
|
||||
.out(direct_interc_3_out[0]));
|
||||
|
||||
direct_interc direct_interc_4_ (
|
||||
.in(frac_logic_in[3]),
|
||||
.out(direct_interc_4_out[0]));
|
||||
|
||||
direct_interc direct_interc_5_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[1]),
|
||||
.out(direct_interc_5_out[0]));
|
||||
|
||||
direct_interc direct_interc_6_ (
|
||||
.in(frac_logic_cin[0]),
|
||||
.out(direct_interc_6_out[0]));
|
||||
|
||||
direct_interc direct_interc_7_ (
|
||||
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut2_out[0]),
|
||||
.out(direct_interc_7_out[0]));
|
||||
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower(carry_follower_a,
|
||||
carry_follower_b,
|
||||
carry_follower_cin,
|
||||
carry_follower_cout);
|
||||
//
|
||||
input [0:0] carry_follower_a;
|
||||
//
|
||||
input [0:0] carry_follower_b;
|
||||
//
|
||||
input [0:0] carry_follower_cin;
|
||||
//
|
||||
output [0:0] carry_follower_cout;
|
||||
|
||||
//
|
||||
wire [0:0] carry_follower_a;
|
||||
wire [0:0] carry_follower_b;
|
||||
wire [0:0] carry_follower_cin;
|
||||
wire [0:0] carry_follower_cout;
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ (
|
||||
.A0(carry_follower_a[0]),
|
||||
.A1(carry_follower_b[0]),
|
||||
.S(carry_follower_cin[0]),
|
||||
.X(carry_follower_cout[0]));
|
||||
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4(pReset,
|
||||
prog_clk,
|
||||
frac_lut4_in,
|
||||
ccff_head,
|
||||
frac_lut4_lut2_out,
|
||||
frac_lut4_lut3_out,
|
||||
frac_lut4_lut4_out,
|
||||
ccff_tail);
|
||||
//
|
||||
input [0:0] pReset;
|
||||
//
|
||||
input [0:0] prog_clk;
|
||||
//
|
||||
input [0:3] frac_lut4_in;
|
||||
//
|
||||
input [0:0] ccff_head;
|
||||
//
|
||||
output [0:1] frac_lut4_lut2_out;
|
||||
//
|
||||
output [0:1] frac_lut4_lut3_out;
|
||||
//
|
||||
output [0:0] frac_lut4_lut4_out;
|
||||
//
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//
|
||||
wire [0:3] frac_lut4_in;
|
||||
wire [0:1] frac_lut4_lut2_out;
|
||||
wire [0:1] frac_lut4_lut3_out;
|
||||
wire [0:0] frac_lut4_lut4_out;
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
wire [0:0] frac_lut4_0__undriven_mode_inv;
|
||||
wire [0:15] frac_lut4_0__undriven_sram_inv;
|
||||
wire [0:0] frac_lut4_0_mode;
|
||||
wire [0:15] frac_lut4_0_sram;
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
frac_lut4 frac_lut4_0_ (
|
||||
.in(frac_lut4_in[0:3]),
|
||||
.sram(frac_lut4_0_sram[0:15]),
|
||||
.sram_inv(frac_lut4_0__undriven_sram_inv[0:15]),
|
||||
.mode(frac_lut4_0_mode[0]),
|
||||
.mode_inv(frac_lut4_0__undriven_mode_inv[0]),
|
||||
.lut2_out(frac_lut4_lut2_out[0:1]),
|
||||
.lut3_out(frac_lut4_lut3_out[0:1]),
|
||||
.lut4_out(frac_lut4_lut4_out[0]));
|
||||
|
||||
frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(ccff_tail[0]),
|
||||
.mem_out({frac_lut4_0_sram[0:15], frac_lut4_0_mode[0]}));
|
||||
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
//
|
||||
module logical_tile_io_mode_io_(IO_ISOL_N,
|
||||
pReset,
|
||||
prog_clk,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
|
||||
io_outpad,
|
||||
ccff_head,
|
||||
io_inpad,
|
||||
ccff_tail);
|
||||
//
|
||||
input [0:0] IO_ISOL_N;
|
||||
//
|
||||
input [0:0] pReset;
|
||||
//
|
||||
input [0:0] prog_clk;
|
||||
//
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
|
||||
//
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
|
||||
//
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
|
||||
//
|
||||
input [0:0] io_outpad;
|
||||
//
|
||||
input [0:0] ccff_head;
|
||||
//
|
||||
output [0:0] io_inpad;
|
||||
//
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//
|
||||
wire [0:0] io_outpad;
|
||||
wire [0:0] io_inpad;
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
wire [0:0] direct_interc_1_out;
|
||||
wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad;
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
|
||||
.IO_ISOL_N(IO_ISOL_N[0]),
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
|
||||
.iopad_outpad(direct_interc_1_out[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]),
|
||||
.ccff_tail(ccff_tail[0]));
|
||||
|
||||
direct_interc direct_interc_0_ (
|
||||
.in(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]),
|
||||
.out(io_inpad[0]));
|
||||
|
||||
direct_interc direct_interc_1_ (
|
||||
.in(io_outpad[0]),
|
||||
.out(direct_interc_1_out[0]));
|
||||
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
module logical_tile_io_mode_physical__iopad(IO_ISOL_N,
|
||||
pReset,
|
||||
prog_clk,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
|
||||
iopad_outpad,
|
||||
ccff_head,
|
||||
iopad_inpad,
|
||||
ccff_tail);
|
||||
//
|
||||
input [0:0] IO_ISOL_N;
|
||||
//
|
||||
input [0:0] pReset;
|
||||
//
|
||||
input [0:0] prog_clk;
|
||||
//
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
|
||||
//
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
|
||||
//
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
|
||||
//
|
||||
input [0:0] iopad_outpad;
|
||||
//
|
||||
input [0:0] ccff_head;
|
||||
//
|
||||
output [0:0] iopad_inpad;
|
||||
//
|
||||
output [0:0] ccff_tail;
|
||||
|
||||
//
|
||||
wire [0:0] iopad_outpad;
|
||||
wire [0:0] iopad_inpad;
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
wire [0:0] EMBEDDED_IO_HD_0_en;
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
|
||||
.IO_ISOL_N(IO_ISOL_N[0]),
|
||||
.SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
|
||||
.SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
|
||||
.SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
|
||||
.FPGA_OUT(iopad_outpad[0]),
|
||||
.FPGA_DIR(EMBEDDED_IO_HD_0_en[0]),
|
||||
.FPGA_IN(iopad_inpad[0]));
|
||||
|
||||
EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(ccff_tail[0]),
|
||||
.mem_out(EMBEDDED_IO_HD_0_en[0]));
|
||||
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,548 @@
|
|||
|
||||
|
||||
module cbx_1__0_
|
||||
( pReset, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_2_, bottom_grid_pin_4_, bottom_grid_pin_6_, bottom_grid_pin_8_, bottom_grid_pin_10_, bottom_grid_pin_12_, bottom_grid_pin_14_, bottom_grid_pin_16_, ccff_tail, IO_ISOL_N, gfpga_pad_EMBEDDED_IO_HD_SOC_IN, gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_12_, top_width_0_height_0__pin_14_, top_width_0_height_0__pin_16_, top_width_0_height_0__pin_1_upper, top_width_0_height_0__pin_1_lower, top_width_0_height_0__pin_3_upper, top_width_0_height_0__pin_3_lower, top_width_0_height_0__pin_5_upper, top_width_0_height_0__pin_5_lower, top_width_0_height_0__pin_7_upper, top_width_0_height_0__pin_7_lower, top_width_0_height_0__pin_9_upper, top_width_0_height_0__pin_9_lower, top_width_0_height_0__pin_11_upper, top_width_0_height_0__pin_11_lower, top_width_0_height_0__pin_13_upper, top_width_0_height_0__pin_13_lower, top_width_0_height_0__pin_15_upper, top_width_0_height_0__pin_15_lower, top_width_0_height_0__pin_17_upper, top_width_0_height_0__pin_17_lower, SC_IN_TOP, SC_OUT_BOT, SC_IN_BOT, SC_OUT_TOP, pReset_E_in, pReset_W_in, pReset_W_out, pReset_E_out, prog_clk_0_N_in, prog_clk_0_W_out );
|
||||
input [0:0] pReset;
|
||||
input [0:29] chanx_left_in;
|
||||
input [0:29] chanx_right_in;
|
||||
input [0:0] ccff_head;
|
||||
output [0:29] chanx_left_out;
|
||||
output [0:29] chanx_right_out;
|
||||
output [0:0] bottom_grid_pin_0_;
|
||||
output [0:0] bottom_grid_pin_2_;
|
||||
output [0:0] bottom_grid_pin_4_;
|
||||
output [0:0] bottom_grid_pin_6_;
|
||||
output [0:0] bottom_grid_pin_8_;
|
||||
output [0:0] bottom_grid_pin_10_;
|
||||
output [0:0] bottom_grid_pin_12_;
|
||||
output [0:0] bottom_grid_pin_14_;
|
||||
output [0:0] bottom_grid_pin_16_;
|
||||
output [0:0] ccff_tail;
|
||||
input [0:0] IO_ISOL_N;
|
||||
input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
|
||||
output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
|
||||
output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
|
||||
input [0:0] top_width_0_height_0__pin_0_;
|
||||
input [0:0] top_width_0_height_0__pin_2_;
|
||||
input [0:0] top_width_0_height_0__pin_4_;
|
||||
input [0:0] top_width_0_height_0__pin_6_;
|
||||
input [0:0] top_width_0_height_0__pin_8_;
|
||||
input [0:0] top_width_0_height_0__pin_10_;
|
||||
input [0:0] top_width_0_height_0__pin_12_;
|
||||
input [0:0] top_width_0_height_0__pin_14_;
|
||||
input [0:0] top_width_0_height_0__pin_16_;
|
||||
output [0:0] top_width_0_height_0__pin_1_upper;
|
||||
output [0:0] top_width_0_height_0__pin_1_lower;
|
||||
output [0:0] top_width_0_height_0__pin_3_upper;
|
||||
output [0:0] top_width_0_height_0__pin_3_lower;
|
||||
output [0:0] top_width_0_height_0__pin_5_upper;
|
||||
output [0:0] top_width_0_height_0__pin_5_lower;
|
||||
output [0:0] top_width_0_height_0__pin_7_upper;
|
||||
output [0:0] top_width_0_height_0__pin_7_lower;
|
||||
output [0:0] top_width_0_height_0__pin_9_upper;
|
||||
output [0:0] top_width_0_height_0__pin_9_lower;
|
||||
output [0:0] top_width_0_height_0__pin_11_upper;
|
||||
output [0:0] top_width_0_height_0__pin_11_lower;
|
||||
output [0:0] top_width_0_height_0__pin_13_upper;
|
||||
output [0:0] top_width_0_height_0__pin_13_lower;
|
||||
output [0:0] top_width_0_height_0__pin_15_upper;
|
||||
output [0:0] top_width_0_height_0__pin_15_lower;
|
||||
output [0:0] top_width_0_height_0__pin_17_upper;
|
||||
output [0:0] top_width_0_height_0__pin_17_lower;
|
||||
input SC_IN_TOP;
|
||||
output SC_OUT_BOT;
|
||||
input SC_IN_BOT;
|
||||
output SC_OUT_TOP;
|
||||
input pReset_E_in;
|
||||
input pReset_W_in;
|
||||
output pReset_W_out;
|
||||
output pReset_E_out;
|
||||
input prog_clk_0_N_in;
|
||||
output prog_clk_0_W_out;
|
||||
|
||||
wire [0:3] mux_2level_size12_0_sram;
|
||||
wire [0:3] mux_2level_size12_1_sram;
|
||||
wire [0:3] mux_2level_size12_2_sram;
|
||||
wire [0:3] mux_2level_size12_3_sram;
|
||||
wire [0:3] mux_2level_size12_4_sram;
|
||||
wire [0:3] mux_2level_size12_5_sram;
|
||||
wire [0:3] mux_2level_size12_6_sram;
|
||||
wire [0:3] mux_2level_size12_7_sram;
|
||||
wire [0:3] mux_2level_size12_8_sram;
|
||||
wire [0:0] mux_2level_size12_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_2_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_3_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_4_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_5_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_6_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_7_ccff_tail;
|
||||
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_7_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
|
||||
wire ccff_tail_mid;
|
||||
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
|
||||
wire [0:0] logical_tile_io_mode_io__7_ccff_tail;
|
||||
wire prog_clk_0;
|
||||
wire [0:0] prog_clk;
|
||||
assign chanx_right_out[0] = chanx_left_in[0];
|
||||
assign chanx_right_out[1] = chanx_left_in[1];
|
||||
assign chanx_right_out[2] = chanx_left_in[2];
|
||||
assign chanx_right_out[3] = chanx_left_in[3];
|
||||
assign chanx_right_out[4] = chanx_left_in[4];
|
||||
assign chanx_right_out[5] = chanx_left_in[5];
|
||||
assign chanx_right_out[6] = chanx_left_in[6];
|
||||
assign chanx_right_out[7] = chanx_left_in[7];
|
||||
assign chanx_right_out[8] = chanx_left_in[8];
|
||||
assign chanx_right_out[9] = chanx_left_in[9];
|
||||
assign chanx_right_out[10] = chanx_left_in[10];
|
||||
assign chanx_right_out[11] = chanx_left_in[11];
|
||||
assign chanx_right_out[12] = chanx_left_in[12];
|
||||
assign chanx_right_out[13] = chanx_left_in[13];
|
||||
assign chanx_right_out[14] = chanx_left_in[14];
|
||||
assign chanx_right_out[15] = chanx_left_in[15];
|
||||
assign chanx_right_out[16] = chanx_left_in[16];
|
||||
assign chanx_right_out[17] = chanx_left_in[17];
|
||||
assign chanx_right_out[18] = chanx_left_in[18];
|
||||
assign chanx_right_out[19] = chanx_left_in[19];
|
||||
assign chanx_right_out[20] = chanx_left_in[20];
|
||||
assign chanx_right_out[21] = chanx_left_in[21];
|
||||
assign chanx_right_out[22] = chanx_left_in[22];
|
||||
assign chanx_right_out[23] = chanx_left_in[23];
|
||||
assign chanx_right_out[24] = chanx_left_in[24];
|
||||
assign chanx_right_out[25] = chanx_left_in[25];
|
||||
assign chanx_right_out[26] = chanx_left_in[26];
|
||||
assign chanx_right_out[27] = chanx_left_in[27];
|
||||
assign chanx_right_out[28] = chanx_left_in[28];
|
||||
assign chanx_right_out[29] = chanx_left_in[29];
|
||||
assign chanx_left_out[0] = chanx_right_in[0];
|
||||
assign chanx_left_out[1] = chanx_right_in[1];
|
||||
assign chanx_left_out[2] = chanx_right_in[2];
|
||||
assign chanx_left_out[3] = chanx_right_in[3];
|
||||
assign chanx_left_out[4] = chanx_right_in[4];
|
||||
assign chanx_left_out[5] = chanx_right_in[5];
|
||||
assign chanx_left_out[6] = chanx_right_in[6];
|
||||
assign chanx_left_out[7] = chanx_right_in[7];
|
||||
assign chanx_left_out[8] = chanx_right_in[8];
|
||||
assign chanx_left_out[9] = chanx_right_in[9];
|
||||
assign chanx_left_out[10] = chanx_right_in[10];
|
||||
assign chanx_left_out[11] = chanx_right_in[11];
|
||||
assign chanx_left_out[12] = chanx_right_in[12];
|
||||
assign chanx_left_out[13] = chanx_right_in[13];
|
||||
assign chanx_left_out[14] = chanx_right_in[14];
|
||||
assign chanx_left_out[15] = chanx_right_in[15];
|
||||
assign chanx_left_out[16] = chanx_right_in[16];
|
||||
assign chanx_left_out[17] = chanx_right_in[17];
|
||||
assign chanx_left_out[18] = chanx_right_in[18];
|
||||
assign chanx_left_out[19] = chanx_right_in[19];
|
||||
assign chanx_left_out[20] = chanx_right_in[20];
|
||||
assign chanx_left_out[21] = chanx_right_in[21];
|
||||
assign chanx_left_out[22] = chanx_right_in[22];
|
||||
assign chanx_left_out[23] = chanx_right_in[23];
|
||||
assign chanx_left_out[24] = chanx_right_in[24];
|
||||
assign chanx_left_out[25] = chanx_right_in[25];
|
||||
assign chanx_left_out[26] = chanx_right_in[26];
|
||||
assign chanx_left_out[27] = chanx_right_in[27];
|
||||
assign chanx_left_out[28] = chanx_right_in[28];
|
||||
assign chanx_left_out[29] = chanx_right_in[29];
|
||||
assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0];
|
||||
assign top_width_0_height_0__pin_3_lower[0] = top_width_0_height_0__pin_3_upper[0];
|
||||
assign top_width_0_height_0__pin_5_lower[0] = top_width_0_height_0__pin_5_upper[0];
|
||||
assign top_width_0_height_0__pin_7_lower[0] = top_width_0_height_0__pin_7_upper[0];
|
||||
assign top_width_0_height_0__pin_9_lower[0] = top_width_0_height_0__pin_9_upper[0];
|
||||
assign top_width_0_height_0__pin_11_lower[0] = top_width_0_height_0__pin_11_upper[0];
|
||||
assign top_width_0_height_0__pin_13_lower[0] = top_width_0_height_0__pin_13_upper[0];
|
||||
assign top_width_0_height_0__pin_15_lower[0] = top_width_0_height_0__pin_15_upper[0];
|
||||
assign top_width_0_height_0__pin_17_lower[0] = top_width_0_height_0__pin_17_upper[0];
|
||||
assign SC_OUT_BOT = SC_IN_TOP;
|
||||
assign SC_OUT_TOP = SC_IN_BOT;
|
||||
assign pReset_E_in = pReset_W_in;
|
||||
assign prog_clk_0 = prog_clk;
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_0
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24] }),
|
||||
.sram(mux_2level_size12_0_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_0_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_1
|
||||
(
|
||||
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25] }),
|
||||
.sram(mux_2level_size12_1_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_2_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_2
|
||||
(
|
||||
.in({ chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26] }),
|
||||
.sram(mux_2level_size12_2_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_4_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_3
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27] }),
|
||||
.sram(mux_2level_size12_3_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_6_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_4
|
||||
(
|
||||
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28] }),
|
||||
.sram(mux_2level_size12_4_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_8_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_5
|
||||
(
|
||||
.in({ chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[23], chanx_right_in[23], chanx_left_in[29], chanx_right_in[29] }),
|
||||
.sram(mux_2level_size12_5_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_10_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_6
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24] }),
|
||||
.sram(mux_2level_size12_6_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_12_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_7
|
||||
(
|
||||
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25] }),
|
||||
.sram(mux_2level_size12_7_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_14_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_8
|
||||
(
|
||||
.in({ chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26] }),
|
||||
.sram(mux_2level_size12_8_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_16_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_0
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_0_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_1
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_1_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_2
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_2_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_3
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_3_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_4
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_4_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_5
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_5_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_6
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_6_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_7
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_7_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_7_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_8
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_7_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.mem_out(mux_2level_size12_8_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
logical_tile_io_mode_io_
|
||||
logical_tile_io_mode_io__0
|
||||
(
|
||||
.IO_ISOL_N(IO_ISOL_N[0]),
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
|
||||
.io_outpad(top_width_0_height_0__pin_0_[0]),
|
||||
.ccff_head(ccff_tail_mid),
|
||||
.io_inpad(top_width_0_height_0__pin_1_upper[0]),
|
||||
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail[0])
|
||||
);
|
||||
|
||||
|
||||
logical_tile_io_mode_io_
|
||||
logical_tile_io_mode_io__1
|
||||
(
|
||||
.IO_ISOL_N(IO_ISOL_N[0]),
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
|
||||
.io_outpad(top_width_0_height_0__pin_2_[0]),
|
||||
.ccff_head(logical_tile_io_mode_io__0_ccff_tail[0]),
|
||||
.io_inpad(top_width_0_height_0__pin_3_upper[0]),
|
||||
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0])
|
||||
);
|
||||
|
||||
|
||||
logical_tile_io_mode_io_
|
||||
logical_tile_io_mode_io__2
|
||||
(
|
||||
.IO_ISOL_N(IO_ISOL_N[0]),
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
|
||||
.io_outpad(top_width_0_height_0__pin_4_[0]),
|
||||
.ccff_head(logical_tile_io_mode_io__1_ccff_tail[0]),
|
||||
.io_inpad(top_width_0_height_0__pin_5_upper[0]),
|
||||
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0])
|
||||
);
|
||||
|
||||
|
||||
logical_tile_io_mode_io_
|
||||
logical_tile_io_mode_io__3
|
||||
(
|
||||
.IO_ISOL_N(IO_ISOL_N[0]),
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
|
||||
.io_outpad(top_width_0_height_0__pin_6_[0]),
|
||||
.ccff_head(logical_tile_io_mode_io__2_ccff_tail[0]),
|
||||
.io_inpad(top_width_0_height_0__pin_7_upper[0]),
|
||||
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0])
|
||||
);
|
||||
|
||||
|
||||
logical_tile_io_mode_io_
|
||||
logical_tile_io_mode_io__4
|
||||
(
|
||||
.IO_ISOL_N(IO_ISOL_N[0]),
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4]),
|
||||
.io_outpad(top_width_0_height_0__pin_8_[0]),
|
||||
.ccff_head(logical_tile_io_mode_io__3_ccff_tail[0]),
|
||||
.io_inpad(top_width_0_height_0__pin_9_upper[0]),
|
||||
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0])
|
||||
);
|
||||
|
||||
|
||||
logical_tile_io_mode_io_
|
||||
logical_tile_io_mode_io__5
|
||||
(
|
||||
.IO_ISOL_N(IO_ISOL_N[0]),
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5]),
|
||||
.io_outpad(top_width_0_height_0__pin_10_[0]),
|
||||
.ccff_head(logical_tile_io_mode_io__4_ccff_tail[0]),
|
||||
.io_inpad(top_width_0_height_0__pin_11_upper[0]),
|
||||
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail[0])
|
||||
);
|
||||
|
||||
|
||||
logical_tile_io_mode_io_
|
||||
logical_tile_io_mode_io__6
|
||||
(
|
||||
.IO_ISOL_N(IO_ISOL_N[0]),
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6]),
|
||||
.io_outpad(top_width_0_height_0__pin_12_[0]),
|
||||
.ccff_head(logical_tile_io_mode_io__5_ccff_tail[0]),
|
||||
.io_inpad(top_width_0_height_0__pin_13_upper[0]),
|
||||
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail[0])
|
||||
);
|
||||
|
||||
|
||||
logical_tile_io_mode_io_
|
||||
logical_tile_io_mode_io__7
|
||||
(
|
||||
.IO_ISOL_N(IO_ISOL_N[0]),
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7]),
|
||||
.io_outpad(top_width_0_height_0__pin_14_[0]),
|
||||
.ccff_head(logical_tile_io_mode_io__6_ccff_tail[0]),
|
||||
.io_inpad(top_width_0_height_0__pin_15_upper[0]),
|
||||
.ccff_tail(logical_tile_io_mode_io__7_ccff_tail[0])
|
||||
);
|
||||
|
||||
|
||||
logical_tile_io_mode_io_
|
||||
logical_tile_io_mode_io__8
|
||||
(
|
||||
.IO_ISOL_N(IO_ISOL_N[0]),
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8]),
|
||||
.io_outpad(top_width_0_height_0__pin_16_[0]),
|
||||
.ccff_head(logical_tile_io_mode_io__7_ccff_tail[0]),
|
||||
.io_inpad(top_width_0_height_0__pin_17_upper[0]),
|
||||
.ccff_tail(ccff_tail[0])
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
pReset_FTB00
|
||||
(
|
||||
.A(pReset_E_in),
|
||||
.X(pReset)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
pReset_W_FTB01
|
||||
(
|
||||
.A(pReset_E_in),
|
||||
.X(pReset_W_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
pReset_E_FTB01
|
||||
(
|
||||
.A(pReset_E_in),
|
||||
.X(pReset_E_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
prog_clk_0_FTB00
|
||||
(
|
||||
.A(prog_clk_0_N_in),
|
||||
.X(prog_clk_0)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_0_W_FTB01
|
||||
(
|
||||
.A(prog_clk_0_N_in),
|
||||
.X(prog_clk_0_W_out)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,671 @@
|
|||
|
||||
|
||||
module cbx_1__1_
|
||||
( pReset, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, SC_IN_TOP, SC_OUT_BOT, SC_IN_BOT, SC_OUT_TOP, REGIN_FEEDTHROUGH, REGOUT_FEEDTHROUGH, CIN_FEEDTHROUGH, COUT_FEEDTHROUGH, pReset_E_in, pReset_W_in, pReset_W_out, pReset_S_out, pReset_E_out, prog_clk_0_N_in, prog_clk_0_W_out, prog_clk_1_W_in, prog_clk_1_E_in, prog_clk_1_N_out, prog_clk_1_S_out, prog_clk_2_E_in, prog_clk_2_W_in, prog_clk_2_W_out, prog_clk_2_E_out, prog_clk_3_W_in, prog_clk_3_E_in, prog_clk_3_E_out, prog_clk_3_W_out, clk_1_W_in, clk_1_E_in, clk_1_N_out, clk_1_S_out, clk_2_E_in, clk_2_W_in, clk_2_W_out, clk_2_E_out, clk_3_W_in, clk_3_E_in, clk_3_E_out, clk_3_W_out );
|
||||
input [0:0] pReset;
|
||||
input [0:29] chanx_left_in;
|
||||
input [0:29] chanx_right_in;
|
||||
input [0:0] ccff_head;
|
||||
output [0:29] chanx_left_out;
|
||||
output [0:29] chanx_right_out;
|
||||
output [0:0] bottom_grid_pin_0_;
|
||||
output [0:0] bottom_grid_pin_1_;
|
||||
output [0:0] bottom_grid_pin_2_;
|
||||
output [0:0] bottom_grid_pin_3_;
|
||||
output [0:0] bottom_grid_pin_4_;
|
||||
output [0:0] bottom_grid_pin_5_;
|
||||
output [0:0] bottom_grid_pin_6_;
|
||||
output [0:0] bottom_grid_pin_7_;
|
||||
output [0:0] bottom_grid_pin_8_;
|
||||
output [0:0] bottom_grid_pin_9_;
|
||||
output [0:0] bottom_grid_pin_10_;
|
||||
output [0:0] bottom_grid_pin_11_;
|
||||
output [0:0] bottom_grid_pin_12_;
|
||||
output [0:0] bottom_grid_pin_13_;
|
||||
output [0:0] bottom_grid_pin_14_;
|
||||
output [0:0] bottom_grid_pin_15_;
|
||||
output [0:0] ccff_tail;
|
||||
input SC_IN_TOP;
|
||||
output SC_OUT_BOT;
|
||||
input SC_IN_BOT;
|
||||
output SC_OUT_TOP;
|
||||
input REGIN_FEEDTHROUGH;
|
||||
output REGOUT_FEEDTHROUGH;
|
||||
input CIN_FEEDTHROUGH;
|
||||
output COUT_FEEDTHROUGH;
|
||||
input pReset_E_in;
|
||||
input pReset_W_in;
|
||||
output pReset_W_out;
|
||||
output pReset_S_out;
|
||||
output pReset_E_out;
|
||||
input prog_clk_0_N_in;
|
||||
output prog_clk_0_W_out;
|
||||
input prog_clk_1_W_in;
|
||||
input prog_clk_1_E_in;
|
||||
output prog_clk_1_N_out;
|
||||
output prog_clk_1_S_out;
|
||||
input prog_clk_2_E_in;
|
||||
input prog_clk_2_W_in;
|
||||
output prog_clk_2_W_out;
|
||||
output prog_clk_2_E_out;
|
||||
input prog_clk_3_W_in;
|
||||
input prog_clk_3_E_in;
|
||||
output prog_clk_3_E_out;
|
||||
output prog_clk_3_W_out;
|
||||
input clk_1_W_in;
|
||||
input clk_1_E_in;
|
||||
output clk_1_N_out;
|
||||
output clk_1_S_out;
|
||||
input clk_2_E_in;
|
||||
input clk_2_W_in;
|
||||
output clk_2_W_out;
|
||||
output clk_2_E_out;
|
||||
input clk_3_W_in;
|
||||
input clk_3_E_in;
|
||||
output clk_3_E_out;
|
||||
output clk_3_W_out;
|
||||
|
||||
wire [0:3] mux_2level_size10_0_sram;
|
||||
wire [0:3] mux_2level_size10_1_sram;
|
||||
wire [0:3] mux_2level_size10_2_sram;
|
||||
wire [0:3] mux_2level_size10_3_sram;
|
||||
wire [0:3] mux_2level_size10_4_sram;
|
||||
wire [0:3] mux_2level_size10_5_sram;
|
||||
wire [0:3] mux_2level_size10_6_sram;
|
||||
wire [0:3] mux_2level_size10_7_sram;
|
||||
wire [0:0] mux_2level_size10_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_2_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_3_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_4_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_5_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_6_ccff_tail;
|
||||
wire [0:3] mux_2level_size12_0_sram;
|
||||
wire [0:3] mux_2level_size12_1_sram;
|
||||
wire [0:3] mux_2level_size12_2_sram;
|
||||
wire [0:3] mux_2level_size12_3_sram;
|
||||
wire [0:3] mux_2level_size12_4_sram;
|
||||
wire [0:3] mux_2level_size12_5_sram;
|
||||
wire [0:3] mux_2level_size12_6_sram;
|
||||
wire [0:3] mux_2level_size12_7_sram;
|
||||
wire [0:0] mux_2level_size12_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_2_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_3_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_4_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_5_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_6_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_7_ccff_tail;
|
||||
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_10_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_11_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_12_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_13_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_14_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_15_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_7_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_9_undriven_sram_inv;
|
||||
wire prog_clk_0;
|
||||
wire [0:0] prog_clk;
|
||||
assign chanx_right_out[0] = chanx_left_in[0];
|
||||
assign chanx_right_out[1] = chanx_left_in[1];
|
||||
assign chanx_right_out[2] = chanx_left_in[2];
|
||||
assign chanx_right_out[3] = chanx_left_in[3];
|
||||
assign chanx_right_out[4] = chanx_left_in[4];
|
||||
assign chanx_right_out[5] = chanx_left_in[5];
|
||||
assign chanx_right_out[6] = chanx_left_in[6];
|
||||
assign chanx_right_out[7] = chanx_left_in[7];
|
||||
assign chanx_right_out[8] = chanx_left_in[8];
|
||||
assign chanx_right_out[9] = chanx_left_in[9];
|
||||
assign chanx_right_out[10] = chanx_left_in[10];
|
||||
assign chanx_right_out[11] = chanx_left_in[11];
|
||||
assign chanx_right_out[12] = chanx_left_in[12];
|
||||
assign chanx_right_out[13] = chanx_left_in[13];
|
||||
assign chanx_right_out[14] = chanx_left_in[14];
|
||||
assign chanx_right_out[15] = chanx_left_in[15];
|
||||
assign chanx_right_out[16] = chanx_left_in[16];
|
||||
assign chanx_right_out[17] = chanx_left_in[17];
|
||||
assign chanx_right_out[18] = chanx_left_in[18];
|
||||
assign chanx_right_out[19] = chanx_left_in[19];
|
||||
assign chanx_right_out[20] = chanx_left_in[20];
|
||||
assign chanx_right_out[21] = chanx_left_in[21];
|
||||
assign chanx_right_out[22] = chanx_left_in[22];
|
||||
assign chanx_right_out[23] = chanx_left_in[23];
|
||||
assign chanx_right_out[24] = chanx_left_in[24];
|
||||
assign chanx_right_out[25] = chanx_left_in[25];
|
||||
assign chanx_right_out[26] = chanx_left_in[26];
|
||||
assign chanx_right_out[27] = chanx_left_in[27];
|
||||
assign chanx_right_out[28] = chanx_left_in[28];
|
||||
assign chanx_right_out[29] = chanx_left_in[29];
|
||||
assign chanx_left_out[0] = chanx_right_in[0];
|
||||
assign chanx_left_out[1] = chanx_right_in[1];
|
||||
assign chanx_left_out[2] = chanx_right_in[2];
|
||||
assign chanx_left_out[3] = chanx_right_in[3];
|
||||
assign chanx_left_out[4] = chanx_right_in[4];
|
||||
assign chanx_left_out[5] = chanx_right_in[5];
|
||||
assign chanx_left_out[6] = chanx_right_in[6];
|
||||
assign chanx_left_out[7] = chanx_right_in[7];
|
||||
assign chanx_left_out[8] = chanx_right_in[8];
|
||||
assign chanx_left_out[9] = chanx_right_in[9];
|
||||
assign chanx_left_out[10] = chanx_right_in[10];
|
||||
assign chanx_left_out[11] = chanx_right_in[11];
|
||||
assign chanx_left_out[12] = chanx_right_in[12];
|
||||
assign chanx_left_out[13] = chanx_right_in[13];
|
||||
assign chanx_left_out[14] = chanx_right_in[14];
|
||||
assign chanx_left_out[15] = chanx_right_in[15];
|
||||
assign chanx_left_out[16] = chanx_right_in[16];
|
||||
assign chanx_left_out[17] = chanx_right_in[17];
|
||||
assign chanx_left_out[18] = chanx_right_in[18];
|
||||
assign chanx_left_out[19] = chanx_right_in[19];
|
||||
assign chanx_left_out[20] = chanx_right_in[20];
|
||||
assign chanx_left_out[21] = chanx_right_in[21];
|
||||
assign chanx_left_out[22] = chanx_right_in[22];
|
||||
assign chanx_left_out[23] = chanx_right_in[23];
|
||||
assign chanx_left_out[24] = chanx_right_in[24];
|
||||
assign chanx_left_out[25] = chanx_right_in[25];
|
||||
assign chanx_left_out[26] = chanx_right_in[26];
|
||||
assign chanx_left_out[27] = chanx_right_in[27];
|
||||
assign chanx_left_out[28] = chanx_right_in[28];
|
||||
assign chanx_left_out[29] = chanx_right_in[29];
|
||||
assign SC_OUT_BOT = SC_IN_TOP;
|
||||
assign SC_OUT_TOP = SC_IN_BOT;
|
||||
assign REGOUT_FEEDTHROUGH = REGIN_FEEDTHROUGH;
|
||||
assign COUT_FEEDTHROUGH = CIN_FEEDTHROUGH;
|
||||
assign pReset_E_in = pReset_W_in;
|
||||
assign prog_clk_0 = prog_clk;
|
||||
assign prog_clk_1_W_in = prog_clk_1_E_in;
|
||||
assign prog_clk_2_E_in = prog_clk_2_W_in;
|
||||
assign prog_clk_3_W_in = prog_clk_3_E_in;
|
||||
assign clk_1_W_in = clk_1_E_in;
|
||||
assign clk_2_E_in = clk_2_W_in;
|
||||
assign clk_3_W_in = clk_3_E_in;
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_0
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24] }),
|
||||
.sram(mux_2level_size12_0_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_0_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_2
|
||||
(
|
||||
.in({ chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26] }),
|
||||
.sram(mux_2level_size12_1_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_2_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_4
|
||||
(
|
||||
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28] }),
|
||||
.sram(mux_2level_size12_2_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_4_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_6
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24] }),
|
||||
.sram(mux_2level_size12_3_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_6_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_8
|
||||
(
|
||||
.in({ chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26] }),
|
||||
.sram(mux_2level_size12_4_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_8_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_10
|
||||
(
|
||||
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22], chanx_left_in[28], chanx_right_in[28] }),
|
||||
.sram(mux_2level_size12_5_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_10_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_12
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24] }),
|
||||
.sram(mux_2level_size12_6_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_12_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_14
|
||||
(
|
||||
.in({ chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[26], chanx_right_in[26] }),
|
||||
.sram(mux_2level_size12_7_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_14_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_0
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_0_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_2
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_1_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_4
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_2_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_6
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_3_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_8
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_4_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_10
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_5_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_12
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_6_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_14
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_7_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_7_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_1
|
||||
(
|
||||
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[16], chanx_right_in[16], chanx_left_in[25], chanx_right_in[25] }),
|
||||
.sram(mux_2level_size10_0_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_1_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_3
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[18], chanx_right_in[18], chanx_left_in[27], chanx_right_in[27] }),
|
||||
.sram(mux_2level_size10_1_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_3_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_5
|
||||
(
|
||||
.in({ chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[20], chanx_right_in[20], chanx_left_in[29], chanx_right_in[29] }),
|
||||
.sram(mux_2level_size10_2_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_5_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_7
|
||||
(
|
||||
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[22], chanx_right_in[22] }),
|
||||
.sram(mux_2level_size10_3_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_7_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_9
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[24], chanx_right_in[24] }),
|
||||
.sram(mux_2level_size10_4_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_9_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_11
|
||||
(
|
||||
.in({ chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[26], chanx_right_in[26] }),
|
||||
.sram(mux_2level_size10_5_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_11_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_13
|
||||
(
|
||||
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[28], chanx_right_in[28] }),
|
||||
.sram(mux_2level_size10_6_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_13_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_15
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21] }),
|
||||
.sram(mux_2level_size10_7_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_15_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_1
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_0_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_3
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_1_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_5
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_2_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_7
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_3_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_9
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_4_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_11
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_5_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_13
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_6_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_15
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_7_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_7_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
pReset_FTB00
|
||||
(
|
||||
.A(pReset_E_in),
|
||||
.X(pReset)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
pReset_W_FTB01
|
||||
(
|
||||
.A(pReset_E_in),
|
||||
.X(pReset_W_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
pReset_S_FTB01
|
||||
(
|
||||
.A(pReset_E_in),
|
||||
.X(pReset_S_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
pReset_E_FTB01
|
||||
(
|
||||
.A(pReset_E_in),
|
||||
.X(pReset_E_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
prog_clk_0_FTB00
|
||||
(
|
||||
.A(prog_clk_0_N_in),
|
||||
.X(prog_clk_0)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_0_W_FTB01
|
||||
(
|
||||
.A(prog_clk_0_N_in),
|
||||
.X(prog_clk_0_W_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_1_N_FTB01
|
||||
(
|
||||
.A(prog_clk_1_W_in),
|
||||
.X(prog_clk_1_N_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_1_S_FTB01
|
||||
(
|
||||
.A(prog_clk_1_W_in),
|
||||
.X(prog_clk_1_S_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_2_W_FTB01
|
||||
(
|
||||
.A(prog_clk_2_E_in),
|
||||
.X(prog_clk_2_W_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_2_E_FTB01
|
||||
(
|
||||
.A(prog_clk_2_E_in),
|
||||
.X(prog_clk_2_E_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_3_E_FTB01
|
||||
(
|
||||
.A(prog_clk_3_W_in),
|
||||
.X(prog_clk_3_E_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_3_W_FTB01
|
||||
(
|
||||
.A(prog_clk_3_W_in),
|
||||
.X(prog_clk_3_W_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
clk_1_N_FTB01
|
||||
(
|
||||
.A(clk_1_W_in),
|
||||
.X(clk_1_N_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
clk_1_S_FTB01
|
||||
(
|
||||
.A(clk_1_W_in),
|
||||
.X(clk_1_S_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
clk_2_W_FTB01
|
||||
(
|
||||
.A(clk_2_E_in),
|
||||
.X(clk_2_W_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
clk_2_E_FTB01
|
||||
(
|
||||
.A(clk_2_E_in),
|
||||
.X(clk_2_E_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
clk_3_E_FTB01
|
||||
(
|
||||
.A(clk_3_W_in),
|
||||
.X(clk_3_E_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
clk_3_W_FTB01
|
||||
(
|
||||
.A(clk_3_W_in),
|
||||
.X(clk_3_W_out)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,589 @@
|
|||
|
||||
|
||||
module cbx_1__2_
|
||||
( pReset, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, top_grid_pin_0_, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, IO_ISOL_N, gfpga_pad_EMBEDDED_IO_HD_SOC_IN, gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, bottom_width_0_height_0__pin_0_, bottom_width_0_height_0__pin_1_upper, bottom_width_0_height_0__pin_1_lower, SC_IN_TOP, SC_OUT_BOT, SC_IN_BOT, SC_OUT_TOP, pReset_E_in, pReset_W_in, pReset_W_out, pReset_S_out, pReset_E_out, prog_clk_0_S_in, prog_clk_0_W_out );
|
||||
input [0:0] pReset;
|
||||
input [0:29] chanx_left_in;
|
||||
input [0:29] chanx_right_in;
|
||||
input [0:0] ccff_head;
|
||||
output [0:29] chanx_left_out;
|
||||
output [0:29] chanx_right_out;
|
||||
output [0:0] top_grid_pin_0_;
|
||||
output [0:0] bottom_grid_pin_0_;
|
||||
output [0:0] bottom_grid_pin_1_;
|
||||
output [0:0] bottom_grid_pin_2_;
|
||||
output [0:0] bottom_grid_pin_3_;
|
||||
output [0:0] bottom_grid_pin_4_;
|
||||
output [0:0] bottom_grid_pin_5_;
|
||||
output [0:0] bottom_grid_pin_6_;
|
||||
output [0:0] bottom_grid_pin_7_;
|
||||
output [0:0] bottom_grid_pin_8_;
|
||||
output [0:0] bottom_grid_pin_9_;
|
||||
output [0:0] bottom_grid_pin_10_;
|
||||
output [0:0] bottom_grid_pin_11_;
|
||||
output [0:0] bottom_grid_pin_12_;
|
||||
output [0:0] bottom_grid_pin_13_;
|
||||
output [0:0] bottom_grid_pin_14_;
|
||||
output [0:0] bottom_grid_pin_15_;
|
||||
output [0:0] ccff_tail;
|
||||
input [0:0] IO_ISOL_N;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
|
||||
input [0:0] bottom_width_0_height_0__pin_0_;
|
||||
output [0:0] bottom_width_0_height_0__pin_1_upper;
|
||||
output [0:0] bottom_width_0_height_0__pin_1_lower;
|
||||
input SC_IN_TOP;
|
||||
output SC_OUT_BOT;
|
||||
input SC_IN_BOT;
|
||||
output SC_OUT_TOP;
|
||||
input pReset_E_in;
|
||||
input pReset_W_in;
|
||||
output pReset_W_out;
|
||||
output pReset_S_out;
|
||||
output pReset_E_out;
|
||||
input prog_clk_0_S_in;
|
||||
output prog_clk_0_W_out;
|
||||
|
||||
wire [0:3] mux_2level_size10_0_sram;
|
||||
wire [0:3] mux_2level_size10_1_sram;
|
||||
wire [0:3] mux_2level_size10_2_sram;
|
||||
wire [0:3] mux_2level_size10_3_sram;
|
||||
wire [0:3] mux_2level_size10_4_sram;
|
||||
wire [0:3] mux_2level_size10_5_sram;
|
||||
wire [0:3] mux_2level_size10_6_sram;
|
||||
wire [0:3] mux_2level_size10_7_sram;
|
||||
wire [0:0] mux_2level_size10_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_2_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_3_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_4_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_5_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_6_ccff_tail;
|
||||
wire [0:3] mux_2level_size12_0_sram;
|
||||
wire [0:3] mux_2level_size12_1_sram;
|
||||
wire [0:3] mux_2level_size12_2_sram;
|
||||
wire [0:3] mux_2level_size12_3_sram;
|
||||
wire [0:3] mux_2level_size12_4_sram;
|
||||
wire [0:3] mux_2level_size12_5_sram;
|
||||
wire [0:3] mux_2level_size12_6_sram;
|
||||
wire [0:3] mux_2level_size12_7_sram;
|
||||
wire [0:3] mux_2level_size12_8_sram;
|
||||
wire [0:0] mux_2level_size12_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_2_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_3_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_4_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_5_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_6_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_7_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_8_ccff_tail;
|
||||
wire [0:3] mux_bottom_ipin_0_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_10_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_11_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_12_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_13_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_14_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_15_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_7_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
|
||||
wire [0:3] mux_top_ipin_9_undriven_sram_inv;
|
||||
wire ccff_tail_mid;
|
||||
wire prog_clk_0;
|
||||
wire [0:0] prog_clk;
|
||||
assign chanx_right_out[0] = chanx_left_in[0];
|
||||
assign chanx_right_out[1] = chanx_left_in[1];
|
||||
assign chanx_right_out[2] = chanx_left_in[2];
|
||||
assign chanx_right_out[3] = chanx_left_in[3];
|
||||
assign chanx_right_out[4] = chanx_left_in[4];
|
||||
assign chanx_right_out[5] = chanx_left_in[5];
|
||||
assign chanx_right_out[6] = chanx_left_in[6];
|
||||
assign chanx_right_out[7] = chanx_left_in[7];
|
||||
assign chanx_right_out[8] = chanx_left_in[8];
|
||||
assign chanx_right_out[9] = chanx_left_in[9];
|
||||
assign chanx_right_out[10] = chanx_left_in[10];
|
||||
assign chanx_right_out[11] = chanx_left_in[11];
|
||||
assign chanx_right_out[12] = chanx_left_in[12];
|
||||
assign chanx_right_out[13] = chanx_left_in[13];
|
||||
assign chanx_right_out[14] = chanx_left_in[14];
|
||||
assign chanx_right_out[15] = chanx_left_in[15];
|
||||
assign chanx_right_out[16] = chanx_left_in[16];
|
||||
assign chanx_right_out[17] = chanx_left_in[17];
|
||||
assign chanx_right_out[18] = chanx_left_in[18];
|
||||
assign chanx_right_out[19] = chanx_left_in[19];
|
||||
assign chanx_right_out[20] = chanx_left_in[20];
|
||||
assign chanx_right_out[21] = chanx_left_in[21];
|
||||
assign chanx_right_out[22] = chanx_left_in[22];
|
||||
assign chanx_right_out[23] = chanx_left_in[23];
|
||||
assign chanx_right_out[24] = chanx_left_in[24];
|
||||
assign chanx_right_out[25] = chanx_left_in[25];
|
||||
assign chanx_right_out[26] = chanx_left_in[26];
|
||||
assign chanx_right_out[27] = chanx_left_in[27];
|
||||
assign chanx_right_out[28] = chanx_left_in[28];
|
||||
assign chanx_right_out[29] = chanx_left_in[29];
|
||||
assign chanx_left_out[0] = chanx_right_in[0];
|
||||
assign chanx_left_out[1] = chanx_right_in[1];
|
||||
assign chanx_left_out[2] = chanx_right_in[2];
|
||||
assign chanx_left_out[3] = chanx_right_in[3];
|
||||
assign chanx_left_out[4] = chanx_right_in[4];
|
||||
assign chanx_left_out[5] = chanx_right_in[5];
|
||||
assign chanx_left_out[6] = chanx_right_in[6];
|
||||
assign chanx_left_out[7] = chanx_right_in[7];
|
||||
assign chanx_left_out[8] = chanx_right_in[8];
|
||||
assign chanx_left_out[9] = chanx_right_in[9];
|
||||
assign chanx_left_out[10] = chanx_right_in[10];
|
||||
assign chanx_left_out[11] = chanx_right_in[11];
|
||||
assign chanx_left_out[12] = chanx_right_in[12];
|
||||
assign chanx_left_out[13] = chanx_right_in[13];
|
||||
assign chanx_left_out[14] = chanx_right_in[14];
|
||||
assign chanx_left_out[15] = chanx_right_in[15];
|
||||
assign chanx_left_out[16] = chanx_right_in[16];
|
||||
assign chanx_left_out[17] = chanx_right_in[17];
|
||||
assign chanx_left_out[18] = chanx_right_in[18];
|
||||
assign chanx_left_out[19] = chanx_right_in[19];
|
||||
assign chanx_left_out[20] = chanx_right_in[20];
|
||||
assign chanx_left_out[21] = chanx_right_in[21];
|
||||
assign chanx_left_out[22] = chanx_right_in[22];
|
||||
assign chanx_left_out[23] = chanx_right_in[23];
|
||||
assign chanx_left_out[24] = chanx_right_in[24];
|
||||
assign chanx_left_out[25] = chanx_right_in[25];
|
||||
assign chanx_left_out[26] = chanx_right_in[26];
|
||||
assign chanx_left_out[27] = chanx_right_in[27];
|
||||
assign chanx_left_out[28] = chanx_right_in[28];
|
||||
assign chanx_left_out[29] = chanx_right_in[29];
|
||||
assign bottom_width_0_height_0__pin_1_lower[0] = bottom_width_0_height_0__pin_1_upper[0];
|
||||
assign SC_OUT_BOT = SC_IN_TOP;
|
||||
assign SC_OUT_TOP = SC_IN_BOT;
|
||||
assign pReset_E_in = pReset_W_in;
|
||||
assign prog_clk_0 = prog_clk;
|
||||
|
||||
mux_2level_size12
|
||||
mux_bottom_ipin_0
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[24], chanx_right_in[24] }),
|
||||
.sram(mux_2level_size12_0_sram[0:3]),
|
||||
.sram_inv(mux_bottom_ipin_0_undriven_sram_inv[0:3]),
|
||||
.out(top_grid_pin_0_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_0
|
||||
(
|
||||
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25] }),
|
||||
.sram(mux_2level_size12_1_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_0_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_2
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27] }),
|
||||
.sram(mux_2level_size12_2_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_2_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_4
|
||||
(
|
||||
.in({ chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[23], chanx_right_in[23], chanx_left_in[29], chanx_right_in[29] }),
|
||||
.sram(mux_2level_size12_3_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_4_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_6
|
||||
(
|
||||
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25] }),
|
||||
.sram(mux_2level_size12_4_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_6_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_8
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27] }),
|
||||
.sram(mux_2level_size12_5_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_8_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_10
|
||||
(
|
||||
.in({ chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17], chanx_left_in[23], chanx_right_in[23], chanx_left_in[29], chanx_right_in[29] }),
|
||||
.sram(mux_2level_size12_6_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_10_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_12
|
||||
(
|
||||
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19], chanx_left_in[25], chanx_right_in[25] }),
|
||||
.sram(mux_2level_size12_7_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_12_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_top_ipin_14
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[21], chanx_right_in[21], chanx_left_in[27], chanx_right_in[27] }),
|
||||
.sram(mux_2level_size12_8_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_14_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_bottom_ipin_0
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_0_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_0
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_1_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_2
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_2_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_4
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_3_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_6
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_4_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_8
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_5_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_10
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_6_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_12
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_7_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_7_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_top_ipin_14
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_8_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_8_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_1
|
||||
(
|
||||
.in({ chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[17], chanx_right_in[17], chanx_left_in[26], chanx_right_in[26] }),
|
||||
.sram(mux_2level_size10_0_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_1_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_3
|
||||
(
|
||||
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[19], chanx_right_in[19], chanx_left_in[28], chanx_right_in[28] }),
|
||||
.sram(mux_2level_size10_1_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_3_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_5
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[21], chanx_right_in[21] }),
|
||||
.sram(mux_2level_size10_2_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_5_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_7
|
||||
(
|
||||
.in({ chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14], chanx_left_in[23], chanx_right_in[23] }),
|
||||
.sram(mux_2level_size10_3_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_7_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_9
|
||||
(
|
||||
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16], chanx_left_in[25], chanx_right_in[25] }),
|
||||
.sram(mux_2level_size10_4_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_9_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_11
|
||||
(
|
||||
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[3], chanx_right_in[3], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18], chanx_left_in[27], chanx_right_in[27] }),
|
||||
.sram(mux_2level_size10_5_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_11_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_13
|
||||
(
|
||||
.in({ chanx_left_in[2], chanx_right_in[2], chanx_left_in[5], chanx_right_in[5], chanx_left_in[14], chanx_right_in[14], chanx_left_in[20], chanx_right_in[20], chanx_left_in[29], chanx_right_in[29] }),
|
||||
.sram(mux_2level_size10_6_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_13_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_top_ipin_15
|
||||
(
|
||||
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[4], chanx_right_in[4], chanx_left_in[7], chanx_right_in[7], chanx_left_in[16], chanx_right_in[16], chanx_left_in[22], chanx_right_in[22] }),
|
||||
.sram(mux_2level_size10_7_sram[0:3]),
|
||||
.sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]),
|
||||
.out(bottom_grid_pin_15_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_1
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_0_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_3
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_1_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_5
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_2_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_7
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_3_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_9
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_4_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_11
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_5_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_13
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_7_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_6_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_top_ipin_15
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_8_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.mem_out(mux_2level_size10_7_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
logical_tile_io_mode_io_
|
||||
logical_tile_io_mode_io__0
|
||||
(
|
||||
.IO_ISOL_N(IO_ISOL_N[0]),
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
|
||||
.io_outpad(bottom_width_0_height_0__pin_0_[0]),
|
||||
.ccff_head(ccff_tail_mid),
|
||||
.io_inpad(bottom_width_0_height_0__pin_1_upper[0]),
|
||||
.ccff_tail(ccff_tail[0])
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
pReset_FTB00
|
||||
(
|
||||
.A(pReset_E_in),
|
||||
.X(pReset)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
pReset_W_FTB01
|
||||
(
|
||||
.A(pReset_E_in),
|
||||
.X(pReset_W_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
pReset_S_FTB01
|
||||
(
|
||||
.A(pReset_E_in),
|
||||
.X(pReset_S_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
pReset_E_FTB01
|
||||
(
|
||||
.A(pReset_E_in),
|
||||
.X(pReset_E_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
prog_clk_0_FTB00
|
||||
(
|
||||
.A(prog_clk_0_S_in),
|
||||
.X(prog_clk_0)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_0_W_FTB01
|
||||
(
|
||||
.A(prog_clk_0_S_in),
|
||||
.X(prog_clk_0_W_out)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
|
||||
|
||||
module cby_0__1_
|
||||
( pReset, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_0_, ccff_tail, IO_ISOL_N, gfpga_pad_EMBEDDED_IO_HD_SOC_IN, gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, right_width_0_height_0__pin_0_, right_width_0_height_0__pin_1_upper, right_width_0_height_0__pin_1_lower, pReset_N_in, prog_clk_0_E_in );
|
||||
input [0:0] pReset;
|
||||
input [0:29] chany_bottom_in;
|
||||
input [0:29] chany_top_in;
|
||||
input [0:0] ccff_head;
|
||||
output [0:29] chany_bottom_out;
|
||||
output [0:29] chany_top_out;
|
||||
output [0:0] left_grid_pin_0_;
|
||||
output [0:0] ccff_tail;
|
||||
input [0:0] IO_ISOL_N;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
|
||||
input [0:0] right_width_0_height_0__pin_0_;
|
||||
output [0:0] right_width_0_height_0__pin_1_upper;
|
||||
output [0:0] right_width_0_height_0__pin_1_lower;
|
||||
input pReset_N_in;
|
||||
input prog_clk_0_E_in;
|
||||
|
||||
wire [0:3] mux_2level_size12_0_sram;
|
||||
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
|
||||
wire ccff_tail_mid;
|
||||
wire prog_clk_0;
|
||||
wire [0:0] prog_clk;
|
||||
assign chany_top_out[0] = chany_bottom_in[0];
|
||||
assign chany_top_out[1] = chany_bottom_in[1];
|
||||
assign chany_top_out[2] = chany_bottom_in[2];
|
||||
assign chany_top_out[3] = chany_bottom_in[3];
|
||||
assign chany_top_out[4] = chany_bottom_in[4];
|
||||
assign chany_top_out[5] = chany_bottom_in[5];
|
||||
assign chany_top_out[6] = chany_bottom_in[6];
|
||||
assign chany_top_out[7] = chany_bottom_in[7];
|
||||
assign chany_top_out[8] = chany_bottom_in[8];
|
||||
assign chany_top_out[9] = chany_bottom_in[9];
|
||||
assign chany_top_out[10] = chany_bottom_in[10];
|
||||
assign chany_top_out[11] = chany_bottom_in[11];
|
||||
assign chany_top_out[12] = chany_bottom_in[12];
|
||||
assign chany_top_out[13] = chany_bottom_in[13];
|
||||
assign chany_top_out[14] = chany_bottom_in[14];
|
||||
assign chany_top_out[15] = chany_bottom_in[15];
|
||||
assign chany_top_out[16] = chany_bottom_in[16];
|
||||
assign chany_top_out[17] = chany_bottom_in[17];
|
||||
assign chany_top_out[18] = chany_bottom_in[18];
|
||||
assign chany_top_out[19] = chany_bottom_in[19];
|
||||
assign chany_top_out[20] = chany_bottom_in[20];
|
||||
assign chany_top_out[21] = chany_bottom_in[21];
|
||||
assign chany_top_out[22] = chany_bottom_in[22];
|
||||
assign chany_top_out[23] = chany_bottom_in[23];
|
||||
assign chany_top_out[24] = chany_bottom_in[24];
|
||||
assign chany_top_out[25] = chany_bottom_in[25];
|
||||
assign chany_top_out[26] = chany_bottom_in[26];
|
||||
assign chany_top_out[27] = chany_bottom_in[27];
|
||||
assign chany_top_out[28] = chany_bottom_in[28];
|
||||
assign chany_top_out[29] = chany_bottom_in[29];
|
||||
assign chany_bottom_out[0] = chany_top_in[0];
|
||||
assign chany_bottom_out[1] = chany_top_in[1];
|
||||
assign chany_bottom_out[2] = chany_top_in[2];
|
||||
assign chany_bottom_out[3] = chany_top_in[3];
|
||||
assign chany_bottom_out[4] = chany_top_in[4];
|
||||
assign chany_bottom_out[5] = chany_top_in[5];
|
||||
assign chany_bottom_out[6] = chany_top_in[6];
|
||||
assign chany_bottom_out[7] = chany_top_in[7];
|
||||
assign chany_bottom_out[8] = chany_top_in[8];
|
||||
assign chany_bottom_out[9] = chany_top_in[9];
|
||||
assign chany_bottom_out[10] = chany_top_in[10];
|
||||
assign chany_bottom_out[11] = chany_top_in[11];
|
||||
assign chany_bottom_out[12] = chany_top_in[12];
|
||||
assign chany_bottom_out[13] = chany_top_in[13];
|
||||
assign chany_bottom_out[14] = chany_top_in[14];
|
||||
assign chany_bottom_out[15] = chany_top_in[15];
|
||||
assign chany_bottom_out[16] = chany_top_in[16];
|
||||
assign chany_bottom_out[17] = chany_top_in[17];
|
||||
assign chany_bottom_out[18] = chany_top_in[18];
|
||||
assign chany_bottom_out[19] = chany_top_in[19];
|
||||
assign chany_bottom_out[20] = chany_top_in[20];
|
||||
assign chany_bottom_out[21] = chany_top_in[21];
|
||||
assign chany_bottom_out[22] = chany_top_in[22];
|
||||
assign chany_bottom_out[23] = chany_top_in[23];
|
||||
assign chany_bottom_out[24] = chany_top_in[24];
|
||||
assign chany_bottom_out[25] = chany_top_in[25];
|
||||
assign chany_bottom_out[26] = chany_top_in[26];
|
||||
assign chany_bottom_out[27] = chany_top_in[27];
|
||||
assign chany_bottom_out[28] = chany_top_in[28];
|
||||
assign chany_bottom_out[29] = chany_top_in[29];
|
||||
assign right_width_0_height_0__pin_1_lower[0] = right_width_0_height_0__pin_1_upper[0];
|
||||
assign prog_clk_0 = prog_clk;
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_0
|
||||
(
|
||||
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24] }),
|
||||
.sram(mux_2level_size12_0_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_0_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_0
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.mem_out(mux_2level_size12_0_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
logical_tile_io_mode_io_
|
||||
logical_tile_io_mode_io__0
|
||||
(
|
||||
.IO_ISOL_N(IO_ISOL_N[0]),
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
|
||||
.io_outpad(right_width_0_height_0__pin_0_[0]),
|
||||
.ccff_head(ccff_tail_mid),
|
||||
.io_inpad(right_width_0_height_0__pin_1_upper[0]),
|
||||
.ccff_tail(ccff_tail[0])
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
pReset_FTB00
|
||||
(
|
||||
.A(pReset_N_in),
|
||||
.X(pReset)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
prog_clk_0_FTB00
|
||||
(
|
||||
.A(prog_clk_0_E_in),
|
||||
.X(prog_clk_0)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,670 @@
|
|||
|
||||
|
||||
module cby_1__1_
|
||||
( pReset, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail, Test_en_S_in, Test_en_E_in, Test_en_W_in, Test_en_N_out, Test_en_W_out, Test_en_E_out, pReset_S_in, pReset_N_out, Reset_S_in, Reset_E_in, Reset_W_in, Reset_N_out, Reset_W_out, Reset_E_out, prog_clk_0_W_in, prog_clk_0_S_out, prog_clk_0_N_out, prog_clk_2_N_in, prog_clk_2_S_in, prog_clk_2_S_out, prog_clk_2_N_out, prog_clk_3_S_in, prog_clk_3_N_in, prog_clk_3_N_out, prog_clk_3_S_out, clk_2_N_in, clk_2_S_in, clk_2_S_out, clk_2_N_out, clk_3_S_in, clk_3_N_in, clk_3_N_out, clk_3_S_out );
|
||||
input [0:0] pReset;
|
||||
input [0:29] chany_bottom_in;
|
||||
input [0:29] chany_top_in;
|
||||
input [0:0] ccff_head;
|
||||
output [0:29] chany_bottom_out;
|
||||
output [0:29] chany_top_out;
|
||||
output [0:0] left_grid_pin_16_;
|
||||
output [0:0] left_grid_pin_17_;
|
||||
output [0:0] left_grid_pin_18_;
|
||||
output [0:0] left_grid_pin_19_;
|
||||
output [0:0] left_grid_pin_20_;
|
||||
output [0:0] left_grid_pin_21_;
|
||||
output [0:0] left_grid_pin_22_;
|
||||
output [0:0] left_grid_pin_23_;
|
||||
output [0:0] left_grid_pin_24_;
|
||||
output [0:0] left_grid_pin_25_;
|
||||
output [0:0] left_grid_pin_26_;
|
||||
output [0:0] left_grid_pin_27_;
|
||||
output [0:0] left_grid_pin_28_;
|
||||
output [0:0] left_grid_pin_29_;
|
||||
output [0:0] left_grid_pin_30_;
|
||||
output [0:0] left_grid_pin_31_;
|
||||
output [0:0] ccff_tail;
|
||||
input Test_en_S_in;
|
||||
input Test_en_E_in;
|
||||
input Test_en_W_in;
|
||||
output Test_en_N_out;
|
||||
output Test_en_W_out;
|
||||
output Test_en_E_out;
|
||||
input pReset_S_in;
|
||||
output pReset_N_out;
|
||||
input Reset_S_in;
|
||||
input Reset_E_in;
|
||||
input Reset_W_in;
|
||||
output Reset_N_out;
|
||||
output Reset_W_out;
|
||||
output Reset_E_out;
|
||||
input prog_clk_0_W_in;
|
||||
output prog_clk_0_S_out;
|
||||
output prog_clk_0_N_out;
|
||||
input prog_clk_2_N_in;
|
||||
input prog_clk_2_S_in;
|
||||
output prog_clk_2_S_out;
|
||||
output prog_clk_2_N_out;
|
||||
input prog_clk_3_S_in;
|
||||
input prog_clk_3_N_in;
|
||||
output prog_clk_3_N_out;
|
||||
output prog_clk_3_S_out;
|
||||
input clk_2_N_in;
|
||||
input clk_2_S_in;
|
||||
output clk_2_S_out;
|
||||
output clk_2_N_out;
|
||||
input clk_3_S_in;
|
||||
input clk_3_N_in;
|
||||
output clk_3_N_out;
|
||||
output clk_3_S_out;
|
||||
|
||||
wire [0:3] mux_2level_size10_0_sram;
|
||||
wire [0:3] mux_2level_size10_1_sram;
|
||||
wire [0:3] mux_2level_size10_2_sram;
|
||||
wire [0:3] mux_2level_size10_3_sram;
|
||||
wire [0:3] mux_2level_size10_4_sram;
|
||||
wire [0:3] mux_2level_size10_5_sram;
|
||||
wire [0:3] mux_2level_size10_6_sram;
|
||||
wire [0:3] mux_2level_size10_7_sram;
|
||||
wire [0:0] mux_2level_size10_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_2_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_3_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_4_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_5_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_6_ccff_tail;
|
||||
wire [0:3] mux_2level_size12_0_sram;
|
||||
wire [0:3] mux_2level_size12_1_sram;
|
||||
wire [0:3] mux_2level_size12_2_sram;
|
||||
wire [0:3] mux_2level_size12_3_sram;
|
||||
wire [0:3] mux_2level_size12_4_sram;
|
||||
wire [0:3] mux_2level_size12_5_sram;
|
||||
wire [0:3] mux_2level_size12_6_sram;
|
||||
wire [0:3] mux_2level_size12_7_sram;
|
||||
wire [0:0] mux_2level_size12_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_2_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_3_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_4_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_5_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_6_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_7_ccff_tail;
|
||||
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_10_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_11_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_12_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_13_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_14_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_15_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_1_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_2_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_3_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_4_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_5_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_6_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_7_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_8_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_9_undriven_sram_inv;
|
||||
wire prog_clk_0;
|
||||
wire [0:0] prog_clk;
|
||||
assign chany_top_out[0] = chany_bottom_in[0];
|
||||
assign chany_top_out[1] = chany_bottom_in[1];
|
||||
assign chany_top_out[2] = chany_bottom_in[2];
|
||||
assign chany_top_out[3] = chany_bottom_in[3];
|
||||
assign chany_top_out[4] = chany_bottom_in[4];
|
||||
assign chany_top_out[5] = chany_bottom_in[5];
|
||||
assign chany_top_out[6] = chany_bottom_in[6];
|
||||
assign chany_top_out[7] = chany_bottom_in[7];
|
||||
assign chany_top_out[8] = chany_bottom_in[8];
|
||||
assign chany_top_out[9] = chany_bottom_in[9];
|
||||
assign chany_top_out[10] = chany_bottom_in[10];
|
||||
assign chany_top_out[11] = chany_bottom_in[11];
|
||||
assign chany_top_out[12] = chany_bottom_in[12];
|
||||
assign chany_top_out[13] = chany_bottom_in[13];
|
||||
assign chany_top_out[14] = chany_bottom_in[14];
|
||||
assign chany_top_out[15] = chany_bottom_in[15];
|
||||
assign chany_top_out[16] = chany_bottom_in[16];
|
||||
assign chany_top_out[17] = chany_bottom_in[17];
|
||||
assign chany_top_out[18] = chany_bottom_in[18];
|
||||
assign chany_top_out[19] = chany_bottom_in[19];
|
||||
assign chany_top_out[20] = chany_bottom_in[20];
|
||||
assign chany_top_out[21] = chany_bottom_in[21];
|
||||
assign chany_top_out[22] = chany_bottom_in[22];
|
||||
assign chany_top_out[23] = chany_bottom_in[23];
|
||||
assign chany_top_out[24] = chany_bottom_in[24];
|
||||
assign chany_top_out[25] = chany_bottom_in[25];
|
||||
assign chany_top_out[26] = chany_bottom_in[26];
|
||||
assign chany_top_out[27] = chany_bottom_in[27];
|
||||
assign chany_top_out[28] = chany_bottom_in[28];
|
||||
assign chany_top_out[29] = chany_bottom_in[29];
|
||||
assign chany_bottom_out[0] = chany_top_in[0];
|
||||
assign chany_bottom_out[1] = chany_top_in[1];
|
||||
assign chany_bottom_out[2] = chany_top_in[2];
|
||||
assign chany_bottom_out[3] = chany_top_in[3];
|
||||
assign chany_bottom_out[4] = chany_top_in[4];
|
||||
assign chany_bottom_out[5] = chany_top_in[5];
|
||||
assign chany_bottom_out[6] = chany_top_in[6];
|
||||
assign chany_bottom_out[7] = chany_top_in[7];
|
||||
assign chany_bottom_out[8] = chany_top_in[8];
|
||||
assign chany_bottom_out[9] = chany_top_in[9];
|
||||
assign chany_bottom_out[10] = chany_top_in[10];
|
||||
assign chany_bottom_out[11] = chany_top_in[11];
|
||||
assign chany_bottom_out[12] = chany_top_in[12];
|
||||
assign chany_bottom_out[13] = chany_top_in[13];
|
||||
assign chany_bottom_out[14] = chany_top_in[14];
|
||||
assign chany_bottom_out[15] = chany_top_in[15];
|
||||
assign chany_bottom_out[16] = chany_top_in[16];
|
||||
assign chany_bottom_out[17] = chany_top_in[17];
|
||||
assign chany_bottom_out[18] = chany_top_in[18];
|
||||
assign chany_bottom_out[19] = chany_top_in[19];
|
||||
assign chany_bottom_out[20] = chany_top_in[20];
|
||||
assign chany_bottom_out[21] = chany_top_in[21];
|
||||
assign chany_bottom_out[22] = chany_top_in[22];
|
||||
assign chany_bottom_out[23] = chany_top_in[23];
|
||||
assign chany_bottom_out[24] = chany_top_in[24];
|
||||
assign chany_bottom_out[25] = chany_top_in[25];
|
||||
assign chany_bottom_out[26] = chany_top_in[26];
|
||||
assign chany_bottom_out[27] = chany_top_in[27];
|
||||
assign chany_bottom_out[28] = chany_top_in[28];
|
||||
assign chany_bottom_out[29] = chany_top_in[29];
|
||||
assign Test_en_S_in = Test_en_E_in;
|
||||
assign Test_en_E_in = Test_en_W_in;
|
||||
assign Reset_S_in = Reset_E_in;
|
||||
assign Reset_E_in = Reset_W_in;
|
||||
assign prog_clk_0 = prog_clk;
|
||||
assign prog_clk_2_N_in = prog_clk_2_S_in;
|
||||
assign prog_clk_3_S_in = prog_clk_3_N_in;
|
||||
assign clk_2_N_in = clk_2_S_in;
|
||||
assign clk_3_S_in = clk_3_N_in;
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_0
|
||||
(
|
||||
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24] }),
|
||||
.sram(mux_2level_size12_0_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_16_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_2
|
||||
(
|
||||
.in({ chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26] }),
|
||||
.sram(mux_2level_size12_1_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_18_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_4
|
||||
(
|
||||
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28] }),
|
||||
.sram(mux_2level_size12_2_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_20_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_6
|
||||
(
|
||||
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24] }),
|
||||
.sram(mux_2level_size12_3_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_22_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_8
|
||||
(
|
||||
.in({ chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26] }),
|
||||
.sram(mux_2level_size12_4_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_24_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_10
|
||||
(
|
||||
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22], chany_bottom_in[28], chany_top_in[28] }),
|
||||
.sram(mux_2level_size12_5_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_26_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_12
|
||||
(
|
||||
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24] }),
|
||||
.sram(mux_2level_size12_6_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_28_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_14
|
||||
(
|
||||
.in({ chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[26], chany_top_in[26] }),
|
||||
.sram(mux_2level_size12_7_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_30_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_0
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_0_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_2
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_1_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_4
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_2_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_6
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_3_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_8
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_4_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_10
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_5_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_12
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_6_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_14
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_7_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_7_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_1
|
||||
(
|
||||
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[25], chany_top_in[25] }),
|
||||
.sram(mux_2level_size10_0_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_17_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_3
|
||||
(
|
||||
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[27], chany_top_in[27] }),
|
||||
.sram(mux_2level_size10_1_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_19_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_5
|
||||
(
|
||||
.in({ chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[29], chany_top_in[29] }),
|
||||
.sram(mux_2level_size10_2_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_21_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_7
|
||||
(
|
||||
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[22], chany_top_in[22] }),
|
||||
.sram(mux_2level_size10_3_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_23_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_9
|
||||
(
|
||||
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[24], chany_top_in[24] }),
|
||||
.sram(mux_2level_size10_4_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_25_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_11
|
||||
(
|
||||
.in({ chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[26], chany_top_in[26] }),
|
||||
.sram(mux_2level_size10_5_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_27_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_13
|
||||
(
|
||||
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[28], chany_top_in[28] }),
|
||||
.sram(mux_2level_size10_6_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_29_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_15
|
||||
(
|
||||
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21] }),
|
||||
.sram(mux_2level_size10_7_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_31_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_1
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_0_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_3
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_1_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_5
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_2_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_7
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_3_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_9
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_4_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_11
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_5_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_13
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_6_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_15
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_7_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_7_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
Test_en_N_FTB01
|
||||
(
|
||||
.A(Test_en_S_in),
|
||||
.X(Test_en_N_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
Test_en_W_FTB01
|
||||
(
|
||||
.A(Test_en_S_in),
|
||||
.X(Test_en_W_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
Test_en_E_FTB01
|
||||
(
|
||||
.A(Test_en_S_in),
|
||||
.X(Test_en_E_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
pReset_FTB00
|
||||
(
|
||||
.A(pReset_S_in),
|
||||
.X(pReset)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
pReset_N_FTB01
|
||||
(
|
||||
.A(pReset_S_in),
|
||||
.X(pReset_N_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
Reset_N_FTB01
|
||||
(
|
||||
.A(Reset_S_in),
|
||||
.X(Reset_N_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
Reset_W_FTB01
|
||||
(
|
||||
.A(Reset_S_in),
|
||||
.X(Reset_W_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
Reset_E_FTB01
|
||||
(
|
||||
.A(Reset_S_in),
|
||||
.X(Reset_E_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
prog_clk_0_FTB00
|
||||
(
|
||||
.A(prog_clk_0_W_in),
|
||||
.X(prog_clk_0)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_0_S_FTB01
|
||||
(
|
||||
.A(prog_clk_0_W_in),
|
||||
.X(prog_clk_0_S_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_0_N_FTB01
|
||||
(
|
||||
.A(prog_clk_0_W_in),
|
||||
.X(prog_clk_0_N_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_2_S_FTB01
|
||||
(
|
||||
.A(prog_clk_2_N_in),
|
||||
.X(prog_clk_2_S_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_2_N_FTB01
|
||||
(
|
||||
.A(prog_clk_2_N_in),
|
||||
.X(prog_clk_2_N_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_3_N_FTB01
|
||||
(
|
||||
.A(prog_clk_3_S_in),
|
||||
.X(prog_clk_3_N_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_3_S_FTB01
|
||||
(
|
||||
.A(prog_clk_3_S_in),
|
||||
.X(prog_clk_3_S_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
clk_2_S_FTB01
|
||||
(
|
||||
.A(clk_2_N_in),
|
||||
.X(clk_2_S_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
clk_2_N_FTB01
|
||||
(
|
||||
.A(clk_2_N_in),
|
||||
.X(clk_2_N_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
clk_3_N_FTB01
|
||||
(
|
||||
.A(clk_3_S_in),
|
||||
.X(clk_3_N_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
clk_3_S_FTB01
|
||||
(
|
||||
.A(clk_3_S_in),
|
||||
.X(clk_3_S_out)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,563 @@
|
|||
|
||||
|
||||
module cby_2__1_
|
||||
( pReset, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, right_grid_pin_0_, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail, IO_ISOL_N, gfpga_pad_EMBEDDED_IO_HD_SOC_IN, gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, left_width_0_height_0__pin_0_, left_width_0_height_0__pin_1_upper, left_width_0_height_0__pin_1_lower, pReset_S_in, prog_clk_0_W_in, prog_clk_0_S_out, prog_clk_0_N_out );
|
||||
input [0:0] pReset;
|
||||
input [0:29] chany_bottom_in;
|
||||
input [0:29] chany_top_in;
|
||||
input [0:0] ccff_head;
|
||||
output [0:29] chany_bottom_out;
|
||||
output [0:29] chany_top_out;
|
||||
output [0:0] right_grid_pin_0_;
|
||||
output [0:0] left_grid_pin_16_;
|
||||
output [0:0] left_grid_pin_17_;
|
||||
output [0:0] left_grid_pin_18_;
|
||||
output [0:0] left_grid_pin_19_;
|
||||
output [0:0] left_grid_pin_20_;
|
||||
output [0:0] left_grid_pin_21_;
|
||||
output [0:0] left_grid_pin_22_;
|
||||
output [0:0] left_grid_pin_23_;
|
||||
output [0:0] left_grid_pin_24_;
|
||||
output [0:0] left_grid_pin_25_;
|
||||
output [0:0] left_grid_pin_26_;
|
||||
output [0:0] left_grid_pin_27_;
|
||||
output [0:0] left_grid_pin_28_;
|
||||
output [0:0] left_grid_pin_29_;
|
||||
output [0:0] left_grid_pin_30_;
|
||||
output [0:0] left_grid_pin_31_;
|
||||
output [0:0] ccff_tail;
|
||||
input [0:0] IO_ISOL_N;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
|
||||
input [0:0] left_width_0_height_0__pin_0_;
|
||||
output [0:0] left_width_0_height_0__pin_1_upper;
|
||||
output [0:0] left_width_0_height_0__pin_1_lower;
|
||||
input pReset_S_in;
|
||||
input prog_clk_0_W_in;
|
||||
output prog_clk_0_S_out;
|
||||
output prog_clk_0_N_out;
|
||||
|
||||
wire [0:3] mux_2level_size10_0_sram;
|
||||
wire [0:3] mux_2level_size10_1_sram;
|
||||
wire [0:3] mux_2level_size10_2_sram;
|
||||
wire [0:3] mux_2level_size10_3_sram;
|
||||
wire [0:3] mux_2level_size10_4_sram;
|
||||
wire [0:3] mux_2level_size10_5_sram;
|
||||
wire [0:3] mux_2level_size10_6_sram;
|
||||
wire [0:3] mux_2level_size10_7_sram;
|
||||
wire [0:0] mux_2level_size10_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_2_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_3_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_4_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_5_ccff_tail;
|
||||
wire [0:0] mux_2level_size10_mem_6_ccff_tail;
|
||||
wire [0:3] mux_2level_size12_0_sram;
|
||||
wire [0:3] mux_2level_size12_1_sram;
|
||||
wire [0:3] mux_2level_size12_2_sram;
|
||||
wire [0:3] mux_2level_size12_3_sram;
|
||||
wire [0:3] mux_2level_size12_4_sram;
|
||||
wire [0:3] mux_2level_size12_5_sram;
|
||||
wire [0:3] mux_2level_size12_6_sram;
|
||||
wire [0:3] mux_2level_size12_7_sram;
|
||||
wire [0:3] mux_2level_size12_8_sram;
|
||||
wire [0:0] mux_2level_size12_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_2_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_3_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_4_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_5_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_6_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_7_ccff_tail;
|
||||
wire [0:0] mux_2level_size12_mem_8_ccff_tail;
|
||||
wire [0:3] mux_left_ipin_0_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_10_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_11_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_12_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_13_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_14_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_15_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_1_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_2_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_3_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_4_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_5_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_6_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_7_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_8_undriven_sram_inv;
|
||||
wire [0:3] mux_right_ipin_9_undriven_sram_inv;
|
||||
wire ccff_tail_mid;
|
||||
wire prog_clk_0;
|
||||
wire [0:0] prog_clk;
|
||||
assign chany_top_out[0] = chany_bottom_in[0];
|
||||
assign chany_top_out[1] = chany_bottom_in[1];
|
||||
assign chany_top_out[2] = chany_bottom_in[2];
|
||||
assign chany_top_out[3] = chany_bottom_in[3];
|
||||
assign chany_top_out[4] = chany_bottom_in[4];
|
||||
assign chany_top_out[5] = chany_bottom_in[5];
|
||||
assign chany_top_out[6] = chany_bottom_in[6];
|
||||
assign chany_top_out[7] = chany_bottom_in[7];
|
||||
assign chany_top_out[8] = chany_bottom_in[8];
|
||||
assign chany_top_out[9] = chany_bottom_in[9];
|
||||
assign chany_top_out[10] = chany_bottom_in[10];
|
||||
assign chany_top_out[11] = chany_bottom_in[11];
|
||||
assign chany_top_out[12] = chany_bottom_in[12];
|
||||
assign chany_top_out[13] = chany_bottom_in[13];
|
||||
assign chany_top_out[14] = chany_bottom_in[14];
|
||||
assign chany_top_out[15] = chany_bottom_in[15];
|
||||
assign chany_top_out[16] = chany_bottom_in[16];
|
||||
assign chany_top_out[17] = chany_bottom_in[17];
|
||||
assign chany_top_out[18] = chany_bottom_in[18];
|
||||
assign chany_top_out[19] = chany_bottom_in[19];
|
||||
assign chany_top_out[20] = chany_bottom_in[20];
|
||||
assign chany_top_out[21] = chany_bottom_in[21];
|
||||
assign chany_top_out[22] = chany_bottom_in[22];
|
||||
assign chany_top_out[23] = chany_bottom_in[23];
|
||||
assign chany_top_out[24] = chany_bottom_in[24];
|
||||
assign chany_top_out[25] = chany_bottom_in[25];
|
||||
assign chany_top_out[26] = chany_bottom_in[26];
|
||||
assign chany_top_out[27] = chany_bottom_in[27];
|
||||
assign chany_top_out[28] = chany_bottom_in[28];
|
||||
assign chany_top_out[29] = chany_bottom_in[29];
|
||||
assign chany_bottom_out[0] = chany_top_in[0];
|
||||
assign chany_bottom_out[1] = chany_top_in[1];
|
||||
assign chany_bottom_out[2] = chany_top_in[2];
|
||||
assign chany_bottom_out[3] = chany_top_in[3];
|
||||
assign chany_bottom_out[4] = chany_top_in[4];
|
||||
assign chany_bottom_out[5] = chany_top_in[5];
|
||||
assign chany_bottom_out[6] = chany_top_in[6];
|
||||
assign chany_bottom_out[7] = chany_top_in[7];
|
||||
assign chany_bottom_out[8] = chany_top_in[8];
|
||||
assign chany_bottom_out[9] = chany_top_in[9];
|
||||
assign chany_bottom_out[10] = chany_top_in[10];
|
||||
assign chany_bottom_out[11] = chany_top_in[11];
|
||||
assign chany_bottom_out[12] = chany_top_in[12];
|
||||
assign chany_bottom_out[13] = chany_top_in[13];
|
||||
assign chany_bottom_out[14] = chany_top_in[14];
|
||||
assign chany_bottom_out[15] = chany_top_in[15];
|
||||
assign chany_bottom_out[16] = chany_top_in[16];
|
||||
assign chany_bottom_out[17] = chany_top_in[17];
|
||||
assign chany_bottom_out[18] = chany_top_in[18];
|
||||
assign chany_bottom_out[19] = chany_top_in[19];
|
||||
assign chany_bottom_out[20] = chany_top_in[20];
|
||||
assign chany_bottom_out[21] = chany_top_in[21];
|
||||
assign chany_bottom_out[22] = chany_top_in[22];
|
||||
assign chany_bottom_out[23] = chany_top_in[23];
|
||||
assign chany_bottom_out[24] = chany_top_in[24];
|
||||
assign chany_bottom_out[25] = chany_top_in[25];
|
||||
assign chany_bottom_out[26] = chany_top_in[26];
|
||||
assign chany_bottom_out[27] = chany_top_in[27];
|
||||
assign chany_bottom_out[28] = chany_top_in[28];
|
||||
assign chany_bottom_out[29] = chany_top_in[29];
|
||||
assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0];
|
||||
assign prog_clk_0 = prog_clk;
|
||||
|
||||
mux_2level_size12
|
||||
mux_left_ipin_0
|
||||
(
|
||||
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[24], chany_top_in[24] }),
|
||||
.sram(mux_2level_size12_0_sram[0:3]),
|
||||
.sram_inv(mux_left_ipin_0_undriven_sram_inv[0:3]),
|
||||
.out(right_grid_pin_0_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_0
|
||||
(
|
||||
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25] }),
|
||||
.sram(mux_2level_size12_1_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_16_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_2
|
||||
(
|
||||
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27] }),
|
||||
.sram(mux_2level_size12_2_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_18_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_4
|
||||
(
|
||||
.in({ chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[23], chany_top_in[23], chany_bottom_in[29], chany_top_in[29] }),
|
||||
.sram(mux_2level_size12_3_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_20_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_6
|
||||
(
|
||||
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25] }),
|
||||
.sram(mux_2level_size12_4_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_22_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_8
|
||||
(
|
||||
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27] }),
|
||||
.sram(mux_2level_size12_5_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_24_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_10
|
||||
(
|
||||
.in({ chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[23], chany_top_in[23], chany_bottom_in[29], chany_top_in[29] }),
|
||||
.sram(mux_2level_size12_6_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_26_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_12
|
||||
(
|
||||
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[25], chany_top_in[25] }),
|
||||
.sram(mux_2level_size12_7_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_28_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12
|
||||
mux_right_ipin_14
|
||||
(
|
||||
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[21], chany_top_in[21], chany_bottom_in[27], chany_top_in[27] }),
|
||||
.sram(mux_2level_size12_8_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_30_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_left_ipin_0
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_0_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_0
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_1_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_2
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_2_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_4
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_3_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_6
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_4_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_8
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_5_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_10
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_6_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_12
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_7_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_7_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size12_mem
|
||||
mem_right_ipin_14
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size10_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size12_mem_8_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size12_8_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_1
|
||||
(
|
||||
.in({ chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[17], chany_top_in[17], chany_bottom_in[26], chany_top_in[26] }),
|
||||
.sram(mux_2level_size10_0_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_17_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_3
|
||||
(
|
||||
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[19], chany_top_in[19], chany_bottom_in[28], chany_top_in[28] }),
|
||||
.sram(mux_2level_size10_1_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_19_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_5
|
||||
(
|
||||
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[21], chany_top_in[21] }),
|
||||
.sram(mux_2level_size10_2_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_21_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_7
|
||||
(
|
||||
.in({ chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[23], chany_top_in[23] }),
|
||||
.sram(mux_2level_size10_3_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_23_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_9
|
||||
(
|
||||
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[25], chany_top_in[25] }),
|
||||
.sram(mux_2level_size10_4_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_25_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_11
|
||||
(
|
||||
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18], chany_bottom_in[27], chany_top_in[27] }),
|
||||
.sram(mux_2level_size10_5_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_27_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_13
|
||||
(
|
||||
.in({ chany_bottom_in[2], chany_top_in[2], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[14], chany_top_in[14], chany_bottom_in[20], chany_top_in[20], chany_bottom_in[29], chany_top_in[29] }),
|
||||
.sram(mux_2level_size10_6_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_29_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10
|
||||
mux_right_ipin_15
|
||||
(
|
||||
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[16], chany_top_in[16], chany_bottom_in[22], chany_top_in[22] }),
|
||||
.sram(mux_2level_size10_7_sram[0:3]),
|
||||
.sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]),
|
||||
.out(left_grid_pin_31_[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_1
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_0_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_3
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_1_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_5
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_2_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_7
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_3_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_9
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_4_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_11
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_5_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_13
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_7_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_size10_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_2level_size10_6_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_size10_mem
|
||||
mem_right_ipin_15
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_size12_mem_8_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.mem_out(mux_2level_size10_7_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
logical_tile_io_mode_io_
|
||||
logical_tile_io_mode_io__0
|
||||
(
|
||||
.IO_ISOL_N(IO_ISOL_N[0]),
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
|
||||
.io_outpad(left_width_0_height_0__pin_0_[0]),
|
||||
.ccff_head(ccff_tail_mid),
|
||||
.io_inpad(left_width_0_height_0__pin_1_upper[0]),
|
||||
.ccff_tail(ccff_tail[0])
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
pReset_FTB00
|
||||
(
|
||||
.A(pReset_S_in),
|
||||
.X(pReset)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
prog_clk_0_FTB00
|
||||
(
|
||||
.A(prog_clk_0_W_in),
|
||||
.X(prog_clk_0)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_0_S_FTB01
|
||||
(
|
||||
.A(prog_clk_0_W_in),
|
||||
.X(prog_clk_0_S_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
prog_clk_0_N_FTB01
|
||||
(
|
||||
.A(prog_clk_0_W_in),
|
||||
.X(prog_clk_0_N_out)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,910 @@
|
|||
|
||||
|
||||
module sb_0__0_
|
||||
( pReset, chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, right_bottom_grid_pin_13_, right_bottom_grid_pin_15_, right_bottom_grid_pin_17_, ccff_head, chany_top_out, chanx_right_out, ccff_tail, pReset_E_in, prog_clk_0_E_in );
|
||||
input [0:0] pReset;
|
||||
input [0:29] chany_top_in;
|
||||
input [0:0] top_left_grid_pin_1_;
|
||||
input [0:29] chanx_right_in;
|
||||
input [0:0] right_bottom_grid_pin_1_;
|
||||
input [0:0] right_bottom_grid_pin_3_;
|
||||
input [0:0] right_bottom_grid_pin_5_;
|
||||
input [0:0] right_bottom_grid_pin_7_;
|
||||
input [0:0] right_bottom_grid_pin_9_;
|
||||
input [0:0] right_bottom_grid_pin_11_;
|
||||
input [0:0] right_bottom_grid_pin_13_;
|
||||
input [0:0] right_bottom_grid_pin_15_;
|
||||
input [0:0] right_bottom_grid_pin_17_;
|
||||
input [0:0] ccff_head;
|
||||
output [0:29] chany_top_out;
|
||||
output [0:29] chanx_right_out;
|
||||
output [0:0] ccff_tail;
|
||||
input pReset_E_in;
|
||||
input prog_clk_0_E_in;
|
||||
|
||||
wire [0:1] mux_2level_tapbuf_size2_0_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_10_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_11_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_12_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_13_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_14_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_15_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_16_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_17_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_18_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_19_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_1_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_20_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_21_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_22_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_23_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_24_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_25_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_2_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_3_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_4_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_5_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_6_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_7_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_8_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_9_sram;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_10_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_11_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_12_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_13_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_14_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_15_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_16_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_17_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_18_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_19_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_20_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_21_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_22_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_23_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_24_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_6_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_7_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_8_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_9_ccff_tail;
|
||||
wire [0:1] mux_2level_tapbuf_size3_0_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size3_1_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size3_2_sram;
|
||||
wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size3_mem_2_ccff_tail;
|
||||
wire [0:3] mux_2level_tapbuf_size4_0_sram;
|
||||
wire [0:3] mux_2level_tapbuf_size4_1_sram;
|
||||
wire [0:3] mux_2level_tapbuf_size4_2_sram;
|
||||
wire [0:3] mux_2level_tapbuf_size4_3_sram;
|
||||
wire [0:3] mux_2level_tapbuf_size4_4_sram;
|
||||
wire [0:3] mux_2level_tapbuf_size4_5_sram;
|
||||
wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail;
|
||||
wire [0:3] mux_right_track_0_undriven_sram_inv;
|
||||
wire [0:3] mux_right_track_10_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_12_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_14_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_16_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_18_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_20_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_22_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_24_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_26_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_28_undriven_sram_inv;
|
||||
wire [0:3] mux_right_track_2_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_30_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_32_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_34_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_36_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_38_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_40_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_42_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_44_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_46_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_48_undriven_sram_inv;
|
||||
wire [0:3] mux_right_track_4_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_50_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_52_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_54_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_56_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_58_undriven_sram_inv;
|
||||
wire [0:3] mux_right_track_6_undriven_sram_inv;
|
||||
wire [0:3] mux_right_track_8_undriven_sram_inv;
|
||||
wire [0:1] mux_top_track_0_undriven_sram_inv;
|
||||
wire [0:1] mux_top_track_12_undriven_sram_inv;
|
||||
wire [0:1] mux_top_track_28_undriven_sram_inv;
|
||||
wire [0:1] mux_top_track_44_undriven_sram_inv;
|
||||
wire [0:1] mux_top_track_6_undriven_sram_inv;
|
||||
wire prog_clk_0;
|
||||
wire [0:0] prog_clk;
|
||||
assign chany_top_out[29] = chanx_right_in[0];
|
||||
assign chany_top_out[1] = chanx_right_in[2];
|
||||
assign chany_top_out[2] = chanx_right_in[3];
|
||||
assign chany_top_out[4] = chanx_right_in[5];
|
||||
assign chany_top_out[5] = chanx_right_in[6];
|
||||
assign chany_top_out[7] = chanx_right_in[8];
|
||||
assign chany_top_out[8] = chanx_right_in[9];
|
||||
assign chany_top_out[9] = chanx_right_in[10];
|
||||
assign chany_top_out[10] = chanx_right_in[11];
|
||||
assign chany_top_out[11] = chanx_right_in[12];
|
||||
assign chany_top_out[12] = chanx_right_in[13];
|
||||
assign chany_top_out[13] = chanx_right_in[14];
|
||||
assign chany_top_out[15] = chanx_right_in[16];
|
||||
assign chany_top_out[16] = chanx_right_in[17];
|
||||
assign chany_top_out[17] = chanx_right_in[18];
|
||||
assign chany_top_out[18] = chanx_right_in[19];
|
||||
assign chany_top_out[19] = chanx_right_in[20];
|
||||
assign chany_top_out[20] = chanx_right_in[21];
|
||||
assign chany_top_out[21] = chanx_right_in[22];
|
||||
assign chany_top_out[23] = chanx_right_in[24];
|
||||
assign chany_top_out[24] = chanx_right_in[25];
|
||||
assign chany_top_out[25] = chanx_right_in[26];
|
||||
assign chany_top_out[26] = chanx_right_in[27];
|
||||
assign chany_top_out[27] = chanx_right_in[28];
|
||||
assign chany_top_out[28] = chanx_right_in[29];
|
||||
assign prog_clk_0 = prog_clk;
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_top_track_0
|
||||
(
|
||||
.in({ top_left_grid_pin_1_[0], chanx_right_in[1] }),
|
||||
.sram(mux_2level_tapbuf_size2_0_sram[0:1]),
|
||||
.sram_inv(mux_top_track_0_undriven_sram_inv[0:1]),
|
||||
.out(chany_top_out[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_top_track_6
|
||||
(
|
||||
.in({ top_left_grid_pin_1_[0], chanx_right_in[4] }),
|
||||
.sram(mux_2level_tapbuf_size2_1_sram[0:1]),
|
||||
.sram_inv(mux_top_track_6_undriven_sram_inv[0:1]),
|
||||
.out(chany_top_out[3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_top_track_12
|
||||
(
|
||||
.in({ top_left_grid_pin_1_[0], chanx_right_in[7] }),
|
||||
.sram(mux_2level_tapbuf_size2_2_sram[0:1]),
|
||||
.sram_inv(mux_top_track_12_undriven_sram_inv[0:1]),
|
||||
.out(chany_top_out[6])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_top_track_28
|
||||
(
|
||||
.in({ top_left_grid_pin_1_[0], chanx_right_in[15] }),
|
||||
.sram(mux_2level_tapbuf_size2_3_sram[0:1]),
|
||||
.sram_inv(mux_top_track_28_undriven_sram_inv[0:1]),
|
||||
.out(chany_top_out[14])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_top_track_44
|
||||
(
|
||||
.in({ top_left_grid_pin_1_[0], chanx_right_in[23] }),
|
||||
.sram(mux_2level_tapbuf_size2_4_sram[0:1]),
|
||||
.sram_inv(mux_top_track_44_undriven_sram_inv[0:1]),
|
||||
.out(chany_top_out[22])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_14
|
||||
(
|
||||
.in({ chany_top_in[6], right_bottom_grid_pin_3_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_5_sram[0:1]),
|
||||
.sram_inv(mux_right_track_14_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[7])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_16
|
||||
(
|
||||
.in({ chany_top_in[7], right_bottom_grid_pin_5_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_6_sram[0:1]),
|
||||
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[8])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_18
|
||||
(
|
||||
.in({ chany_top_in[8], right_bottom_grid_pin_7_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_7_sram[0:1]),
|
||||
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[9])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_20
|
||||
(
|
||||
.in({ chany_top_in[9], right_bottom_grid_pin_9_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_8_sram[0:1]),
|
||||
.sram_inv(mux_right_track_20_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[10])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_22
|
||||
(
|
||||
.in({ chany_top_in[10], right_bottom_grid_pin_11_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_9_sram[0:1]),
|
||||
.sram_inv(mux_right_track_22_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[11])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_24
|
||||
(
|
||||
.in({ chany_top_in[11], right_bottom_grid_pin_13_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_10_sram[0:1]),
|
||||
.sram_inv(mux_right_track_24_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[12])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_26
|
||||
(
|
||||
.in({ chany_top_in[12], right_bottom_grid_pin_15_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_11_sram[0:1]),
|
||||
.sram_inv(mux_right_track_26_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[13])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_30
|
||||
(
|
||||
.in({ chany_top_in[14], right_bottom_grid_pin_3_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_12_sram[0:1]),
|
||||
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[15])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_32
|
||||
(
|
||||
.in({ chany_top_in[15], right_bottom_grid_pin_5_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_13_sram[0:1]),
|
||||
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[16])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_34
|
||||
(
|
||||
.in({ chany_top_in[16], right_bottom_grid_pin_7_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_14_sram[0:1]),
|
||||
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[17])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_36
|
||||
(
|
||||
.in({ chany_top_in[17], right_bottom_grid_pin_9_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_15_sram[0:1]),
|
||||
.sram_inv(mux_right_track_36_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[18])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_38
|
||||
(
|
||||
.in({ chany_top_in[18], right_bottom_grid_pin_11_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_16_sram[0:1]),
|
||||
.sram_inv(mux_right_track_38_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[19])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_40
|
||||
(
|
||||
.in({ chany_top_in[19], right_bottom_grid_pin_13_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_17_sram[0:1]),
|
||||
.sram_inv(mux_right_track_40_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[20])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_42
|
||||
(
|
||||
.in({ chany_top_in[20], right_bottom_grid_pin_15_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_18_sram[0:1]),
|
||||
.sram_inv(mux_right_track_42_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[21])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_46
|
||||
(
|
||||
.in({ chany_top_in[22], right_bottom_grid_pin_3_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_19_sram[0:1]),
|
||||
.sram_inv(mux_right_track_46_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[23])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_48
|
||||
(
|
||||
.in({ chany_top_in[23], right_bottom_grid_pin_5_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_20_sram[0:1]),
|
||||
.sram_inv(mux_right_track_48_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[24])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_50
|
||||
(
|
||||
.in({ chany_top_in[24], right_bottom_grid_pin_7_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_21_sram[0:1]),
|
||||
.sram_inv(mux_right_track_50_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[25])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_52
|
||||
(
|
||||
.in({ chany_top_in[25], right_bottom_grid_pin_9_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_22_sram[0:1]),
|
||||
.sram_inv(mux_right_track_52_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[26])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_54
|
||||
(
|
||||
.in({ chany_top_in[26], right_bottom_grid_pin_11_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_23_sram[0:1]),
|
||||
.sram_inv(mux_right_track_54_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[27])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_56
|
||||
(
|
||||
.in({ chany_top_in[27], right_bottom_grid_pin_13_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_24_sram[0:1]),
|
||||
.sram_inv(mux_right_track_56_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[28])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_58
|
||||
(
|
||||
.in({ chany_top_in[28], right_bottom_grid_pin_15_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_25_sram[0:1]),
|
||||
.sram_inv(mux_right_track_58_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[29])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_top_track_0
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_0_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_top_track_6
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_1_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_top_track_12
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_2_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_top_track_28
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_3_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_top_track_44
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_4_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_14
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size3_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_5_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_16
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_6_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_18
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_7_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_7_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_20
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_7_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_8_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_8_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_22
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_8_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_9_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_9_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_24
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_9_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_10_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_10_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_26
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_10_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_11_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_11_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_30
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size3_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_12_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_12_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_32
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_12_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_13_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_13_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_34
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_13_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_14_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_14_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_36
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_14_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_15_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_15_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_38
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_15_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_16_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_16_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_40
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_16_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_17_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_17_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_42
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_17_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_18_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_18_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_46
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size3_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_19_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_19_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_48
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_19_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_20_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_20_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_50
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_20_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_21_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_21_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_52
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_21_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_22_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_22_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_54
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_22_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_23_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_23_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_56
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_23_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_24_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_24_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_58
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_24_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_25_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4
|
||||
mux_right_track_0
|
||||
(
|
||||
.in({ chany_top_in[29], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_13_[0] }),
|
||||
.sram(mux_2level_tapbuf_size4_0_sram[0:3]),
|
||||
.sram_inv(mux_right_track_0_undriven_sram_inv[0:3]),
|
||||
.out(chanx_right_out[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4
|
||||
mux_right_track_2
|
||||
(
|
||||
.in({ chany_top_in[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_15_[0] }),
|
||||
.sram(mux_2level_tapbuf_size4_1_sram[0:3]),
|
||||
.sram_inv(mux_right_track_2_undriven_sram_inv[0:3]),
|
||||
.out(chanx_right_out[1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4
|
||||
mux_right_track_4
|
||||
(
|
||||
.in({ chany_top_in[1], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_11_[0], right_bottom_grid_pin_17_[0] }),
|
||||
.sram(mux_2level_tapbuf_size4_2_sram[0:3]),
|
||||
.sram_inv(mux_right_track_4_undriven_sram_inv[0:3]),
|
||||
.out(chanx_right_out[2])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4
|
||||
mux_right_track_6
|
||||
(
|
||||
.in({ chany_top_in[2], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_13_[0] }),
|
||||
.sram(mux_2level_tapbuf_size4_3_sram[0:3]),
|
||||
.sram_inv(mux_right_track_6_undriven_sram_inv[0:3]),
|
||||
.out(chanx_right_out[3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4
|
||||
mux_right_track_8
|
||||
(
|
||||
.in({ chany_top_in[3], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_15_[0] }),
|
||||
.sram(mux_2level_tapbuf_size4_4_sram[0:3]),
|
||||
.sram_inv(mux_right_track_8_undriven_sram_inv[0:3]),
|
||||
.out(chanx_right_out[4])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4
|
||||
mux_right_track_10
|
||||
(
|
||||
.in({ chany_top_in[4], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_11_[0], right_bottom_grid_pin_17_[0] }),
|
||||
.sram(mux_2level_tapbuf_size4_5_sram[0:3]),
|
||||
.sram_inv(mux_right_track_10_undriven_sram_inv[0:3]),
|
||||
.out(chanx_right_out[5])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4_mem
|
||||
mem_right_track_0
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size4_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size4_0_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4_mem
|
||||
mem_right_track_2
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size4_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size4_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size4_1_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4_mem
|
||||
mem_right_track_4
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size4_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size4_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size4_2_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4_mem
|
||||
mem_right_track_6
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size4_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size4_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size4_3_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4_mem
|
||||
mem_right_track_8
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size4_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size4_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size4_4_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4_mem
|
||||
mem_right_track_10
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size4_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size4_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size4_5_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size3
|
||||
mux_right_track_12
|
||||
(
|
||||
.in({ chany_top_in[5], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_17_[0] }),
|
||||
.sram(mux_2level_tapbuf_size3_0_sram[0:1]),
|
||||
.sram_inv(mux_right_track_12_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[6])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size3
|
||||
mux_right_track_28
|
||||
(
|
||||
.in({ chany_top_in[13], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_17_[0] }),
|
||||
.sram(mux_2level_tapbuf_size3_1_sram[0:1]),
|
||||
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[14])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size3
|
||||
mux_right_track_44
|
||||
(
|
||||
.in({ chany_top_in[21], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_17_[0] }),
|
||||
.sram(mux_2level_tapbuf_size3_2_sram[0:1]),
|
||||
.sram_inv(mux_right_track_44_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[22])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size3_mem
|
||||
mem_right_track_12
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size4_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size3_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size3_0_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size3_mem
|
||||
mem_right_track_28
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_11_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size3_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size3_1_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size3_mem
|
||||
mem_right_track_44
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_18_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size3_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size3_2_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
pReset_FTB00
|
||||
(
|
||||
.A(pReset_E_in),
|
||||
.X(pReset)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
prog_clk_0_FTB00
|
||||
(
|
||||
.A(prog_clk_0_E_in),
|
||||
.X(prog_clk_0)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,922 @@
|
|||
|
||||
|
||||
module sb_0__2_
|
||||
( pReset, chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, right_bottom_grid_pin_42_, right_bottom_grid_pin_43_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chanx_right_out, chany_bottom_out, ccff_tail, SC_IN_TOP, SC_OUT_BOT, pReset_E_in, pReset_S_out, prog_clk_0_E_in );
|
||||
input [0:0] pReset;
|
||||
input [0:29] chanx_right_in;
|
||||
input [0:0] right_top_grid_pin_1_;
|
||||
input [0:0] right_bottom_grid_pin_36_;
|
||||
input [0:0] right_bottom_grid_pin_37_;
|
||||
input [0:0] right_bottom_grid_pin_38_;
|
||||
input [0:0] right_bottom_grid_pin_39_;
|
||||
input [0:0] right_bottom_grid_pin_40_;
|
||||
input [0:0] right_bottom_grid_pin_41_;
|
||||
input [0:0] right_bottom_grid_pin_42_;
|
||||
input [0:0] right_bottom_grid_pin_43_;
|
||||
input [0:29] chany_bottom_in;
|
||||
input [0:0] bottom_left_grid_pin_1_;
|
||||
input [0:0] ccff_head;
|
||||
output [0:29] chanx_right_out;
|
||||
output [0:29] chany_bottom_out;
|
||||
output [0:0] ccff_tail;
|
||||
input SC_IN_TOP;
|
||||
output SC_OUT_BOT;
|
||||
input pReset_E_in;
|
||||
output pReset_S_out;
|
||||
input prog_clk_0_E_in;
|
||||
|
||||
wire [0:1] mux_2level_tapbuf_size2_0_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_10_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_11_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_12_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_13_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_14_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_15_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_16_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_17_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_18_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_19_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_1_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_20_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_21_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_22_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_23_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_24_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_25_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_26_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_2_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_3_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_4_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_5_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_6_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_7_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_8_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size2_9_sram;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_10_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_11_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_12_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_13_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_14_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_15_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_16_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_17_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_18_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_19_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_20_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_21_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_22_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_23_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_24_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_25_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_6_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_7_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_8_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size2_mem_9_ccff_tail;
|
||||
wire [0:1] mux_2level_tapbuf_size3_0_sram;
|
||||
wire [0:1] mux_2level_tapbuf_size3_1_sram;
|
||||
wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail;
|
||||
wire [0:3] mux_2level_tapbuf_size4_0_sram;
|
||||
wire [0:3] mux_2level_tapbuf_size4_1_sram;
|
||||
wire [0:3] mux_2level_tapbuf_size4_2_sram;
|
||||
wire [0:3] mux_2level_tapbuf_size4_3_sram;
|
||||
wire [0:3] mux_2level_tapbuf_size4_4_sram;
|
||||
wire [0:3] mux_2level_tapbuf_size4_5_sram;
|
||||
wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail;
|
||||
wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail;
|
||||
wire [0:1] mux_bottom_track_13_undriven_sram_inv;
|
||||
wire [0:1] mux_bottom_track_1_undriven_sram_inv;
|
||||
wire [0:1] mux_bottom_track_29_undriven_sram_inv;
|
||||
wire [0:1] mux_bottom_track_45_undriven_sram_inv;
|
||||
wire [0:1] mux_bottom_track_7_undriven_sram_inv;
|
||||
wire [0:3] mux_right_track_0_undriven_sram_inv;
|
||||
wire [0:3] mux_right_track_10_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_12_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_14_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_16_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_18_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_20_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_22_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_24_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_26_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_28_undriven_sram_inv;
|
||||
wire [0:3] mux_right_track_2_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_30_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_32_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_34_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_36_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_38_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_40_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_42_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_44_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_46_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_48_undriven_sram_inv;
|
||||
wire [0:3] mux_right_track_4_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_50_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_52_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_54_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_56_undriven_sram_inv;
|
||||
wire [0:1] mux_right_track_58_undriven_sram_inv;
|
||||
wire [0:3] mux_right_track_6_undriven_sram_inv;
|
||||
wire [0:3] mux_right_track_8_undriven_sram_inv;
|
||||
wire prog_clk_0;
|
||||
wire [0:0] prog_clk;
|
||||
assign chany_bottom_out[28] = chanx_right_in[0];
|
||||
assign chany_bottom_out[27] = chanx_right_in[1];
|
||||
assign chany_bottom_out[26] = chanx_right_in[2];
|
||||
assign chany_bottom_out[25] = chanx_right_in[3];
|
||||
assign chany_bottom_out[24] = chanx_right_in[4];
|
||||
assign chany_bottom_out[23] = chanx_right_in[5];
|
||||
assign chany_bottom_out[21] = chanx_right_in[7];
|
||||
assign chany_bottom_out[20] = chanx_right_in[8];
|
||||
assign chany_bottom_out[19] = chanx_right_in[9];
|
||||
assign chany_bottom_out[18] = chanx_right_in[10];
|
||||
assign chany_bottom_out[17] = chanx_right_in[11];
|
||||
assign chany_bottom_out[16] = chanx_right_in[12];
|
||||
assign chany_bottom_out[15] = chanx_right_in[13];
|
||||
assign chany_bottom_out[13] = chanx_right_in[15];
|
||||
assign chany_bottom_out[12] = chanx_right_in[16];
|
||||
assign chany_bottom_out[11] = chanx_right_in[17];
|
||||
assign chany_bottom_out[10] = chanx_right_in[18];
|
||||
assign chany_bottom_out[9] = chanx_right_in[19];
|
||||
assign chany_bottom_out[8] = chanx_right_in[20];
|
||||
assign chany_bottom_out[7] = chanx_right_in[21];
|
||||
assign chany_bottom_out[5] = chanx_right_in[23];
|
||||
assign chany_bottom_out[4] = chanx_right_in[24];
|
||||
assign chany_bottom_out[2] = chanx_right_in[26];
|
||||
assign chany_bottom_out[1] = chanx_right_in[27];
|
||||
assign chany_bottom_out[29] = chanx_right_in[29];
|
||||
assign SC_OUT_BOT = SC_IN_TOP;
|
||||
assign prog_clk_0 = prog_clk;
|
||||
|
||||
mux_2level_tapbuf_size4
|
||||
mux_right_track_0
|
||||
(
|
||||
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[28] }),
|
||||
.sram(mux_2level_tapbuf_size4_0_sram[0:3]),
|
||||
.sram_inv(mux_right_track_0_undriven_sram_inv[0:3]),
|
||||
.out(chanx_right_out[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4
|
||||
mux_right_track_2
|
||||
(
|
||||
.in({ right_bottom_grid_pin_36_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_42_[0], chany_bottom_in[27] }),
|
||||
.sram(mux_2level_tapbuf_size4_1_sram[0:3]),
|
||||
.sram_inv(mux_right_track_2_undriven_sram_inv[0:3]),
|
||||
.out(chanx_right_out[1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4
|
||||
mux_right_track_4
|
||||
(
|
||||
.in({ right_bottom_grid_pin_37_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_43_[0], chany_bottom_in[26] }),
|
||||
.sram(mux_2level_tapbuf_size4_2_sram[0:3]),
|
||||
.sram_inv(mux_right_track_4_undriven_sram_inv[0:3]),
|
||||
.out(chanx_right_out[2])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4
|
||||
mux_right_track_6
|
||||
(
|
||||
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[25] }),
|
||||
.sram(mux_2level_tapbuf_size4_3_sram[0:3]),
|
||||
.sram_inv(mux_right_track_6_undriven_sram_inv[0:3]),
|
||||
.out(chanx_right_out[3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4
|
||||
mux_right_track_8
|
||||
(
|
||||
.in({ right_bottom_grid_pin_36_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_42_[0], chany_bottom_in[24] }),
|
||||
.sram(mux_2level_tapbuf_size4_4_sram[0:3]),
|
||||
.sram_inv(mux_right_track_8_undriven_sram_inv[0:3]),
|
||||
.out(chanx_right_out[4])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4
|
||||
mux_right_track_10
|
||||
(
|
||||
.in({ right_bottom_grid_pin_37_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_43_[0], chany_bottom_in[23] }),
|
||||
.sram(mux_2level_tapbuf_size4_5_sram[0:3]),
|
||||
.sram_inv(mux_right_track_10_undriven_sram_inv[0:3]),
|
||||
.out(chanx_right_out[5])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4_mem
|
||||
mem_right_track_0
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size4_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size4_0_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4_mem
|
||||
mem_right_track_2
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size4_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size4_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size4_1_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4_mem
|
||||
mem_right_track_4
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size4_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size4_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size4_2_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4_mem
|
||||
mem_right_track_6
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size4_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size4_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size4_3_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4_mem
|
||||
mem_right_track_8
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size4_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size4_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size4_4_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size4_mem
|
||||
mem_right_track_10
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size4_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size4_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size4_5_sram[0:3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_12
|
||||
(
|
||||
.in({ right_top_grid_pin_1_[0], chany_bottom_in[22] }),
|
||||
.sram(mux_2level_tapbuf_size2_0_sram[0:1]),
|
||||
.sram_inv(mux_right_track_12_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[6])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_14
|
||||
(
|
||||
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[21] }),
|
||||
.sram(mux_2level_tapbuf_size2_1_sram[0:1]),
|
||||
.sram_inv(mux_right_track_14_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[7])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_16
|
||||
(
|
||||
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[20] }),
|
||||
.sram(mux_2level_tapbuf_size2_2_sram[0:1]),
|
||||
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[8])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_18
|
||||
(
|
||||
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[19] }),
|
||||
.sram(mux_2level_tapbuf_size2_3_sram[0:1]),
|
||||
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[9])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_20
|
||||
(
|
||||
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[18] }),
|
||||
.sram(mux_2level_tapbuf_size2_4_sram[0:1]),
|
||||
.sram_inv(mux_right_track_20_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[10])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_22
|
||||
(
|
||||
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[17] }),
|
||||
.sram(mux_2level_tapbuf_size2_5_sram[0:1]),
|
||||
.sram_inv(mux_right_track_22_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[11])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_24
|
||||
(
|
||||
.in({ right_bottom_grid_pin_41_[0], chany_bottom_in[16] }),
|
||||
.sram(mux_2level_tapbuf_size2_6_sram[0:1]),
|
||||
.sram_inv(mux_right_track_24_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[12])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_26
|
||||
(
|
||||
.in({ right_bottom_grid_pin_42_[0], chany_bottom_in[15] }),
|
||||
.sram(mux_2level_tapbuf_size2_7_sram[0:1]),
|
||||
.sram_inv(mux_right_track_26_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[13])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_30
|
||||
(
|
||||
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[13] }),
|
||||
.sram(mux_2level_tapbuf_size2_8_sram[0:1]),
|
||||
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[15])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_32
|
||||
(
|
||||
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[12] }),
|
||||
.sram(mux_2level_tapbuf_size2_9_sram[0:1]),
|
||||
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[16])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_34
|
||||
(
|
||||
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[11] }),
|
||||
.sram(mux_2level_tapbuf_size2_10_sram[0:1]),
|
||||
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[17])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_36
|
||||
(
|
||||
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[10] }),
|
||||
.sram(mux_2level_tapbuf_size2_11_sram[0:1]),
|
||||
.sram_inv(mux_right_track_36_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[18])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_38
|
||||
(
|
||||
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[9] }),
|
||||
.sram(mux_2level_tapbuf_size2_12_sram[0:1]),
|
||||
.sram_inv(mux_right_track_38_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[19])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_40
|
||||
(
|
||||
.in({ right_bottom_grid_pin_41_[0], chany_bottom_in[8] }),
|
||||
.sram(mux_2level_tapbuf_size2_13_sram[0:1]),
|
||||
.sram_inv(mux_right_track_40_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[20])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_42
|
||||
(
|
||||
.in({ right_bottom_grid_pin_42_[0], chany_bottom_in[7] }),
|
||||
.sram(mux_2level_tapbuf_size2_14_sram[0:1]),
|
||||
.sram_inv(mux_right_track_42_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[21])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_44
|
||||
(
|
||||
.in({ right_top_grid_pin_1_[0], chany_bottom_in[6] }),
|
||||
.sram(mux_2level_tapbuf_size2_15_sram[0:1]),
|
||||
.sram_inv(mux_right_track_44_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[22])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_46
|
||||
(
|
||||
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[5] }),
|
||||
.sram(mux_2level_tapbuf_size2_16_sram[0:1]),
|
||||
.sram_inv(mux_right_track_46_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[23])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_48
|
||||
(
|
||||
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[4] }),
|
||||
.sram(mux_2level_tapbuf_size2_17_sram[0:1]),
|
||||
.sram_inv(mux_right_track_48_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[24])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_50
|
||||
(
|
||||
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[3] }),
|
||||
.sram(mux_2level_tapbuf_size2_18_sram[0:1]),
|
||||
.sram_inv(mux_right_track_50_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[25])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_54
|
||||
(
|
||||
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[1] }),
|
||||
.sram(mux_2level_tapbuf_size2_19_sram[0:1]),
|
||||
.sram_inv(mux_right_track_54_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[27])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_56
|
||||
(
|
||||
.in({ right_bottom_grid_pin_41_[0], chany_bottom_in[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_20_sram[0:1]),
|
||||
.sram_inv(mux_right_track_56_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[28])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_right_track_58
|
||||
(
|
||||
.in({ right_bottom_grid_pin_42_[0], chany_bottom_in[29] }),
|
||||
.sram(mux_2level_tapbuf_size2_21_sram[0:1]),
|
||||
.sram_inv(mux_right_track_58_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[29])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_bottom_track_1
|
||||
(
|
||||
.in({ chanx_right_in[28], bottom_left_grid_pin_1_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_22_sram[0:1]),
|
||||
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[0])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_bottom_track_7
|
||||
(
|
||||
.in({ chanx_right_in[25], bottom_left_grid_pin_1_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_23_sram[0:1]),
|
||||
.sram_inv(mux_bottom_track_7_undriven_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[3])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_bottom_track_13
|
||||
(
|
||||
.in({ chanx_right_in[22], bottom_left_grid_pin_1_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_24_sram[0:1]),
|
||||
.sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[6])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_bottom_track_29
|
||||
(
|
||||
.in({ chanx_right_in[14], bottom_left_grid_pin_1_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_25_sram[0:1]),
|
||||
.sram_inv(mux_bottom_track_29_undriven_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[14])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2
|
||||
mux_bottom_track_45
|
||||
(
|
||||
.in({ chanx_right_in[6], bottom_left_grid_pin_1_[0] }),
|
||||
.sram(mux_2level_tapbuf_size2_26_sram[0:1]),
|
||||
.sram_inv(mux_bottom_track_45_undriven_sram_inv[0:1]),
|
||||
.out(chany_bottom_out[22])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_12
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size4_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_0_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_14
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_1_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_16
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_2_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_18
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_3_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_20
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_4_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_22
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_5_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_24
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_6_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_26
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_7_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_7_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_30
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size3_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_8_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_8_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_32
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_8_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_9_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_9_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_34
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_9_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_10_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_10_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_36
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_10_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_11_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_11_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_38
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_11_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_12_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_12_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_40
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_12_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_13_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_13_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_42
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_13_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_14_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_14_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_44
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_14_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_15_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_15_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_46
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_15_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_16_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_16_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_48
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_16_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_17_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_17_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_50
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_17_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_18_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_18_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_54
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size3_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_19_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_19_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_56
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_19_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_20_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_20_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_right_track_58
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_20_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_21_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_21_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_bottom_track_1
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_21_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_22_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_22_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_bottom_track_7
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_22_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_23_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_23_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_bottom_track_13
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_23_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_24_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_24_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_bottom_track_29
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_24_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size2_mem_25_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_25_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size2_mem
|
||||
mem_bottom_track_45
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_25_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size2_26_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size3
|
||||
mux_right_track_28
|
||||
(
|
||||
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_43_[0], chany_bottom_in[14] }),
|
||||
.sram(mux_2level_tapbuf_size3_0_sram[0:1]),
|
||||
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[14])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size3
|
||||
mux_right_track_52
|
||||
(
|
||||
.in({ right_bottom_grid_pin_39_[0], right_bottom_grid_pin_43_[0], chany_bottom_in[2] }),
|
||||
.sram(mux_2level_tapbuf_size3_1_sram[0:1]),
|
||||
.sram_inv(mux_right_track_52_undriven_sram_inv[0:1]),
|
||||
.out(chanx_right_out[26])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size3_mem
|
||||
mem_right_track_28
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_7_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size3_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size3_0_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
mux_2level_tapbuf_size3_mem
|
||||
mem_right_track_52
|
||||
(
|
||||
.pReset(pReset[0]),
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_2level_tapbuf_size2_mem_18_ccff_tail[0]),
|
||||
.ccff_tail(mux_2level_tapbuf_size3_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_2level_tapbuf_size3_1_sram[0:1])
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
pReset_FTB00
|
||||
(
|
||||
.A(pReset_E_in),
|
||||
.X(pReset)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_4
|
||||
pReset_S_FTB01
|
||||
(
|
||||
.A(pReset_E_in),
|
||||
.X(pReset_S_out)
|
||||
);
|
||||
|
||||
|
||||
sky130_fd_sc_hd__buf_8
|
||||
prog_clk_0_FTB00
|
||||
(
|
||||
.A(prog_clk_0_E_in),
|
||||
.X(prog_clk_0)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,10 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
module decoder2to4 ( in, out );
|
||||
input [1:0] in;
|
||||
output [3:0] out;
|
||||
wire n3, n4;
|
||||
|
||||
sky130_fd_sc_hd__nor2_1 U9 ( .A(n3), .B(n4), .Y(out[3]) );
|
||||
sky130_fd_sc_hd__nor2_1 U10 ( .A(in[0]), .B(n4), .Y(out[2]) );
|
||||
sky130_fd_sc_hd__clkinv_1 U11 ( .A(in[1]), .Y(n4) );
|
||||
sky130_fd_sc_hd__nor2_1 U12 ( .A(in[1]), .B(n3), .Y(out[1]) );
|
||||
sky130_fd_sc_hd__clkinv_1 U13 ( .A(in[0]), .Y(n3) );
|
||||
sky130_fd_sc_hd__nor2_1 U14 ( .A(in[1]), .B(in[0]), .Y(out[0]) );
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
`timescale 1ns/1ps
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module EMBEDDED_IO_HD (
|
||||
input SOC_IN, //
|
||||
output SOC_OUT, //
|
||||
output SOC_DIR, //
|
||||
output FPGA_IN, //
|
||||
input FPGA_OUT, //
|
||||
input FPGA_DIR, //
|
||||
input IO_ISOL_N //
|
||||
);
|
||||
|
||||
wire SOC_DIR_N;
|
||||
|
||||
//
|
||||
sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (.B_N(IO_ISOL_N),
|
||||
.A(FPGA_DIR),
|
||||
.X(SOC_DIR)
|
||||
);
|
||||
|
||||
//
|
||||
sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR), .Y(SOC_DIR_N));
|
||||
sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE (.TE_B(SOC_DIR_N),
|
||||
.A(SOC_IN),
|
||||
.Z(FPGA_IN)
|
||||
);
|
||||
|
||||
//
|
||||
sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE (.TE_B(SOC_DIR),
|
||||
.A(FPGA_OUT),
|
||||
.Z(SOC_OUT)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
//
|
||||
`timescale 1ns/10ps
|
||||
`celldefine
|
||||
module scs8hd_muxinv2_1 (Z, Q1, Q2, S0, S0B, S1, S1B);
|
||||
output Z;
|
||||
input Q1, Q2, S0, S0B, S1, S1B;
|
||||
|
||||
wire Q1__bar, Q2__bar;
|
||||
|
||||
not (Q2__bar, Q2);
|
||||
not (Q1__bar, Q1);
|
||||
|
||||
bufif1 (Z, Q1__bar, S0);
|
||||
bufif1 (Z, Q2__bar, S1);
|
||||
|
||||
`ifdef ENABLE_SIGNAL_INITIALIZATION
|
||||
initial begin
|
||||
$deposit(Q1, 1'b0);
|
||||
$deposit(Q2, 1'b0);
|
||||
end
|
||||
`endif
|
||||
|
||||
specify
|
||||
(Q1 => Z) = 0.01;
|
||||
(Q2 => Z) = 0.01;
|
||||
(S0 => Z) = 0.01;
|
||||
(S0B => Z) = 0.01;
|
||||
(S1 => Z) = 0.01;
|
||||
(S1B => Z) = 0.01;
|
||||
endspecify
|
||||
endmodule
|
||||
`endcelldefine
|
||||
|
||||
//
|
||||
`timescale 1ns/10ps
|
||||
`celldefine
|
||||
module scs8hd_muxinv3_1 (Z, Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B);
|
||||
output Z;
|
||||
input Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B;
|
||||
|
||||
wire Q1__bar, Q2__bar, Q3__bar;
|
||||
|
||||
not (Q3__bar, Q3);
|
||||
not (Q2__bar, Q2);
|
||||
not (Q1__bar, Q1);
|
||||
|
||||
bufif1 (Z, Q1__bar, S0);
|
||||
bufif1 (Z, Q2__bar, S1);
|
||||
bufif1 (Z, Q3__bar, S2);
|
||||
|
||||
`ifdef ENABLE_SIGNAL_INITIALIZATION
|
||||
initial begin
|
||||
$deposit(Q1, 1'b0);
|
||||
$deposit(Q2, 1'b0);
|
||||
$deposit(Q3, 1'b0);
|
||||
end
|
||||
`endif
|
||||
|
||||
//
|
||||
specify
|
||||
(Q1 => Z) = 0.01;
|
||||
(Q3 => Z) = 0.01;
|
||||
(S0 => Z) = 0.01;
|
||||
(S0B => Z) = 0.01;
|
||||
(S2 => Z) = 0.01;
|
||||
(S2B => Z) = 0.01;
|
||||
endspecify
|
||||
endmodule
|
||||
`endcelldefine
|
||||
|
|
@ -0,0 +1,483 @@
|
|||
/*
|
||||
*-------------------------------------------------------------
|
||||
*
|
||||
* A wrapper for the FPGA IP to fit the I/O interface of Caravel SoC
|
||||
*
|
||||
* The wrapper is a technology mapped netlist where the mode-switch
|
||||
* multiplexers are mapped to the Skywater 130nm
|
||||
* High-Density (HD) standard cells
|
||||
*
|
||||
*-------------------------------------------------------------
|
||||
*/
|
||||
|
||||
module fpga_top (
|
||||
//
|
||||
//
|
||||
inout vdda1, //
|
||||
inout vdda2, //
|
||||
inout vssa1, //
|
||||
inout vssa2, //
|
||||
inout vccd1, //
|
||||
inout vccd2, //
|
||||
inout vssd1, //
|
||||
inout vssd2, //
|
||||
|
||||
//
|
||||
input wb_clk_i,
|
||||
input wb_rst_i,
|
||||
input wbs_stb_i,
|
||||
input wbs_cyc_i,
|
||||
input wbs_we_i,
|
||||
input [3:0] wbs_sel_i,
|
||||
input [31:0] wbs_dat_i,
|
||||
input [31:0] wbs_adr_i,
|
||||
output wbs_ack_o,
|
||||
output [31:0] wbs_dat_o,
|
||||
|
||||
//
|
||||
input [127:0] la_data_in,
|
||||
output [127:0] la_data_out,
|
||||
input [127:0] la_oen,
|
||||
|
||||
//
|
||||
input [37:0] io_in,
|
||||
output [37:0] io_out,
|
||||
output [37:0] io_oeb
|
||||
);
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
//
|
||||
wire prog_clk;
|
||||
wire Test_en;
|
||||
wire IO_ISOL_N;
|
||||
wire clk;
|
||||
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
|
||||
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
|
||||
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
|
||||
wire ccff_head;
|
||||
wire ccff_tail;
|
||||
wire sc_head;
|
||||
wire sc_tail;
|
||||
wire pReset;
|
||||
wire Reset;
|
||||
|
||||
//
|
||||
wire wb_la_switch;
|
||||
wire wb_la_switch_b;
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV (.A(wb_la_switch), .Y(wb_la_switch_b));
|
||||
|
||||
//
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24];
|
||||
assign io_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0];
|
||||
assign io_oeb[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = io_in[23];
|
||||
assign io_out[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1];
|
||||
assign io_oeb[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = io_in[22];
|
||||
assign io_out[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2];
|
||||
assign io_oeb[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = io_in[21];
|
||||
assign io_out[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3];
|
||||
assign io_oeb[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = io_in[20];
|
||||
assign io_out[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4];
|
||||
assign io_oeb[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = io_in[19];
|
||||
assign io_out[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5];
|
||||
assign io_oeb[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = io_in[18];
|
||||
assign io_out[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6];
|
||||
assign io_oeb[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = io_in[17];
|
||||
assign io_out[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7];
|
||||
assign io_oeb[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = io_in[16];
|
||||
assign io_out[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8];
|
||||
assign io_oeb[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = io_in[15];
|
||||
assign io_out[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9];
|
||||
assign io_oeb[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = io_in[14];
|
||||
assign io_out[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10];
|
||||
assign io_oeb[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = io_in[13];
|
||||
assign io_out[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11];
|
||||
assign io_oeb[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11];
|
||||
assign ccff_head = io_in[12];
|
||||
assign io_out[12] = 1'b0;
|
||||
assign io_oeb[12] = 1'b1;
|
||||
assign io_out[11] = sc_tail;
|
||||
assign io_oeb[11] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = io_in[10];
|
||||
assign io_out[10] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12];
|
||||
assign io_oeb[10] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = io_in[9];
|
||||
assign io_out[9] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13];
|
||||
assign io_oeb[9] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = io_in[8];
|
||||
assign io_out[8] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14];
|
||||
assign io_oeb[8] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = io_in[7];
|
||||
assign io_out[7] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15];
|
||||
assign io_oeb[7] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = io_in[6];
|
||||
assign io_out[6] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16];
|
||||
assign io_oeb[6] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = io_in[5];
|
||||
assign io_out[5] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17];
|
||||
assign io_oeb[5] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = io_in[4];
|
||||
assign io_out[4] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18];
|
||||
assign io_oeb[4] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18];
|
||||
assign pReset = io_in[3];
|
||||
assign io_out[3] = 1'b0;
|
||||
assign io_oeb[3] = 1'b1;
|
||||
assign Reset = io_in[2];
|
||||
assign io_out[2] = 1'b0;
|
||||
assign io_oeb[2] = 1'b1;
|
||||
assign IO_ISOL_N = io_in[1];
|
||||
assign io_out[1] = 1'b0;
|
||||
assign io_oeb[1] = 1'b1;
|
||||
assign Test_en = io_in[0];
|
||||
assign io_out[0] = 1'b0;
|
||||
assign io_oeb[0] = 1'b1;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = la_data_in[127];
|
||||
assign la_data_out[127] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = la_data_in[126];
|
||||
assign la_data_out[126] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[125];
|
||||
assign la_data_out[125] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[124];
|
||||
assign la_data_out[124] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[123];
|
||||
assign la_data_out[123] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[122];
|
||||
assign la_data_out[122] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[121];
|
||||
assign la_data_out[121] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[120];
|
||||
assign la_data_out[120] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[119];
|
||||
assign la_data_out[119] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[118];
|
||||
assign la_data_out[118] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[117];
|
||||
assign la_data_out[117] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[116];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(wbs_dat_o[0]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(la_data_out[116]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[115];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(wbs_dat_o[1]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(la_data_out[115]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[114];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(wbs_dat_o[2]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(la_data_out[114]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[113];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(wbs_dat_o[3]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(la_data_out[113]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[112];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(wbs_dat_o[4]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(la_data_out[112]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[111];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(wbs_dat_o[5]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(la_data_out[111]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[110];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(wbs_dat_o[6]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(la_data_out[110]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[109];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(wbs_dat_o[7]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(la_data_out[109]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[108];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(wbs_dat_o[8]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(la_data_out[108]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[107];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(wbs_dat_o[9]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(la_data_out[107]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[106];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(wbs_dat_o[10]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(la_data_out[106]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[105];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(wbs_dat_o[11]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(la_data_out[105]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[104];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(wbs_dat_o[12]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(la_data_out[104]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[103];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(wbs_dat_o[13]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(la_data_out[103]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[102];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(wbs_dat_o[14]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(la_data_out[102]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[101];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(wbs_dat_o[15]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(la_data_out[101]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[100];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(wbs_dat_o[16]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(la_data_out[100]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[99];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(wbs_dat_o[17]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(la_data_out[99]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[98];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(wbs_dat_o[18]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(la_data_out[98]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[97];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(wbs_dat_o[19]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(la_data_out[97]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[96];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(wbs_dat_o[20]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(la_data_out[96]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[95];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(wbs_dat_o[21]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(la_data_out[95]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[94];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(wbs_dat_o[22]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(la_data_out[94]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[93];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(wbs_dat_o[23]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(la_data_out[93]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[92];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(wbs_dat_o[24]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(la_data_out[92]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[91];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(wbs_dat_o[25]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(la_data_out[91]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[90];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(wbs_dat_o[26]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(la_data_out[90]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[89];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(wbs_dat_o[27]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(la_data_out[89]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[88];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(wbs_dat_o[28]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(la_data_out[88]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[87];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(wbs_dat_o[29]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(la_data_out[87]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[86];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(wbs_dat_o[30]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(la_data_out[86]));
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[85];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(wbs_dat_o[31]));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(la_data_out[85]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX (.S(wb_la_switch), .A1(wbs_dat_i[0]), .A0(la_data_in[84]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62]));
|
||||
assign la_data_out[84] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX (.S(wb_la_switch), .A1(wbs_dat_i[1]), .A0(la_data_in[83]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63]));
|
||||
assign la_data_out[83] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX (.S(wb_la_switch), .A1(wbs_dat_i[2]), .A0(la_data_in[82]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64]));
|
||||
assign la_data_out[82] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX (.S(wb_la_switch), .A1(wbs_dat_i[3]), .A0(la_data_in[81]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65]));
|
||||
assign la_data_out[81] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX (.S(wb_la_switch), .A1(wbs_dat_i[4]), .A0(la_data_in[80]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66]));
|
||||
assign la_data_out[80] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX (.S(wb_la_switch), .A1(wbs_dat_i[5]), .A0(la_data_in[79]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67]));
|
||||
assign la_data_out[79] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX (.S(wb_la_switch), .A1(wbs_dat_i[6]), .A0(la_data_in[78]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68]));
|
||||
assign la_data_out[78] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX (.S(wb_la_switch), .A1(wbs_dat_i[7]), .A0(la_data_in[77]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69]));
|
||||
assign la_data_out[77] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX (.S(wb_la_switch), .A1(wbs_dat_i[8]), .A0(la_data_in[76]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70]));
|
||||
assign la_data_out[76] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX (.S(wb_la_switch), .A1(wbs_dat_i[9]), .A0(la_data_in[75]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71]));
|
||||
assign la_data_out[75] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX (.S(wb_la_switch), .A1(wbs_dat_i[10]), .A0(la_data_in[74]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72]));
|
||||
assign la_data_out[74] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX (.S(wb_la_switch), .A1(wbs_dat_i[11]), .A0(la_data_in[73]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73]));
|
||||
assign la_data_out[73] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX (.S(wb_la_switch), .A1(wbs_dat_i[12]), .A0(la_data_in[72]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74]));
|
||||
assign la_data_out[72] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX (.S(wb_la_switch), .A1(wbs_dat_i[13]), .A0(la_data_in[71]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75]));
|
||||
assign la_data_out[71] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX (.S(wb_la_switch), .A1(wbs_dat_i[14]), .A0(la_data_in[70]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76]));
|
||||
assign la_data_out[70] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX (.S(wb_la_switch), .A1(wbs_dat_i[15]), .A0(la_data_in[69]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77]));
|
||||
assign la_data_out[69] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX (.S(wb_la_switch), .A1(wbs_dat_i[16]), .A0(la_data_in[68]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78]));
|
||||
assign la_data_out[68] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX (.S(wb_la_switch), .A1(wbs_dat_i[17]), .A0(la_data_in[67]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79]));
|
||||
assign la_data_out[67] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX (.S(wb_la_switch), .A1(wbs_dat_i[18]), .A0(la_data_in[66]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80]));
|
||||
assign la_data_out[66] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX (.S(wb_la_switch), .A1(wbs_dat_i[19]), .A0(la_data_in[65]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81]));
|
||||
assign la_data_out[65] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX (.S(wb_la_switch), .A1(wbs_dat_i[20]), .A0(la_data_in[64]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82]));
|
||||
assign la_data_out[64] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX (.S(wb_la_switch), .A1(wbs_dat_i[21]), .A0(la_data_in[63]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83]));
|
||||
assign la_data_out[63] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX (.S(wb_la_switch), .A1(wbs_dat_i[22]), .A0(la_data_in[62]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84]));
|
||||
assign la_data_out[62] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX (.S(wb_la_switch), .A1(wbs_dat_i[23]), .A0(la_data_in[61]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85]));
|
||||
assign la_data_out[61] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX (.S(wb_la_switch), .A1(wbs_dat_i[24]), .A0(la_data_in[60]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86]));
|
||||
assign la_data_out[60] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX (.S(wb_la_switch), .A1(wbs_dat_i[25]), .A0(la_data_in[59]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87]));
|
||||
assign la_data_out[59] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX (.S(wb_la_switch), .A1(wbs_dat_i[26]), .A0(la_data_in[58]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88]));
|
||||
assign la_data_out[58] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX (.S(wb_la_switch), .A1(wbs_dat_i[27]), .A0(la_data_in[57]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89]));
|
||||
assign la_data_out[57] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX (.S(wb_la_switch), .A1(wbs_dat_i[28]), .A0(la_data_in[56]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90]));
|
||||
assign la_data_out[56] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX (.S(wb_la_switch), .A1(wbs_dat_i[29]), .A0(la_data_in[55]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91]));
|
||||
assign la_data_out[55] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX (.S(wb_la_switch), .A1(wbs_dat_i[30]), .A0(la_data_in[54]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92]));
|
||||
assign la_data_out[54] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX (.S(wb_la_switch), .A1(wbs_dat_i[31]), .A0(la_data_in[53]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93]));
|
||||
assign la_data_out[53] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX (.S(wb_la_switch), .A1(wbs_adr_i[0]), .A0(la_data_in[52]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94]));
|
||||
assign la_data_out[52] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX (.S(wb_la_switch), .A1(wbs_adr_i[1]), .A0(la_data_in[51]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95]));
|
||||
assign la_data_out[51] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX (.S(wb_la_switch), .A1(wbs_adr_i[2]), .A0(la_data_in[50]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96]));
|
||||
assign la_data_out[50] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX (.S(wb_la_switch), .A1(wbs_adr_i[3]), .A0(la_data_in[49]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97]));
|
||||
assign la_data_out[49] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX (.S(wb_la_switch), .A1(wbs_adr_i[4]), .A0(la_data_in[48]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98]));
|
||||
assign la_data_out[48] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX (.S(wb_la_switch), .A1(wbs_adr_i[5]), .A0(la_data_in[47]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99]));
|
||||
assign la_data_out[47] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX (.S(wb_la_switch), .A1(wbs_adr_i[6]), .A0(la_data_in[46]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100]));
|
||||
assign la_data_out[46] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX (.S(wb_la_switch), .A1(wbs_adr_i[7]), .A0(la_data_in[45]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101]));
|
||||
assign la_data_out[45] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX (.S(wb_la_switch), .A1(wbs_adr_i[8]), .A0(la_data_in[44]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102]));
|
||||
assign la_data_out[44] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX (.S(wb_la_switch), .A1(wbs_adr_i[9]), .A0(la_data_in[43]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103]));
|
||||
assign la_data_out[43] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX (.S(wb_la_switch), .A1(wbs_adr_i[10]), .A0(la_data_in[42]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104]));
|
||||
assign la_data_out[42] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX (.S(wb_la_switch), .A1(wbs_adr_i[11]), .A0(la_data_in[41]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105]));
|
||||
assign la_data_out[41] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX (.S(wb_la_switch), .A1(wbs_adr_i[12]), .A0(la_data_in[40]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106]));
|
||||
assign la_data_out[40] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX (.S(wb_la_switch), .A1(wbs_adr_i[13]), .A0(la_data_in[39]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107]));
|
||||
assign la_data_out[39] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX (.S(wb_la_switch), .A1(wbs_adr_i[14]), .A0(la_data_in[38]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108]));
|
||||
assign la_data_out[38] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX (.S(wb_la_switch), .A1(wbs_adr_i[15]), .A0(la_data_in[37]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109]));
|
||||
assign la_data_out[37] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX (.S(wb_la_switch), .A1(wbs_adr_i[16]), .A0(la_data_in[36]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110]));
|
||||
assign la_data_out[36] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX (.S(wb_la_switch), .A1(wbs_adr_i[17]), .A0(la_data_in[35]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111]));
|
||||
assign la_data_out[35] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX (.S(wb_la_switch), .A1(wbs_adr_i[18]), .A0(la_data_in[34]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112]));
|
||||
assign la_data_out[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX (.S(wb_la_switch), .A1(wbs_adr_i[19]), .A0(la_data_in[33]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113]));
|
||||
assign la_data_out[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX (.S(wb_la_switch), .A1(wbs_adr_i[20]), .A0(la_data_in[32]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114]));
|
||||
assign la_data_out[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX (.S(wb_la_switch), .A1(wbs_adr_i[21]), .A0(la_data_in[31]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115]));
|
||||
assign la_data_out[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX (.S(wb_la_switch), .A1(wbs_adr_i[22]), .A0(la_data_in[30]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116]));
|
||||
assign la_data_out[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX (.S(wb_la_switch), .A1(wbs_adr_i[23]), .A0(la_data_in[29]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117]));
|
||||
assign la_data_out[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX (.S(wb_la_switch), .A1(wbs_adr_i[24]), .A0(la_data_in[28]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118]));
|
||||
assign la_data_out[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX (.S(wb_la_switch), .A1(wbs_adr_i[25]), .A0(la_data_in[27]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119]));
|
||||
assign la_data_out[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX (.S(wb_la_switch), .A1(wbs_adr_i[26]), .A0(la_data_in[26]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120]));
|
||||
assign la_data_out[26] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX (.S(wb_la_switch), .A1(wbs_adr_i[27]), .A0(la_data_in[25]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121]));
|
||||
assign la_data_out[25] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX (.S(wb_la_switch), .A1(wbs_adr_i[28]), .A0(la_data_in[24]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122]));
|
||||
assign la_data_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX (.S(wb_la_switch), .A1(wbs_adr_i[29]), .A0(la_data_in[23]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123]));
|
||||
assign la_data_out[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX (.S(wb_la_switch), .A1(wbs_adr_i[30]), .A0(la_data_in[22]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124]));
|
||||
assign la_data_out[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX (.S(wb_la_switch), .A1(wbs_adr_i[31]), .A0(la_data_in[21]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125]));
|
||||
assign la_data_out[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX (.S(wb_la_switch), .A1(wbs_sel_i[0]), .A0(la_data_in[20]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126]));
|
||||
assign la_data_out[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX (.S(wb_la_switch), .A1(wbs_sel_i[1]), .A0(la_data_in[19]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127]));
|
||||
assign la_data_out[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX (.S(wb_la_switch), .A1(wbs_sel_i[2]), .A0(la_data_in[18]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128]));
|
||||
assign la_data_out[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX (.S(wb_la_switch), .A1(wbs_sel_i[3]), .A0(la_data_in[17]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129]));
|
||||
assign la_data_out[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX (.S(wb_la_switch), .A1(wbs_we_i), .A0(la_data_in[16]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130]));
|
||||
assign la_data_out[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX (.S(wb_la_switch), .A1(wbs_stb_i), .A0(la_data_in[15]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131]));
|
||||
assign la_data_out[15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX (.S(wb_la_switch), .A1(wbs_cyc_i), .A0(la_data_in[14]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132]));
|
||||
assign la_data_out[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[13];
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(wbs_ack_o));
|
||||
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(la_data_out[13]));
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX (.S(wb_la_switch), .A1(wb_rst_i), .A0(la_data_in[12]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134]));
|
||||
assign la_data_out[12] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134];
|
||||
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX (.S(wb_la_switch), .A1(wb_clk_i), .A0(la_data_in[11]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135]));
|
||||
assign la_data_out[11] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135];
|
||||
assign prog_clk = io_in[37];
|
||||
assign io_out[37] = 1'b0;
|
||||
assign io_oeb[37] = 1'b1;
|
||||
assign clk = io_in[36];
|
||||
assign io_out[36] = 1'b0;
|
||||
assign io_oeb[36] = 1'b1;
|
||||
assign io_out[35] = ccff_tail;
|
||||
assign io_oeb[35] = 1'b0;
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = io_in[34];
|
||||
assign io_out[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136];
|
||||
assign io_oeb[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = io_in[33];
|
||||
assign io_out[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137];
|
||||
assign io_oeb[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = io_in[32];
|
||||
assign io_out[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138];
|
||||
assign io_oeb[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = io_in[31];
|
||||
assign io_out[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139];
|
||||
assign io_oeb[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = io_in[30];
|
||||
assign io_out[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140];
|
||||
assign io_oeb[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = io_in[29];
|
||||
assign io_out[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141];
|
||||
assign io_oeb[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = io_in[28];
|
||||
assign io_out[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142];
|
||||
assign io_oeb[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142];
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = io_in[27];
|
||||
assign io_out[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143];
|
||||
assign io_oeb[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143];
|
||||
assign sc_head = io_in[26];
|
||||
assign io_out[26] = 1'b0;
|
||||
assign io_oeb[26] = 1'b1;
|
||||
//
|
||||
|
||||
//
|
||||
//
|
||||
assign wb_la_switch = io_in[25];
|
||||
assign io_out[25] = 1'b0;
|
||||
assign io_oeb[25] = 1'b1;
|
||||
|
||||
//
|
||||
|
||||
fpga_core fpga_core_uut(
|
||||
.prog_clk(prog_clk),
|
||||
.Test_en(Test_en),
|
||||
.clk(clk),
|
||||
.IO_ISOL_N(IO_ISOL_N),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
|
||||
.ccff_head(ccff_head),
|
||||
.ccff_tail(ccff_tail),
|
||||
.sc_head(sc_head),
|
||||
.sc_tail(sc_tail),
|
||||
.pReset(pReset),
|
||||
.Reset(Reset)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
module const0(const0);
|
||||
//
|
||||
output [0:0] const0;
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
assign const0[0] = 1'b0;
|
||||
endmodule
|
||||
//
|
||||
|
||||
//
|
||||
module const1(const1);
|
||||
//
|
||||
output [0:0] const1;
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
assign const1[0] = 1'b1;
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
module local_encoder1to1 ( addr, data, data_inv );
|
||||
input [0:0] addr;
|
||||
output [0:0] data;
|
||||
output [0:0] data_inv;
|
||||
wire \data[0] ;
|
||||
assign data[0] = \data[0] ;
|
||||
assign \data[0] = addr[0];
|
||||
|
||||
sky130_fd_sc_hd__clkinv_1 U2 ( .A(\data[0] ), .Y(data_inv[0]) );
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
module local_encoder1to2 ( addr, data, data_inv );
|
||||
input [0:0] addr;
|
||||
output [0:1] data;
|
||||
output [0:1] data_inv;
|
||||
wire \addr[0] , \data_inv[1] ;
|
||||
assign data[1] = \addr[0] ;
|
||||
assign data_inv[0] = \addr[0] ;
|
||||
assign \addr[0] = addr[0];
|
||||
assign data[0] = \data_inv[1] ;
|
||||
assign data_inv[1] = \data_inv[1] ;
|
||||
|
||||
sky130_fd_sc_hd__clkinv_1 U2 ( .A(\addr[0] ), .Y(\data_inv[1] ) );
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
module local_encoder2to3 ( addr, data, data_inv );
|
||||
input [0:1] addr;
|
||||
output [0:2] data;
|
||||
output [0:2] data_inv;
|
||||
wire \data[2] ;
|
||||
assign data[2] = \data[2] ;
|
||||
assign \data[2] = addr[1];
|
||||
|
||||
sky130_fd_sc_hd__clkinv_1 U8 ( .A(data[0]), .Y(data_inv[0]) );
|
||||
sky130_fd_sc_hd__clkinv_1 U9 ( .A(data_inv[1]), .Y(data[1]) );
|
||||
sky130_fd_sc_hd__nand2_1 U10 ( .A(addr[0]), .B(data_inv[2]), .Y(data_inv[1])
|
||||
);
|
||||
sky130_fd_sc_hd__clkinv_1 U11 ( .A(\data[2] ), .Y(data_inv[2]) );
|
||||
sky130_fd_sc_hd__nor2_1 U12 ( .A(\data[2] ), .B(addr[0]), .Y(data[0]) );
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
module local_encoder2to4 ( addr, data, data_inv );
|
||||
input [0:1] addr;
|
||||
output [0:3] data;
|
||||
output [0:3] data_inv;
|
||||
wire n9;
|
||||
|
||||
sky130_fd_sc_hd__nor2_1 U13 ( .A(addr[1]), .B(addr[0]), .Y(data[0]) );
|
||||
sky130_fd_sc_hd__clkinv_1 U14 ( .A(data[1]), .Y(data_inv[1]) );
|
||||
sky130_fd_sc_hd__clkinv_1 U15 ( .A(data[0]), .Y(data_inv[0]) );
|
||||
sky130_fd_sc_hd__clkinv_1 U16 ( .A(data_inv[2]), .Y(data[2]) );
|
||||
sky130_fd_sc_hd__nand2_1 U17 ( .A(addr[1]), .B(n9), .Y(data_inv[2]) );
|
||||
sky130_fd_sc_hd__nor2_1 U18 ( .A(n9), .B(addr[1]), .Y(data[1]) );
|
||||
sky130_fd_sc_hd__clkinv_1 U19 ( .A(addr[0]), .Y(n9) );
|
||||
sky130_fd_sc_hd__clkinv_1 U20 ( .A(data_inv[3]), .Y(data[3]) );
|
||||
sky130_fd_sc_hd__nand2_1 U21 ( .A(addr[1]), .B(addr[0]), .Y(data_inv[3]) );
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
module frac_lut4(in,
|
||||
sram,
|
||||
sram_inv,
|
||||
mode,
|
||||
mode_inv,
|
||||
lut2_out,
|
||||
lut3_out,
|
||||
lut4_out);
|
||||
//
|
||||
input [0:3] in;
|
||||
//
|
||||
input [0:15] sram;
|
||||
//
|
||||
input [0:15] sram_inv;
|
||||
//
|
||||
input [0:0] mode;
|
||||
//
|
||||
input [0:0] mode_inv;
|
||||
//
|
||||
output [0:1] lut2_out;
|
||||
//
|
||||
output [0:1] lut3_out;
|
||||
//
|
||||
output [0:0] lut4_out;
|
||||
|
||||
//
|
||||
wire [0:3] in;
|
||||
wire [0:1] lut2_out;
|
||||
wire [0:1] lut3_out;
|
||||
wire [0:0] lut4_out;
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
wire [0:0] sky130_fd_sc_hd__buf_2_0_X;
|
||||
wire [0:0] sky130_fd_sc_hd__buf_2_1_X;
|
||||
wire [0:0] sky130_fd_sc_hd__buf_2_2_X;
|
||||
wire [0:0] sky130_fd_sc_hd__buf_2_3_X;
|
||||
wire [0:0] sky130_fd_sc_hd__inv_1_0_Y;
|
||||
wire [0:0] sky130_fd_sc_hd__inv_1_1_Y;
|
||||
wire [0:0] sky130_fd_sc_hd__inv_1_2_Y;
|
||||
wire [0:0] sky130_fd_sc_hd__inv_1_3_Y;
|
||||
wire [0:0] sky130_fd_sc_hd__or2_1_0_X;
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_ (
|
||||
.A(mode[0]),
|
||||
.B(in[3]),
|
||||
.X(sky130_fd_sc_hd__or2_1_0_X[0]));
|
||||
|
||||
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
|
||||
.A(in[0]),
|
||||
.Y(sky130_fd_sc_hd__inv_1_0_Y[0]));
|
||||
|
||||
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ (
|
||||
.A(in[1]),
|
||||
.Y(sky130_fd_sc_hd__inv_1_1_Y[0]));
|
||||
|
||||
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ (
|
||||
.A(in[2]),
|
||||
.Y(sky130_fd_sc_hd__inv_1_2_Y[0]));
|
||||
|
||||
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
|
||||
.A(sky130_fd_sc_hd__or2_1_0_X[0]),
|
||||
.Y(sky130_fd_sc_hd__inv_1_3_Y[0]));
|
||||
|
||||
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ (
|
||||
.A(in[0]),
|
||||
.X(sky130_fd_sc_hd__buf_2_0_X[0]));
|
||||
|
||||
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ (
|
||||
.A(in[1]),
|
||||
.X(sky130_fd_sc_hd__buf_2_1_X[0]));
|
||||
|
||||
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ (
|
||||
.A(in[2]),
|
||||
.X(sky130_fd_sc_hd__buf_2_2_X[0]));
|
||||
|
||||
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ (
|
||||
.A(sky130_fd_sc_hd__or2_1_0_X[0]),
|
||||
.X(sky130_fd_sc_hd__buf_2_3_X[0]));
|
||||
|
||||
frac_lut4_mux frac_lut4_mux_0_ (
|
||||
.in(sram[0:15]),
|
||||
.sram({sky130_fd_sc_hd__buf_2_0_X[0], sky130_fd_sc_hd__buf_2_1_X[0], sky130_fd_sc_hd__buf_2_2_X[0], sky130_fd_sc_hd__buf_2_3_X[0]}),
|
||||
.sram_inv({sky130_fd_sc_hd__inv_1_0_Y[0], sky130_fd_sc_hd__inv_1_1_Y[0], sky130_fd_sc_hd__inv_1_2_Y[0], sky130_fd_sc_hd__inv_1_3_Y[0]}),
|
||||
.lut2_out(lut2_out[0:1]),
|
||||
.lut3_out(lut3_out[0:1]),
|
||||
.lut4_out(lut4_out[0]));
|
||||
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,370 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
module mux_2level_basis_input4_mem4(in,
|
||||
mem,
|
||||
mem_inv,
|
||||
out);
|
||||
//
|
||||
input [0:3] in;
|
||||
//
|
||||
input [0:3] mem;
|
||||
//
|
||||
input [0:3] mem_inv;
|
||||
//
|
||||
output [0:0] out;
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
scs8hd_muxinv2_1 scs8hd_muxinv2_1_0(
|
||||
.Q1(in[0]),
|
||||
.Q2(in[1]),
|
||||
.S0(mem[0]),
|
||||
.S0B(mem_inv[0]),
|
||||
.S1(mem[1]),
|
||||
.S1B(mem_inv[1]),
|
||||
.Z(out[0])
|
||||
);
|
||||
scs8hd_muxinv2_1 scs8hd_muxinv2_1_1(
|
||||
.Q1(in[2]),
|
||||
.Q2(in[3]),
|
||||
.S0(mem[2]),
|
||||
.S0B(mem_inv[2]),
|
||||
.S1(mem[3]),
|
||||
.S1B(mem_inv[3]),
|
||||
.Z(out[0])
|
||||
);
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
module mux_2level_basis_input2_mem2(in,
|
||||
mem,
|
||||
mem_inv,
|
||||
out);
|
||||
//
|
||||
input [0:1] in;
|
||||
//
|
||||
input [0:1] mem;
|
||||
//
|
||||
input [0:1] mem_inv;
|
||||
//
|
||||
output [0:0] out;
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
scs8hd_muxinv2_1 scs8hd_muxinv2_1_0(
|
||||
.Q1(in[0]),
|
||||
.Q2(in[1]),
|
||||
.S0(mem[0]),
|
||||
.S0B(mem_inv[0]),
|
||||
.S1(mem[1]),
|
||||
.S1B(mem_inv[1]),
|
||||
.Z(out[0])
|
||||
);
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
module mux_2level_tapbuf_basis_input3_mem3(in,
|
||||
mem,
|
||||
mem_inv,
|
||||
out);
|
||||
//
|
||||
input [0:2] in;
|
||||
//
|
||||
input [0:2] mem;
|
||||
//
|
||||
input [0:2] mem_inv;
|
||||
//
|
||||
output [0:0] out;
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
scs8hd_muxinv3_1 scs8hd_muxinv3_1_0(
|
||||
.Q1(in[0]),
|
||||
.Q2(in[1]),
|
||||
.Q3(in[2]),
|
||||
.S0(mem[0]),
|
||||
.S0B(mem_inv[0]),
|
||||
.S1(mem[1]),
|
||||
.S1B(mem_inv[1]),
|
||||
.S2(mem[2]),
|
||||
.S2B(mem_inv[2]),
|
||||
.Z(out[0])
|
||||
);
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
module mux_2level_tapbuf_basis_input2_mem2(in,
|
||||
mem,
|
||||
mem_inv,
|
||||
out);
|
||||
//
|
||||
input [0:1] in;
|
||||
//
|
||||
input [0:1] mem;
|
||||
//
|
||||
input [0:1] mem_inv;
|
||||
//
|
||||
output [0:0] out;
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
scs8hd_muxinv2_1 scs8hd_muxinv2_1_0(
|
||||
.Q1(in[0]),
|
||||
.Q2(in[1]),
|
||||
.S0(mem[0]),
|
||||
.S0B(mem_inv[0]),
|
||||
.S1(mem[1]),
|
||||
.S1B(mem_inv[1]),
|
||||
.Z(out[0])
|
||||
);
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
module mux_2level_tapbuf_basis_input4_mem4(in,
|
||||
mem,
|
||||
mem_inv,
|
||||
out);
|
||||
//
|
||||
input [0:3] in;
|
||||
//
|
||||
input [0:3] mem;
|
||||
//
|
||||
input [0:3] mem_inv;
|
||||
//
|
||||
output [0:0] out;
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
scs8hd_muxinv2_1 scs8hd_muxinv2_1_0(
|
||||
.Q1(in[0]),
|
||||
.Q2(in[1]),
|
||||
.S0(mem[0]),
|
||||
.S0B(mem_inv[0]),
|
||||
.S1(mem[1]),
|
||||
.S1B(mem_inv[1]),
|
||||
.Z(out[0])
|
||||
);
|
||||
scs8hd_muxinv2_1 scs8hd_muxinv2_1_1(
|
||||
.Q1(in[2]),
|
||||
.Q2(in[3]),
|
||||
.S0(mem[2]),
|
||||
.S0B(mem_inv[2]),
|
||||
.S1(mem[3]),
|
||||
.S1B(mem_inv[3]),
|
||||
.Z(out[0])
|
||||
);
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
module mux_2level_tapbuf_basis_input2_mem1(in,
|
||||
mem,
|
||||
mem_inv,
|
||||
out);
|
||||
//
|
||||
input [0:1] in;
|
||||
//
|
||||
input [0:0] mem;
|
||||
//
|
||||
input [0:0] mem_inv;
|
||||
//
|
||||
output [0:0] out;
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0(
|
||||
.A1(in[0]),
|
||||
.A0(in[1]),
|
||||
.S(mem[0]),
|
||||
.X(out[0])
|
||||
);
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
module mux_1level_tapbuf_basis_input3_mem3(in,
|
||||
mem,
|
||||
mem_inv,
|
||||
out);
|
||||
//
|
||||
input [0:2] in;
|
||||
//
|
||||
input [0:2] mem;
|
||||
//
|
||||
input [0:2] mem_inv;
|
||||
//
|
||||
output [0:0] out;
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
scs8hd_muxinv3_1 scs8hd_muxinv3_1_0(
|
||||
.Q1(in[0]),
|
||||
.Q2(in[1]),
|
||||
.Q3(in[2]),
|
||||
.S0(mem[0]),
|
||||
.S0B(mem_inv[0]),
|
||||
.S1(mem[1]),
|
||||
.S1B(mem_inv[1]),
|
||||
.S2(mem[2]),
|
||||
.S2B(mem_inv[2]),
|
||||
.Z(out[0])
|
||||
);
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
module mux_1level_basis_input3_mem3(in,
|
||||
mem,
|
||||
mem_inv,
|
||||
out);
|
||||
//
|
||||
input [0:2] in;
|
||||
//
|
||||
input [0:2] mem;
|
||||
//
|
||||
input [0:2] mem_inv;
|
||||
//
|
||||
output [0:0] out;
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
scs8hd_muxinv3_1 scs8hd_muxinv3_1_0(
|
||||
.Q1(in[0]),
|
||||
.Q2(in[1]),
|
||||
.Q3(in[2]),
|
||||
.S0(mem[0]),
|
||||
.S0B(mem_inv[0]),
|
||||
.S1(mem[1]),
|
||||
.S1B(mem_inv[1]),
|
||||
.S2(mem[2]),
|
||||
.S2B(mem_inv[2]),
|
||||
.Z(out[0])
|
||||
);
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,20 @@
|
|||
`timescale 1ns/1ps
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
module sky130_fd_sc_hd__mux2_1_wrapper (
|
||||
input A0,
|
||||
input A1,
|
||||
input S,
|
||||
output X
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__mux2_1 MUX2 (.A0(A0),
|
||||
.A1(A1),
|
||||
.S(S),
|
||||
.X(X)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
//
|
||||
module direct_interc(in,
|
||||
out);
|
||||
//
|
||||
input [0:0] in;
|
||||
//
|
||||
output [0:0] out;
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
|
||||
wire [0:0] in;
|
||||
wire [0:0] out;
|
||||
assign out[0] = in[0];
|
||||
endmodule
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
`include "./SRC/define_simulation.v"
|
||||
|
||||
//
|
||||
`include "./SRC/fabric_netlists.v"
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
`include "top_output_verilog.v"
|
||||
`endif
|
||||
|
||||
`ifdef ENABLE_FORMAL_VERIFICATION
|
||||
`include "./SRC/top_top_formal_verification.v"
|
||||
`ifdef FORMAL_SIMULATION
|
||||
`include "./SRC/top_formal_random_top_tb.v"
|
||||
`endif
|
||||
`endif
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
`include "./SRC/top_autocheck_top_tb.v"
|
||||
`endif
|
||||
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue