[Sync] Updated sync file list

.github/workflows/perform_precheck.sh

@@ -44,8 +44,7 @@ mv ./gds/caravel_merged.gds ./gds/caravel.gds
 # rm -f gds/caravel.old.gds
 
 # = = = = = = = = = = = = = Perform Open MPW Checks = = = = = = = = = = = = = =
-if [[ ! -n "$SKIP_PRECHECK" ]]; then
-    echo $SKIP_PRECHECK
+if [[ "$SKIP_PRECHECK" != 1 ]]; then
     echo "[Info] Running MPW Prechecker"
     cd /usr/local/bin
     python3 open_mpw_prechecker.py \

.github/workflows/sync_repo.sh

@@ -5,10 +5,13 @@
 # Working directory in github workspace
 # Original repo is places SOFA-Chips
 # for conditional file copy use PROJ_SUFFIX (example SOFA_HD)
-
-tail -n +2 ./SOFA-Chips/SynRepoConfig/sync_files.csv | while  IFS=, read -r srcLoc dstLoc; do
-    Copying "./SOFA-Chips/$srcLoc --> ${DEST_DIR}/$dstLoc"
-    rsync -avp ./SOFA-Chips/$srcLoc ${DEST_DIR}/$dstLoc
+COPY_FILE="./SOFA-Chips/SynRepoConfig/sync_files_${PROJ_SUFFIX,,}.csv"
+echo "[Info] Using file for rsync $COPY_FILE"
+tail -n +2 $COPY_FILE | while  IFS=, read -r srcLoc dstLoc; do
+    srcLoc=$(echo $(eval "echo $srcLoc"))
+    dstLoc=$(echo $(eval "echo $dstLoc"))
+    echo "Copying ./SOFA-Chips/$srcLoc --> ${DEST_DIR}/$dstLoc"
+    rsync -ap ./SOFA-Chips/$srcLoc ${DEST_DIR}/$dstLoc
 done
 
 cd ${DEST_DIR}

SynRepoConfig/sync_files.csv

@@ -1,2 +0,0 @@
-SrcLoc, DestLoc
-FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/,OpenFPGA_task

SynRepoConfig/sync_files_qlsofa_hd.csv

@@ -0,0 +1,4 @@
+SrcLoc, DestLoc
+FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/,OpenFPGA_task
+FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
+FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v

SynRepoConfig/sync_files_sofa_chd.csv

@@ -0,0 +1,4 @@
+SrcLoc, DestLoc
+FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task
+FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
+FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v

SynRepoConfig/sync_files_sofa_hd.csv

@@ -0,0 +1,4 @@
+SrcLoc, DestLoc
+FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/,OpenFPGA_task
+FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
+FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v