mirror of https://github.com/lnis-uofu/SOFA.git
Merge remote-tracking branch 'origin/master' into ganesh_dev
This commit is contained in:
Ganesh Gore
commit
06e220d7e4
|
|
@ -1,3 +1,3 @@
|
|||
*.gds filter=lfs diff=lfs merge=lfs -text
|
||||
*.spef filter=lfs diff=lfs merge=lfs -text
|
||||
TESTBENCH/**/*.v filter=lfs diff=lfs merge=lfs -text
|
||||
TESTBENCH/*/pnr/verilog_testbench/*_tb.v filter=lfs diff=lfs merge=lfs -text
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ sudo apt-get install libxft-dev
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|||
sudo apt-get install libxml++2.6-dev
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||||
sudo apt-get install perl
|
||||
sudo apt-get install python
|
||||
sudo apt-get install python3-setuptools
|
||||
sudo apt-get install python-lxml
|
||||
sudo apt-get install texinfo
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||||
sudo apt-get install time
|
||||
|
|
@ -46,3 +47,5 @@ sudo apt-get install g++-9
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|||
sudo apt-get install gcc-9
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||||
sudo apt-get install clang-6.0
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||||
sudo apt-get install clang-8
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||||
# Python dependencies
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||||
python3 -m pip install -r /home/runner/work/SOFA/SOFA/OpenFPGA/requirements.txt
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||||
|
|
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|||
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@ -103,7 +103,8 @@
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|||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
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||||
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
|
||||
<!-- Trick OpenFPGA to avoid auto-generating TGATE modules, which are not used in PnR -->
|
||||
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/fd_hd_mux_custom_cells_tt.v">
|
||||
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
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||||
|
|
@ -288,7 +289,7 @@
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|||
</direct_connection>
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||||
<tile_annotations>
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||||
<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
|
||||
<global_port name="reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
|
||||
<global_port name="Reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
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||||
</tile_annotations>
|
||||
<pb_type_annotations>
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||||
<!-- physical pb_type binding in complex block IO -->
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||||
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|
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|||
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@ -6,7 +6,7 @@
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|||
#recommonmark
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||||
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||||
#Handle references in bibtex format
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||||
sphinxcontrib-bibtex
|
||||
sphinxcontrib-bibtex<2.0.0
|
||||
sphinxcontrib-tikz
|
||||
|
||||
#Work-around bug "AttributeError: 'Values' object has no attribute 'character_level_inline_markup'" with docutils 0.13.1
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||||
|
|
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|||
|
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@ -7,3 +7,5 @@
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|||
sofa_hd/index
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||||
|
||||
qlsofa_hd/index
|
||||
|
||||
sofa_chd/index
|
||||
|
|
|
|||
|
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@ -1,253 +0,0 @@
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Before Width: | Height: | Size: 22 KiB |
File diff suppressed because it is too large
Load Diff
|
Before Width: | Height: | Size: 72 KiB |
|
|
@ -1,4 +1,4 @@
|
|||
.. _datasheet_sofa_hd:
|
||||
.. _datasheet_qlsofa_hd:
|
||||
QLSOFA HD
|
||||
|
||||
QLSOFA HD
|
||||
|
|
|
|||
|
|
@ -8,29 +8,14 @@ Circuit Designs
|
|||
I/O Circuit
|
||||
^^^^^^^^^^^
|
||||
|
||||
As shown in :numref:`fig_qlsofa_hd_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_qlsofa_hd_fpga_arch`) is an digital I/O cell with
|
||||
QLSOFA HD FPGA share the same I/O circuit design as SOFA HD FPGA.
|
||||
See details at :ref:`sofa_hd_circuit_design_io`.
|
||||
|
||||
- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized.
|
||||
.. _sofa_hd_circuit_design_mux:
|
||||
|
||||
.. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality!
|
||||
Multiplexer
|
||||
^^^^^^^^^^^
|
||||
|
||||
- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid
|
||||
|
||||
- ``SOC_OUT`` port outputs any random signal when the I/O is in input mode
|
||||
- ``FPGA_IN`` port is driven by any random signal when the I/O is output mode
|
||||
QLSOFA HD FPGA share the same multiplexer design as SOFA HD FPGA.
|
||||
See details at :ref:`sofa_hd_circuit_design_mux`.
|
||||
|
||||
- An internal configurable memory element to control the direction of I/O cell
|
||||
|
||||
The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where
|
||||
|
||||
- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode
|
||||
|
||||
- When configuration bit (FF output) is logic ``0``, the I/O cell is in output mode
|
||||
|
||||
.. _fig_qlsofa_hd_embedded_io_schematic:
|
||||
|
||||
.. figure:: ./figures/qlsofa_hd_embedded_io_schematic.svg
|
||||
:scale: 30%
|
||||
:alt: Schematic of embedded I/O cell used in FPGA
|
||||
|
||||
Schematic of embedded I/O cell used in FPGA
|
||||
|
|
|
|||
|
|
@ -8,21 +8,8 @@ Architecture
|
|||
Floorplan
|
||||
^^^^^^^^^
|
||||
|
||||
|
||||
:numref:`fig_qlsofa_hd_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric.
|
||||
The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric.
|
||||
I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`qlsofa_hd_io_resource`).
|
||||
|
||||
.. _fig_qlsofa_hd_fpga_arch:
|
||||
|
||||
.. figure:: ./figures/qlsofa_hd_fpga_arch.svg
|
||||
:scale: 25%
|
||||
:alt: Tile-based FPGA architecture
|
||||
|
||||
Tile-based FPGA architecture
|
||||
|
||||
|
||||
.. _qlsofa_hd_fpga_arch_tiles:
|
||||
QLSOFA HD FPGA share the same floroplan as SOFA HD FPGA.
|
||||
See details at :ref:`sofa_hd_fpga_arch_floorplan`.
|
||||
|
||||
Tiles
|
||||
^^^^^
|
||||
|
|
@ -64,19 +51,5 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra
|
|||
Scan-chain
|
||||
^^^^^^^^^^
|
||||
|
||||
There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`qlsofa_hd_clb_arch_scan_chain`), as illustrated in :numref:`fig_qlsofa_hd_fabric_scan_chain`.
|
||||
|
||||
When `Test_en` signal is active, users can
|
||||
|
||||
- overwrite the contents of all the D-type flip-flops in the FPGA by feeding signals to the `SC_HEAD` port
|
||||
- readback the contents of all the D-type flip-flops in the FPGA through the `SC_TAIL` port.
|
||||
|
||||
.. _fig_qlsofa_hd_fabric_scan_chain:
|
||||
|
||||
.. figure:: ./figures/qlsofa_hd_fabric_scan_chain.svg
|
||||
:scale: 25%
|
||||
:alt: Built-in scan-chain across FPGA
|
||||
|
||||
Built-in scan-chain across FPGA
|
||||
|
||||
|
||||
QLSOFA HD FPGA share the same floroplan as SOFA HD FPGA.
|
||||
See details at :ref:`sofa_hd_fpga_arch_scan_chain`.
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ I/O Resources
|
|||
Pin Assignment
|
||||
^^^^^^^^^^^^^^
|
||||
|
||||
The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`.
|
||||
The QLSOFA HD FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`.
|
||||
|
||||
Among the 144 I/Os,
|
||||
|
||||
|
|
@ -26,14 +26,14 @@ Among the 144 I/Os,
|
|||
:scale: 20%
|
||||
:alt: I/O arrangement of FPGA IP
|
||||
|
||||
I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface
|
||||
I/O arrangement of QLSOFA HD FPGA IP: switchable between logic analyzer and wishbone bus interface
|
||||
|
||||
.. _io_resource_qlsofa_hd_external_io:
|
||||
|
||||
External I/Os
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
A SOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os.
|
||||
A QLSOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os.
|
||||
|
||||
Full details are summarized in the following table.
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,433 @@
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.. _datasheet_sofa_chd:
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SOFA CHD
|
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|
||||
SOFA CHD
|
||||
--------
|
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|
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.. toctree::
|
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:maxdepth: 2
|
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|
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sofa_chd_fpga_arch
|
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sofa_chd_io_resource
|
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sofa_chd_clb_arch
|
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sofa_chd_circuit_design
|
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|
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@ -0,0 +1,42 @@
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.. _sofa_chd_circuit_design:
|
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|
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Circuit Designs
|
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---------------
|
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|
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.. _sofa_chd_circuit_design_io:
|
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|
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I/O Circuit
|
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^^^^^^^^^^^
|
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SOFA CHD FPGA share the same I/O circuit design as SOFA HD FPGA.
|
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See details at :ref:`sofa_hd_circuit_design_io`.
|
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.. _sofa_hd_circuit_design_mux:
|
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|
||||
Multiplexer
|
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^^^^^^^^^^^
|
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|
||||
Routing multiplexer are designed by using a few custom cells based on the Skywater *High-Density* (HD) PDK, as shown in :numref:`fig_sofa_chd_mux_circuit`.
|
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The multiplexer design follows a two-level structure, which is applied to all the routing multiplexers in logic elements, connection blocks and switch blocks across the FPGA fabric.
|
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|
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.. _fig_sofa_chd_mux_circuit:
|
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|
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.. figure:: ./figures/sofa_chd_mux_circuit.svg
|
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:scale: 30%
|
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:alt: Schematic of multiplexer design in SOFA CHD FPGA
|
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|
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Schematic of multiplexer design in SOFA CHD FPGA
|
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|
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Each primitive in the two-level structure could be a 2/3/4-input custom cell, depending on the input size of the routing multiplexer.
|
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Each custom cell is built with input inverters and transmission-gates.
|
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For instance, :numref:`fig_sofa_chd_custom_mux_cells` shows the transistor-level design of a 3-input custom cell.
|
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.. _fig_sofa_chd_custom_mux_cells:
|
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|
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.. figure:: ./figures/custom_mux_cells.svg
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:scale: 40%
|
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:alt: Detailed schematic of a 3-input custom cell in SOFA CHD FPGA
|
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|
||||
Detailed schematic of a 3-input custom cell in SOFA CHD FPGA
|
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|
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.. note:: Each routing multiplexer has a dedicated input which is connected to ground (GND) signal. When it is not used, the output will be driven by the ground, working as a constant generator.
|
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|
|
@ -0,0 +1,7 @@
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.. _sofa_chd_clb_arch:
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|
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Configurable Logic Block
|
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------------------------
|
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|
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The SOFA CHD FPGA IP share the same *Configurable Logic Block* (CLB) architecture as QLSOFA HD FPGA IP.
|
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See details at :ref:`qlsofa_hd_clb_arch`.
|
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|
|
@ -0,0 +1,7 @@
|
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.. _sofa_chd_fpga_arch:
|
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|
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Architecture
|
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-------------
|
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|
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SOFA CHD FPGA share the same architecture as QLSOFA HD FPGA.
|
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See full details at :ref:`qlsofa_hd_fpga_arch`.
|
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|
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@ -0,0 +1,7 @@
|
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.. _sofa_chd_io_resource:
|
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|
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I/O Resources
|
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-------------
|
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|
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The SOFA CHD FPGA IP share the same I/O resource arragement as QLSOFA HD FPGA IP.
|
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See details at :ref:`qlsofa_hd_io_resource`.
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Before Width: | Height: | Size: 18 KiB After Width: | Height: | Size: 19 KiB |
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|
After Width: | Height: | Size: 48 KiB |
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Load Diff
|
After Width: | Height: | Size: 86 KiB |
|
|
@ -21,7 +21,7 @@ As shown in :numref:`fig_sofa_hd_embedded_io_schematic`, the I/O circuit used in
|
|||
|
||||
- An internal configurable memory element to control the direction of I/O cell
|
||||
|
||||
The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where
|
||||
The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC (which requires an active-low signal to enable output directionality), where
|
||||
|
||||
- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode
|
||||
|
||||
|
|
@ -34,3 +34,36 @@ The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC,
|
|||
:alt: Schematic of embedded I/O cell used in FPGA
|
||||
|
||||
Schematic of embedded I/O cell used in FPGA
|
||||
|
||||
:numref:`fig_sofa_hd_embedded_io_test_waveform` shows an example waveform about how the I/O cell works:
|
||||
|
||||
- When ``IO_ISOL_N`` is enabled/disabled
|
||||
- When operates in input mode
|
||||
- When operates in output mode
|
||||
|
||||
.. _fig_sofa_hd_embedded_io_test_waveform:
|
||||
|
||||
.. figure:: ./figures/sofa_hd_embedded_io_test_waveform.svg
|
||||
:scale: 30%
|
||||
:alt: Schematic of embedded I/O cell used in FPGA
|
||||
|
||||
An example of waveforms of embedded I/O cell used in FPGA
|
||||
|
||||
|
||||
.. _sofa_hd_circuit_design_mux:
|
||||
|
||||
Multiplexer
|
||||
^^^^^^^^^^^
|
||||
|
||||
Routing multiplexer are designed by using the skywater *High-Density* (HD) 2-input MUX cell, as shown in :numref:`fig_sofa_hd_mux_circuit`.
|
||||
The tree-like multiplexer design is applied to all the routing multiplexers in logic elements, connection blocks and switch blocks across the FPGA fabric.
|
||||
|
||||
.. _fig_sofa_hd_mux_circuit:
|
||||
|
||||
.. figure:: ./figures/sofa_hd_mux_circuit.svg
|
||||
:scale: 30%
|
||||
:alt: Schematic of multiplexer design in SOFA HD FPGA
|
||||
|
||||
Schematic of multiplexer design in SOFA HD FPGA
|
||||
|
||||
.. note:: Each routing multiplexer has a dedicated input which is connected to ground (GND) signal. When it is not used, the output will be driven by the ground, working as a constant generator.
|
||||
|
|
|
|||
Binary file not shown.
|
After Width: | Height: | Size: 741 KiB |
|
|
@ -7,27 +7,27 @@ The High Density (HD) FPGAs are embedded FPGAs built with the Skywater 130nm Hig
|
|||
|
||||
.. table:: Logic capacity of High Density (HD) FPGA IPs
|
||||
|
||||
+-------------------------------+------------+-----------+
|
||||
| Resource/Capacity | SOFA HD | QLSOFA HD |
|
||||
+===============================+============+===========+
|
||||
| Look-Up Tables [1]_ | 1152 | 1152 |
|
||||
+-------------------------------+------------+-----------+
|
||||
| Flip-flops | 2304 | 2304 |
|
||||
+-------------------------------+------------+-----------+
|
||||
| Soft Adders [2]_ | N/A | 1152 |
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||||
+-------------------------------+------------+-----------+
|
||||
| Routing Channel Width [3]_ | 40 | 60 |
|
||||
+-------------------------------+------------+-----------+
|
||||
| Max. Configuration Speed [4]_ | 50MHz | 50MHz |
|
||||
+-------------------------------+------------+-----------+
|
||||
| Max. Operating Speed [4]_ | 50MHz | 50 MHz |
|
||||
+-------------------------------+------------+-----------+
|
||||
| User I/O Pins [5]_ | 144 | 144 |
|
||||
+-------------------------------+------------+-----------+
|
||||
| Max. I/O Speed [4]_ | 33MHz | 33 MHz |
|
||||
+-------------------------------+------------+-----------+
|
||||
| Core Voltage | 1.8V | 1.8V |
|
||||
+-------------------------------+------------+-----------+
|
||||
+-------------------------------+------------+-----------+----------+
|
||||
| Resource/Capacity | SOFA HD | QLSOFA HD | SOFA CHD |
|
||||
+===============================+============+===========+==========+
|
||||
| Look-Up Tables [1]_ | 1152 | 1152 | 1152 |
|
||||
+-------------------------------+------------+-----------+----------+
|
||||
| Flip-flops | 2304 | 2304 | 2304 |
|
||||
+-------------------------------+------------+-----------+----------+
|
||||
| Soft Adders [2]_ | N/A | 1152 | 1152 |
|
||||
+-------------------------------+------------+-----------+----------+
|
||||
| Routing Channel Width [3]_ | 40 | 60 | 60 |
|
||||
+-------------------------------+------------+-----------+----------+
|
||||
| Max. Configuration Speed [4]_ | 50MHz | 50MHz | 50MHz |
|
||||
+-------------------------------+------------+-----------+----------+
|
||||
| Max. Operating Speed [4]_ | 50MHz | 50 MHz | 50MHz |
|
||||
+-------------------------------+------------+-----------+----------+
|
||||
| User I/O Pins [5]_ | 144 | 144 | 144 |
|
||||
+-------------------------------+------------+-----------+----------+
|
||||
| Max. I/O Speed [4]_ | 33MHz | 33MHz | 33MHz |
|
||||
+-------------------------------+------------+-----------+----------+
|
||||
| Core Voltage | 1.8V | 1.8V | 1.8V |
|
||||
+-------------------------------+------------+-----------+----------+
|
||||
|
||||
.. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT.
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,18 @@
|
|||
Introduction
|
||||
------------
|
||||
|
||||
All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII.
|
||||
All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK.
|
||||
The devices are embedded FPGA IPs, which are designed to interface the caravel SoC interface.
|
||||
We aims to empower embedded applications with its low-cost design approach but high-density architecture.
|
||||
Operating temperature ranging from 0 :math:`^\circ C` to 85 :math:`^\circ C`
|
||||
*Skywater Opensource FpgA* (SOFA) is a fully open-source embedded FPGA IP library, from the architecture description to production ready layouts.
|
||||
As illustrated in :numref:`fig_sofa_motivation`, SOFA IPs are designed through the Skywater 130nm PDK, OpenFPGA framework and Synopsys IC Compiler II.
|
||||
The runtime of the design flow for each IP is within 24 hours.
|
||||
|
||||
All the SOFA FPGAs are designed to interface the Caravel SoC interface.
|
||||
We aims to empower embedded applications with its low-cost design approach but high-density architecture.
|
||||
|
||||
.. _fig_sofa_motivation:
|
||||
|
||||
.. figure:: ./figures/sofa_motivation.png
|
||||
:scale: 15%
|
||||
:alt: 24-hour FPGA IP development: from PDK to production-ready layout
|
||||
|
||||
24-hour FPGA IP development: from PDK to production-ready layout
|
||||
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
You can adapt this file completely to your liking, but it should at least
|
||||
contain the root `toctree` directive.
|
||||
|
||||
Welcome to SKywater-OpenFPGA documentation!
|
||||
===========================================
|
||||
Welcome to SOFA documentation!
|
||||
==============================
|
||||
|
||||
.. toctree::
|
||||
:caption: Device Family
|
||||
|
|
|
|||
|
|
@ -0,0 +1,41 @@
|
|||
//-------------------------------------------
|
||||
// A file to include all the dependency HDL codes
|
||||
// required by Caravel gate-level netlists
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
`define USE_POWER_PINS 1
|
||||
|
||||
////////////////////////////////////
|
||||
// Skywater standard cell netlists
|
||||
// I/O cells
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v"
|
||||
// High density cells
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
|
||||
// High voltage cells
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
|
||||
|
||||
// Gate-level netlists
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/DFFRAM.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/caravel.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/chip_io.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/digital_pll.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/mgmt_core.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/storage.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/user_id_programming.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/user_proj_example.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/user_project_wrapper.v"
|
||||
|
||||
// Use RTL codes for the following module as the gate-level netlists are buggy
|
||||
// in handling power pins
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/defines.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/mgmt_protect.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/mgmt_protect_hv.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/gpio_control_block.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/simple_por.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
|
||||
|
|
@ -58,9 +58,9 @@ custom_nlist = open(args.output_verilog, "w")
|
|||
#######################################################################
|
||||
# A function to generate Verilog codes for a MUX3 custom cell
|
||||
# Given an input index
|
||||
def generate_verilog_codes_custom_cell_mux3(first_input_index, instance_index):
|
||||
def generate_verilog_codes_custom_cell_mux3(first_input_index, instance_index, add_inverter_follower):
|
||||
lines = []
|
||||
|
||||
# Instanciate a 3-input MUX cell
|
||||
lines.append("\tscs8hd_muxinv3_1 scs8hd_muxinv3_1_" + str(instance_index) + "(")
|
||||
lines.append("\t .Q1(in[" + str(first_input_index) + "]),")
|
||||
lines.append("\t .Q2(in[" + str(first_input_index + 1) + "]),")
|
||||
|
|
@ -71,17 +71,28 @@ def generate_verilog_codes_custom_cell_mux3(first_input_index, instance_index):
|
|||
lines.append("\t .S1B(mem_inv[" + str(first_input_index + 1) + "]),")
|
||||
lines.append("\t .S2(mem[" + str(first_input_index + 2) + "]),")
|
||||
lines.append("\t .S2B(mem_inv[" + str(first_input_index + 2) + "]),")
|
||||
lines.append("\t .Z(out[0])")
|
||||
if (add_inverter_follower):
|
||||
lines.append("\t .Z(out_inv[0])")
|
||||
else:
|
||||
lines.append("\t .Z(out[0])")
|
||||
lines.append("\t );")
|
||||
|
||||
# Instanciate an inverter follower to pair the MUX cells (which has input inverters)
|
||||
if (add_inverter_follower):
|
||||
lines.append("\tsky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower" + str(instance_index) + "(")
|
||||
lines.append("\t .A(out_inv[0]),")
|
||||
lines.append("\t .Y(out[0])")
|
||||
lines.append("\t );")
|
||||
|
||||
return lines
|
||||
|
||||
#######################################################################
|
||||
# A function to generate Verilog codes for a MUX3 custom cell
|
||||
# Given an input index
|
||||
def generate_verilog_codes_custom_cell_mux2(first_input_index, instance_index):
|
||||
def generate_verilog_codes_custom_cell_mux2(first_input_index, instance_index, add_inverter_follower):
|
||||
lines = []
|
||||
|
||||
# Instanciate a 2-input MUX cell
|
||||
lines.append("\tscs8hd_muxinv2_1 scs8hd_muxinv2_1_" + str(instance_index) + "(")
|
||||
lines.append("\t .Q1(in[" + str(first_input_index) + "]),")
|
||||
lines.append("\t .Q2(in[" + str(first_input_index + 1) + "]),")
|
||||
|
|
@ -89,9 +100,19 @@ def generate_verilog_codes_custom_cell_mux2(first_input_index, instance_index):
|
|||
lines.append("\t .S0B(mem_inv[" + str(first_input_index) + "]),")
|
||||
lines.append("\t .S1(mem[" + str(first_input_index + 1) + "]),")
|
||||
lines.append("\t .S1B(mem_inv[" + str(first_input_index + 1) + "]),")
|
||||
lines.append("\t .Z(out[0])")
|
||||
if (add_inverter_follower):
|
||||
lines.append("\t .Z(out_inv[0])")
|
||||
else:
|
||||
lines.append("\t .Z(out[0])")
|
||||
lines.append("\t );")
|
||||
|
||||
# Instanciate an inverter follower to pair the MUX cells (which has input inverters)
|
||||
if (add_inverter_follower):
|
||||
lines.append("\tsky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower" + str(instance_index) + "(")
|
||||
lines.append("\t .A(out_inv[0]),")
|
||||
lines.append("\t .Y(out[0])")
|
||||
lines.append("\t );")
|
||||
|
||||
return lines
|
||||
|
||||
#######################################################################
|
||||
|
|
@ -116,8 +137,12 @@ def generate_verilog_codes_standard_cell_mux2(first_input_index, instance_index)
|
|||
# In this case, an standard cell will be outputted
|
||||
# - If the memory size is larger than 1, the input size should be the same
|
||||
# as memory size. In this case, we will output custom cells
|
||||
def write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size):
|
||||
def write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size, add_inverter_follower):
|
||||
lines = []
|
||||
|
||||
if (add_inverter_follower):
|
||||
lines.append("wire [0:0] out_inv;")
|
||||
|
||||
if (1 == mem_size):
|
||||
assert(2 == input_size)
|
||||
# Output a standard cell, currently we support HD cell MUX2
|
||||
|
|
@ -132,17 +157,17 @@ def write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size):
|
|||
# - a few MUX2 cells
|
||||
if (1 == input_size % 2):
|
||||
assert(3 <= input_size)
|
||||
for line in generate_verilog_codes_custom_cell_mux3(0, 0):
|
||||
for line in generate_verilog_codes_custom_cell_mux3(0, 0, add_inverter_follower):
|
||||
lines.append(line)
|
||||
for mux2_inst in range(int((input_size - 3) / 2)):
|
||||
for line in generate_verilog_codes_custom_cell_mux2(3 + 2 * mux2_inst, mux2_inst):
|
||||
for line in generate_verilog_codes_custom_cell_mux2(3 + 2 * mux2_inst, mux2_inst, add_inverter_follower):
|
||||
lines.append(line)
|
||||
# - If the input size is an even number, we will use
|
||||
# - a few MUX2 cells
|
||||
else:
|
||||
assert (0 == input_size % 2)
|
||||
for mux2_inst in range(int(input_size / 2)):
|
||||
for line in generate_verilog_codes_custom_cell_mux2(2 * mux2_inst, mux2_inst):
|
||||
for line in generate_verilog_codes_custom_cell_mux2(2 * mux2_inst, mux2_inst, add_inverter_follower):
|
||||
lines.append(line)
|
||||
|
||||
# Output lines to file
|
||||
|
|
@ -154,6 +179,7 @@ with open(args.template_netlist, "r") as wp:
|
|||
template_nlist = wp.readlines()
|
||||
# A flag for write the current line or skip
|
||||
output_action = "copy"
|
||||
mux_structure = "1level"
|
||||
input_size = 0
|
||||
mem_size = 0
|
||||
for line_num, curr_line in enumerate(template_nlist):
|
||||
|
|
@ -168,6 +194,12 @@ with open(args.template_netlist, "r") as wp:
|
|||
mem_size = int(re.findall("input(\d+)_mem(\d+)\(", curr_line)[0][1])
|
||||
assert(input_size > 0)
|
||||
assert(mem_size > 0)
|
||||
# Find the MUX structure levels
|
||||
if (re.search("1level", curr_line)):
|
||||
mux_structure = "1level"
|
||||
else:
|
||||
assert(re.search("2level", curr_line))
|
||||
mux_structure = "2level"
|
||||
# Change status indicating that we are now inside a module
|
||||
output_action = "copy"
|
||||
|
||||
|
|
@ -179,7 +211,7 @@ with open(args.template_netlist, "r") as wp:
|
|||
# Reaching the end of the current module
|
||||
# Now output the custom cell instanciation
|
||||
if (curr_line.startswith("endmodule")):
|
||||
write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size)
|
||||
write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size, "1level" != mux_structure)
|
||||
output_action = "copy"
|
||||
|
||||
if ("skip" != output_action):
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ module EMBEDDED_IO_HD (
|
|||
sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (.B_N(IO_ISOL_N),
|
||||
.A(FPGA_DIR),
|
||||
.X(SOC_DIR)
|
||||
);
|
||||
);
|
||||
|
||||
// Use drive-strength 4 for a high fan-out from global routing architecture
|
||||
sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR), .Y(SOC_DIR_N));
|
||||
|
|
|
|||
|
|
@ -16,6 +16,9 @@ import argparse
|
|||
import logging
|
||||
import subprocess
|
||||
import glob
|
||||
import threading
|
||||
import multiprocessing
|
||||
import run_post_pnr_msim_test
|
||||
|
||||
#####################################################################
|
||||
# Initialize logger
|
||||
|
|
@ -64,15 +67,16 @@ num_sim_finished = 0
|
|||
msim_testrun_script_abspath = os.path.abspath(__file__)
|
||||
msim_testrun_script_abspath = re.sub(os.path.basename(msim_testrun_script_abspath), "run_post_pnr_msim_test.py", msim_testrun_script_abspath)
|
||||
|
||||
threads = []
|
||||
for testbench_file in testbench_files:
|
||||
# Find testbench name
|
||||
testbench_name = re.findall("(\w+)_include_netlists.v", os.path.basename(testbench_file))[0]
|
||||
cmd = "python3 " + msim_testrun_script_abspath \
|
||||
+ " --verilog_testbench " + testbench_file \
|
||||
+ " --project_path " + msim_task_dir_abspath + "/" + testbench_name \
|
||||
+ " --testbench_name " + testbench_name + "_autocheck_top_tb"
|
||||
subprocess.run(cmd, shell=True, check=True)
|
||||
num_sim_finished += 1
|
||||
process = multiprocessing.Process(target=run_post_pnr_msim_test.run_msim, args=(testbench_file, msim_task_dir_abspath + "/" + testbench_name, testbench_name + "_autocheck_top_tb",))
|
||||
process.start()
|
||||
threads.append(process)
|
||||
|
||||
for process in threads:
|
||||
process.join()
|
||||
|
||||
logging.info("Done")
|
||||
logging.info("Finish " + str(num_sim_finished) + " ModelSim simulations")
|
||||
logging.info("Finish " + str(len(threads)) + " ModelSim simulations")
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
# - Analyze output log files and return succeed or failure
|
||||
#####################################################################
|
||||
|
||||
import sys
|
||||
import os
|
||||
from os.path import dirname, abspath, isfile
|
||||
import shutil
|
||||
|
|
@ -18,138 +19,150 @@ import subprocess
|
|||
# Initialize logger
|
||||
#####################################################################
|
||||
logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.INFO)
|
||||
#####################################################################
|
||||
# Main function of this script, so that it can be called by other scripts
|
||||
#####################################################################
|
||||
def main(args):
|
||||
#####################################################################
|
||||
# Parse the options
|
||||
#####################################################################
|
||||
parser = argparse.ArgumentParser(description='Run ModelSim verification for a testbench')
|
||||
parser.add_argument('--verilog_testbench', required=True,
|
||||
help='Specify the file path for the Verilog testbench as input')
|
||||
parser.add_argument('--project_path', required=True,
|
||||
help='Specify the file path to create the ModelSim project')
|
||||
parser.add_argument('--testbench_name', required=True,
|
||||
help='Specify the top-level module of the testbench')
|
||||
args = parser.parse_args(args)
|
||||
|
||||
run_msim(args.verilog_testbench, args.project_path, args.testbench_name)
|
||||
|
||||
#####################################################################
|
||||
# Parse the options
|
||||
# Main function of this script, so that it can be called by other scripts
|
||||
#####################################################################
|
||||
parser = argparse.ArgumentParser(description='Run ModelSim verification for a testbench')
|
||||
parser.add_argument('--verilog_testbench', required=True,
|
||||
help='Specify the file path for the Verilog testbench as input')
|
||||
parser.add_argument('--project_path', required=True,
|
||||
help='Specify the file path to create the ModelSim project')
|
||||
parser.add_argument('--testbench_name', required=True,
|
||||
help='Specify the top-level module of the testbench')
|
||||
args = parser.parse_args()
|
||||
def run_msim(verilog_testbench, project_path, testbench_name):
|
||||
#####################################################################
|
||||
# Check options:
|
||||
# - Input testbench file must be valid
|
||||
# Otherwise, error out
|
||||
# - If the modelsim project path does not exist, create it
|
||||
#####################################################################
|
||||
if not isfile(verilog_testbench):
|
||||
logging.error("Invalid Verilog testbench: " + verilog_testbench + "\nFile does not exist!\n")
|
||||
exit(1)
|
||||
|
||||
project_abs_path = os.path.abspath(project_path)
|
||||
if not os.path.isdir(project_abs_path):
|
||||
logging.debug("Creating ModelSim project directory : " + project_abs_path + " ...\n")
|
||||
os.makedirs(project_abs_path, exist_ok=True)
|
||||
logging.debug("Done\n")
|
||||
|
||||
#####################################################################
|
||||
# Create the Tcl script for Modelsim
|
||||
#####################################################################
|
||||
# Get modelsim process tcl file path
|
||||
msim_proc_tcl_path = os.path.abspath(__file__)
|
||||
msim_proc_tcl_path = re.sub(os.path.basename(msim_proc_tcl_path), "modelsim_proc.tcl", msim_proc_tcl_path)
|
||||
if not isfile(msim_proc_tcl_path):
|
||||
logging.error("Invalid process script for ModelSim: " + msim_proc_tcl_path + "\nFile does not exist!\n")
|
||||
exit(1)
|
||||
|
||||
# Create output file handler
|
||||
tcl_file_path = project_abs_path + "/" + os.path.basename(testbench_name) + ".tcl"
|
||||
logging.debug("Generating Tcl script for ModelSim: " + tcl_file_path)
|
||||
tcl_file = open(tcl_file_path, "w")
|
||||
|
||||
# A string buffer to write tcl content
|
||||
tcl_lines = []
|
||||
|
||||
tcl_lines.append("echo \"==============================\"")
|
||||
tcl_lines.append("pwd")
|
||||
tcl_lines.append("echo \"==============================\"")
|
||||
tcl_lines.append("\n")
|
||||
tcl_lines.append("set project_name " + testbench_name)
|
||||
tcl_lines.append("set top_tb " + testbench_name)
|
||||
tcl_lines.append("\n")
|
||||
tcl_lines.append("set project_path \"" + project_abs_path + "\"")
|
||||
tcl_lines.append("set verilog_files \"" + os.path.abspath(verilog_testbench) + "\"")
|
||||
tcl_lines.append("\n")
|
||||
tcl_lines.append("source " + msim_proc_tcl_path)
|
||||
tcl_lines.append("\n")
|
||||
tcl_lines.append("try {")
|
||||
tcl_lines.append("\ttop_create_new_project $project_name $verilog_files $project_path $top_tb")
|
||||
tcl_lines.append("} finally {")
|
||||
tcl_lines.append("\tquit")
|
||||
tcl_lines.append("}")
|
||||
|
||||
for line in tcl_lines:
|
||||
tcl_file.write(line + "\n")
|
||||
|
||||
tcl_file.close()
|
||||
logging.debug("Done")
|
||||
|
||||
#####################################################################
|
||||
# Run ModelSim simulation
|
||||
#####################################################################
|
||||
curr_dir = os.getcwd()
|
||||
# Change to the project directory
|
||||
os.chdir(project_abs_path)
|
||||
logging.debug("Changed to directory: " + project_abs_path)
|
||||
|
||||
# Run ModelSim
|
||||
vsim_log_file_path = project_abs_path + "/vsim_run_log"
|
||||
vsim_bin = "/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/bin/vsim"
|
||||
vsim_cmd = vsim_bin + " -c -do " + os.path.abspath(tcl_file_path) + " > " + vsim_log_file_path
|
||||
logging.debug("Running modelsim by : " + vsim_cmd)
|
||||
subprocess.run(vsim_cmd, shell=True, check=True)
|
||||
|
||||
# Go back to current directory
|
||||
os.chdir(curr_dir)
|
||||
|
||||
#####################################################################
|
||||
# Parse log files and report any errors
|
||||
#####################################################################
|
||||
vsim_log_file = open(vsim_log_file_path, "r")
|
||||
|
||||
# Error counter
|
||||
num_err = 0
|
||||
num_err_lines_found = 0
|
||||
verification_passed = False
|
||||
|
||||
for line in vsim_log_file:
|
||||
# Check errors from self-testing testbench output
|
||||
if line.startswith("# Simulation finish with") :
|
||||
num_sim_err = int(re.findall("# Simulation finish with(\s+)(\d+) errors", line)[0][1])
|
||||
num_err_lines_found += 1
|
||||
if (0 < num_sim_err) :
|
||||
logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n")
|
||||
# Add to total errors
|
||||
num_err += num_sim_err
|
||||
if line.startswith("# Simulation Failed with") :
|
||||
print (line)
|
||||
num_sim_err = int(re.findall("# Simulation Failed with(\s+)(\d+) error\(s\)", line)[0][1])
|
||||
num_err_lines_found += 1
|
||||
if (0 < num_sim_err) :
|
||||
logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n")
|
||||
# Add to total errors
|
||||
num_err += num_sim_err
|
||||
# Check total errors by Modelsim
|
||||
if line.startswith("# Errors:") :
|
||||
num_msim_err = int(re.findall("# Errors:(\s)(\d+),", line)[0][1])
|
||||
num_err_lines_found += 1
|
||||
num_err += num_msim_err
|
||||
|
||||
vsim_log_file.close()
|
||||
|
||||
if (0 == num_err_lines_found) :
|
||||
logging.error("No error lines found!Something wrong in setting up modelsim simulation\n")
|
||||
elif (0 < num_err) :
|
||||
logging.error("ModelSim failed with " + str(num_err) + " errors!\n")
|
||||
else :
|
||||
verification_passed = True
|
||||
|
||||
if (verification_passed) :
|
||||
logging.info(testbench_name + "...[Passed]\n")
|
||||
else :
|
||||
logging.error(testbench_name + "...[Failed]\n")
|
||||
|
||||
#####################################################################
|
||||
# Check options:
|
||||
# - Input testbench file must be valid
|
||||
# Otherwise, error out
|
||||
# - If the modelsim project path does not exist, create it
|
||||
#####################################################################
|
||||
if not isfile(args.verilog_testbench):
|
||||
logging.error("Invalid Verilog testbench: " + args.verilog_testbench + "\nFile does not exist!\n")
|
||||
exit(1)
|
||||
|
||||
project_abs_path = os.path.abspath(args.project_path)
|
||||
if not os.path.isdir(project_abs_path):
|
||||
logging.debug("Creating ModelSim project directory : " + project_abs_path + " ...\n")
|
||||
os.makedirs(project_abs_path, exist_ok=True)
|
||||
logging.debug("Done\n")
|
||||
|
||||
#####################################################################
|
||||
# Create the Tcl script for Modelsim
|
||||
#####################################################################
|
||||
# Get modelsim process tcl file path
|
||||
msim_proc_tcl_path = os.path.abspath(__file__)
|
||||
msim_proc_tcl_path = re.sub(os.path.basename(msim_proc_tcl_path), "modelsim_proc.tcl", msim_proc_tcl_path)
|
||||
if not isfile(msim_proc_tcl_path):
|
||||
logging.error("Invalid process script for ModelSim: " + msim_proc_tcl_path + "\nFile does not exist!\n")
|
||||
exit(1)
|
||||
|
||||
# Create output file handler
|
||||
tcl_file_path = project_abs_path + "/" + os.path.basename(args.testbench_name) + ".tcl"
|
||||
logging.debug("Generating Tcl script for ModelSim: " + tcl_file_path)
|
||||
tcl_file = open(tcl_file_path, "w")
|
||||
|
||||
# A string buffer to write tcl content
|
||||
tcl_lines = []
|
||||
|
||||
tcl_lines.append("echo \"==============================\"")
|
||||
tcl_lines.append("pwd")
|
||||
tcl_lines.append("echo \"==============================\"")
|
||||
tcl_lines.append("\n")
|
||||
tcl_lines.append("set project_name " + args.testbench_name)
|
||||
tcl_lines.append("set top_tb " + args.testbench_name)
|
||||
tcl_lines.append("\n")
|
||||
tcl_lines.append("set project_path \"" + project_abs_path + "\"")
|
||||
tcl_lines.append("set verilog_files \"" + os.path.abspath(args.verilog_testbench) + "\"")
|
||||
tcl_lines.append("\n")
|
||||
tcl_lines.append("source " + msim_proc_tcl_path)
|
||||
tcl_lines.append("\n")
|
||||
tcl_lines.append("try {")
|
||||
tcl_lines.append("\ttop_create_new_project $project_name $verilog_files $project_path $top_tb")
|
||||
tcl_lines.append("} finally {")
|
||||
tcl_lines.append("\tquit")
|
||||
tcl_lines.append("}")
|
||||
|
||||
for line in tcl_lines:
|
||||
tcl_file.write(line + "\n")
|
||||
|
||||
tcl_file.close()
|
||||
logging.debug("Done")
|
||||
|
||||
#####################################################################
|
||||
# Run ModelSim simulation
|
||||
#####################################################################
|
||||
curr_dir = os.getcwd()
|
||||
# Change to the project directory
|
||||
os.chdir(project_abs_path)
|
||||
logging.debug("Changed to directory: " + project_abs_path)
|
||||
|
||||
# Run ModelSim
|
||||
vsim_log_file_path = project_abs_path + "/vsim_run_log"
|
||||
vsim_bin = "/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/bin/vsim"
|
||||
vsim_cmd = vsim_bin + " -c -do " + os.path.abspath(tcl_file_path) + " > " + vsim_log_file_path
|
||||
logging.debug("Running modelsim by : " + vsim_cmd)
|
||||
subprocess.run(vsim_cmd, shell=True, check=True)
|
||||
|
||||
# Go back to current directory
|
||||
os.chdir(curr_dir)
|
||||
|
||||
#####################################################################
|
||||
# Parse log files and report any errors
|
||||
#####################################################################
|
||||
vsim_log_file = open(vsim_log_file_path, "r")
|
||||
|
||||
# Error counter
|
||||
num_err = 0
|
||||
num_err_lines_found = 0
|
||||
verification_passed = False
|
||||
|
||||
for line in vsim_log_file:
|
||||
# Check errors from self-testing testbench output
|
||||
if line.startswith("# Simulation finish with") :
|
||||
num_sim_err = int(re.findall("# Simulation finish with(\s+)(\d+) errors", line)[0][1])
|
||||
num_err_lines_found += 1
|
||||
if (0 < num_sim_err) :
|
||||
logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n")
|
||||
# Add to total errors
|
||||
num_err += num_sim_err
|
||||
if line.startswith("# Simulation Failed with") :
|
||||
print (line)
|
||||
num_sim_err = int(re.findall("# Simulation Failed with(\s+)(\d+) error\(s\)", line)[0][1])
|
||||
num_err_lines_found += 1
|
||||
if (0 < num_sim_err) :
|
||||
logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n")
|
||||
# Add to total errors
|
||||
num_err += num_sim_err
|
||||
# Check total errors by Modelsim
|
||||
if line.startswith("# Errors:") :
|
||||
num_msim_err = int(re.findall("# Errors:(\s)(\d+),", line)[0][1])
|
||||
num_err_lines_found += 1
|
||||
num_err += num_msim_err
|
||||
|
||||
vsim_log_file.close()
|
||||
|
||||
if (0 == num_err_lines_found) :
|
||||
logging.error("No error lines found!Something wrong in setting up modelsim simulation\n")
|
||||
elif (0 < num_err) :
|
||||
logging.error("ModelSim failed with " + str(num_err) + " errors!\n")
|
||||
else :
|
||||
verification_passed = True
|
||||
|
||||
if (verification_passed) :
|
||||
logging.info(args.testbench_name + "...[Passed]\n")
|
||||
else :
|
||||
logging.error(args.testbench_name + "...[Failed]\n")
|
||||
if __name__ == "__main__":
|
||||
main(sys.argv[1:])
|
||||
|
|
|
|||
|
|
@ -0,0 +1,10 @@
|
|||
# Skywater PDK
|
||||
This directory is the workspace for running Synopsys Design Compiler for FPGA primitives
|
||||
This required to synthesis decoders in FPGA fabrics
|
||||
Please keep this directory clean and organize as follows:
|
||||
- **HDL**: Any HDL to synthesis
|
||||
- **SCRIPT**: Scripts to enable Design Compile runs
|
||||
- **RPT**: Report files from Design Compiler runs
|
||||
- **TEMP**: workspace for Design Compiler projects
|
||||
- READMD is the only file allowed in the directory, others should be sub-directories.
|
||||
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
##########################################################
|
||||
# Template scripts to synthesize a combinational circuit
|
||||
# using Design Compiler
|
||||
# Author: Xifan Tang
|
||||
# Organization: University of Utah
|
||||
# Date: September 4th, 2020
|
||||
##########################################################
|
||||
|
||||
# Variable declaration
|
||||
set CTRITICAL_PATH 1; # [ns]
|
||||
|
||||
# Make sure a clean start
|
||||
remove_design -all
|
||||
|
||||
set DB_FILE "/research/ece/lnis/CAD_TOOLS/DKITS/skywater/skywater-pdk/vendor/synopsys/results/lib/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
|
||||
|
||||
# Read standard cell library
|
||||
# Here we consider the Skywater 130nm High Density(HD) cell library
|
||||
read_db ${DB_FILE}
|
||||
set target_library ${DB_FILE}
|
||||
set link_library ${DB_FILE}
|
||||
|
||||
set DESIGN_NAME DESIGN_NAME_VAR
|
||||
set RTL_NETLIST RTL_NETLIST_VAR
|
||||
|
||||
# Parse the HDL
|
||||
analyze -f verilog ${RTL_NETLIST}
|
||||
elaborate ${DESIGN_NAME}
|
||||
|
||||
# Set constraints
|
||||
# Push to 0 for the minimum area
|
||||
set_max_area 0
|
||||
|
||||
# Link to technology library and start compilation
|
||||
link
|
||||
compile -map_effort high
|
||||
|
||||
# Output netlist
|
||||
write -format Verilog -output ../GATE_NETLISTS/${DESIGN_NAME}_post_synth.v
|
||||
|
||||
# Report results
|
||||
report_unit > ../RPT/${DESIGN_NAME}_unit.rpt
|
||||
report_area > ../RPT/${DESIGN_NAME}_area.rpt
|
||||
report_timing > ../RPT/${DESIGN_NAME}_timing.rpt
|
||||
report_power > ../RPT/${DESIGN_NAME}_power.rpt
|
||||
report_reference > ../RPT/${DESIGN_NAME}_reference.rpt
|
||||
|
||||
# Finish here
|
||||
exit
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
#####################################################################
|
||||
# Python script to execute Design Compiler Synthesis for a given template tcl script
|
||||
# This script will
|
||||
# - Create the tcl script as synthesis recipe
|
||||
# - Run Design Compiler
|
||||
# - Analyze output log files and return succeed or failure
|
||||
#####################################################################
|
||||
|
||||
import sys
|
||||
import os
|
||||
from os.path import dirname, abspath, isfile
|
||||
import shutil
|
||||
import re
|
||||
import argparse
|
||||
import logging
|
||||
import subprocess
|
||||
|
||||
#####################################################################
|
||||
# Initialize logger
|
||||
#####################################################################
|
||||
logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.INFO)
|
||||
#####################################################################
|
||||
# Main function of this script, so that it can be called by other scripts
|
||||
#####################################################################
|
||||
def main(args):
|
||||
#####################################################################
|
||||
# Parse the options
|
||||
#####################################################################
|
||||
parser = argparse.ArgumentParser(description='Run Synopsys Design Compiler Synthesis for an input netlist')
|
||||
parser.add_argument('--rtl_netlist', required=True,
|
||||
help='Specify the file path to the RTL netlist as input')
|
||||
parser.add_argument('--recipe_template', required=True,
|
||||
help='Specify the file path to tcl script contain template synthesis recipe')
|
||||
parser.add_argument('--technology_library', required=True,
|
||||
help='Specify the technology library which the RTL netlist will be mapped to')
|
||||
parser.add_argument('--project_workspace', required=True,
|
||||
help='Specify the directory to run Design Compiler')
|
||||
args = parser.parse_args(args)
|
||||
|
||||
run_dc_batch_synth(args.rtl_netlist, args.recipe_template, args.technology_library, args.project_workspace)
|
||||
|
||||
#####################################################################
|
||||
# A function to execute a single-run of Design Compiler for a RTL design
|
||||
#####################################################################
|
||||
def run_dc_synth(rtl_netlist, rtl_design_name, recipe_template, technology_library, project_workspace):
|
||||
project_abs_path = os.path.abspath(project_workspace)
|
||||
if not os.path.isdir(project_abs_path):
|
||||
logging.debug("Creating Design Compiler project directory : " + project_abs_path + " ...\n")
|
||||
os.makedirs(project_abs_path, exist_ok=True)
|
||||
logging.debug("Done\n")
|
||||
|
||||
#####################################################################
|
||||
# Create the Tcl script for Design Compiler
|
||||
#####################################################################
|
||||
# Get absolute path to the template tcl script, it must be valid
|
||||
template_tcl_path = os.path.abspath(recipe_template)
|
||||
assert(isfile(template_tcl_path))
|
||||
|
||||
# Create output file handler
|
||||
tcl_file_path = project_abs_path + "/" + os.path.basename(rtl_design_name) + "_dc.tcl"
|
||||
logging.debug("Generating Tcl script from template recipe: " + tcl_file_path)
|
||||
|
||||
tcl_file = open(tcl_file_path, "w")
|
||||
|
||||
with open(template_tcl_path, "r") as wp:
|
||||
template_tcl_file = wp.readlines()
|
||||
for line_num, curr_line in enumerate(template_tcl_file):
|
||||
line2output = curr_line
|
||||
# Replace keywords with custom values
|
||||
line2output = re.sub("TECH_DB_VAR", technology_library, curr_line)
|
||||
line2output = re.sub("DESIGN_NAME_VAR", rtl_design_name, curr_line)
|
||||
line2output = re.sub("RTL_NETLIST_VAR", rtl_netlist, curr_line)
|
||||
# Finished processing
|
||||
# Output the line
|
||||
tcl_file.write(line2output)
|
||||
|
||||
tcl_file.close()
|
||||
logging.debug("Done")
|
||||
|
||||
#####################################################################
|
||||
# Run Design Compiler
|
||||
#####################################################################
|
||||
curr_dir = os.getcwd()
|
||||
# Change to the project directory
|
||||
os.chdir(project_abs_path)
|
||||
logging.debug("Changed to directory: " + project_abs_path)
|
||||
|
||||
# Run Design Compiler
|
||||
dc_log_file_path = project_abs_path + "/" + os.path.basename(rtl_design_name) + "_dc.log"
|
||||
dc_shell_bin = "dc_shell"
|
||||
dc_shell_cmd = dc_shell_bin + " -f " + os.path.abspath(tcl_file_path) + " > " + dc_log_file_path
|
||||
logging.debug("Running Design Compiler by : " + dc_shell_cmd)
|
||||
subprocess.run(dc_shell_cmd, shell=True, check=True)
|
||||
|
||||
# Go back to current directory
|
||||
os.chdir(curr_dir)
|
||||
|
||||
#####################################################################
|
||||
# Main function of this script, so that it can be called by other scripts
|
||||
#####################################################################
|
||||
def run_dc_batch_synth(rtl_netlist, recipe_template, technology_library, project_workspace):
|
||||
#####################################################################
|
||||
# Check options:
|
||||
# - Input files must be valid
|
||||
# Otherwise, error out
|
||||
#####################################################################
|
||||
if not isfile(rtl_netlist):
|
||||
logging.error("Invalid RTL netlist: " + rtr_netlist + "\nFile does not exist!\n")
|
||||
exit(1)
|
||||
|
||||
if not isfile(recipe_template):
|
||||
logging.error("Invalid recipe template: " + recipe_template + "\nFile does not exist!\n")
|
||||
exit(1)
|
||||
|
||||
if not isfile(technology_library):
|
||||
logging.error("Invalid technology library: " + technology_library + "\nFile does not exist!\n")
|
||||
exit(1)
|
||||
|
||||
#####################################################################
|
||||
# Collect all the RTL designs to synthesis from the RTL netlist
|
||||
#####################################################################
|
||||
rtl_design_names = []
|
||||
with open(rtl_netlist, "r") as wp:
|
||||
rtl_file = wp.readlines()
|
||||
# If a line starts with 'module', it is an RTL design to be synthesized
|
||||
for line_num, curr_line in enumerate(rtl_file):
|
||||
if (curr_line.startswith("module")):
|
||||
# Get the design name
|
||||
rtl_design_name = re.findall("module(\s+)(\w+)\(", curr_line)[0][1]
|
||||
rtl_design_names.append(rtl_design_name)
|
||||
|
||||
logging.info("Found " + str(len(rtl_design_names)) + " RTL designs to synthesize")
|
||||
|
||||
# Get absolute path to the template tcl script, it must be valid
|
||||
rtl_netlist_abs_path = os.path.abspath(rtl_netlist)
|
||||
assert(isfile(rtl_netlist_abs_path))
|
||||
|
||||
for rtl_design_name in rtl_design_names:
|
||||
logging.info("Running Design Compiler for design: " + rtl_design_name)
|
||||
run_dc_synth(rtl_netlist_abs_path, rtl_design_name, recipe_template, technology_library, project_workspace)
|
||||
logging.info("Done")
|
||||
|
||||
if __name__ == "__main__":
|
||||
main(sys.argv[1:])
|
||||
|
|
@ -0,0 +1 @@
|
|||
python3 SCRIPTS/run_dc_synth.py --rtl_netlist ../HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/SRC/sub_module/local_encoder.v --recipe_template SCRIPTS/dc_template.tcl --technology_library ../PDK/skywater-pdk/vendor/synopsys/results/lib/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db --project_workspace ./TEMP
|
||||
Binary file not shown.
BIN
TESTBENCH/common/post_pnr_fpga_cells.v (Stored with Git LFS)
BIN
TESTBENCH/common/post_pnr_fpga_cells.v (Stored with Git LFS)
Binary file not shown.
Binary file not shown.
BIN
TESTBENCH/digital_io_hd_test/digital_io_hd_test_include_netlists.v (Stored with Git LFS)
Normal file
BIN
TESTBENCH/digital_io_hd_test/digital_io_hd_test_include_netlists.v (Stored with Git LFS)
Normal file
Binary file not shown.
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v (Stored with Git LFS)
Normal file
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v (Stored with Git LFS)
Normal file
Binary file not shown.
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
Normal file
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
Normal file
Binary file not shown.
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v (Stored with Git LFS)
Normal file
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v (Stored with Git LFS)
Normal file
Binary file not shown.
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
Normal file
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
Normal file
Binary file not shown.
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v (Stored with Git LFS)
Normal file
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v (Stored with Git LFS)
Normal file
Binary file not shown.
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
Normal file
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
Normal file
Binary file not shown.
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v (Stored with Git LFS)
Normal file
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v (Stored with Git LFS)
Normal file
Binary file not shown.
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
Normal file
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
Normal file
Binary file not shown.
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v (Stored with Git LFS)
Normal file
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v (Stored with Git LFS)
Normal file
Binary file not shown.
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v (Stored with Git LFS)
Normal file
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v (Stored with Git LFS)
Normal file
Binary file not shown.
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
Normal file
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
Normal file
Binary file not shown.
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v (Stored with Git LFS)
Normal file
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v (Stored with Git LFS)
Normal file
Binary file not shown.
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
Normal file
BIN
TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
Normal file
Binary file not shown.
|
|
@ -0,0 +1,2 @@
|
|||
envyaml==1.0.201125
|
||||
humanize==3.1.0
|
||||
Loading…
Reference in New Issue