diff --git a/.gitattributes b/.gitattributes index 4aaecad..c570f03 100644 --- a/.gitattributes +++ b/.gitattributes @@ -1,3 +1,3 @@ *.gds filter=lfs diff=lfs merge=lfs -text *.spef filter=lfs diff=lfs merge=lfs -text -TESTBENCH/**/*.v filter=lfs diff=lfs merge=lfs -text +TESTBENCH/*/pnr/verilog_testbench/*_tb.v filter=lfs diff=lfs merge=lfs -text diff --git a/.github/workflows/install_dependency.sh b/.github/workflows/install_dependency.sh index 0e663ef..d2b8ffe 100644 --- a/.github/workflows/install_dependency.sh +++ b/.github/workflows/install_dependency.sh @@ -26,6 +26,7 @@ sudo apt-get install libxft-dev sudo apt-get install libxml++2.6-dev sudo apt-get install perl sudo apt-get install python +sudo apt-get install python3-setuptools sudo apt-get install python-lxml sudo apt-get install texinfo sudo apt-get install time @@ -46,3 +47,5 @@ sudo apt-get install g++-9 sudo apt-get install gcc-9 sudo apt-get install clang-6.0 sudo apt-get install clang-8 +# Python dependencies +python3 -m pip install -r /home/runner/work/SOFA/SOFA/OpenFPGA/requirements.txt diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml index 479c05b..eca3577 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml @@ -103,7 +103,8 @@ 10e-12 - + + @@ -288,7 +289,7 @@ - + diff --git a/DOC/requirements.txt b/DOC/requirements.txt index 0d6c023..314f232 100644 --- a/DOC/requirements.txt +++ b/DOC/requirements.txt @@ -6,7 +6,7 @@ #recommonmark #Handle references in bibtex format -sphinxcontrib-bibtex +sphinxcontrib-bibtex<2.0.0 sphinxcontrib-tikz #Work-around bug "AttributeError: 'Values' object has no attribute 'character_level_inline_markup'" with docutils 0.13.1 diff --git a/DOC/source/datasheet/index.rst b/DOC/source/datasheet/index.rst index ef6404f..1aaddde 100644 --- a/DOC/source/datasheet/index.rst +++ b/DOC/source/datasheet/index.rst @@ -7,3 +7,5 @@ sofa_hd/index qlsofa_hd/index + + sofa_chd/index diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_embedded_io_schematic.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_embedded_io_schematic.svg deleted file mode 100644 index 75482cb..0000000 --- a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_embedded_io_schematic.svg +++ /dev/null @@ -1,253 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Produced by OmniGraffle 7.18\n2020-11-19 23:01:04 +0000 - - switch - - boundary - - - - - - - - - - - - - CCFF_IN - - - - - - - - CCFF_OUT - - - - - - - - FPGA Fabric - - - - - SoC Interface - - - - - - - - base - - - SOC_IN - - - - - SOC_OUT - - - - - - - - - - - - - - - - - FPGA_OUT - - - - - FPGA_IN - - - - - - - - - - - - SOC_DIR - - - - - - - - - - - - - - - - - - - - - - - - - - FF - - - - - - - - - - - - PROG_CLK - - - - - - - - - - - IO_ISOL_N - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - output pin - - - - - input pin - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fabric_scan_chain.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fabric_scan_chain.svg deleted file mode 100644 index 0bf9cc5..0000000 --- a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fabric_scan_chain.svg +++ /dev/null @@ -1,320 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Produced by OmniGraffle 7.18\n2020-11-17 17:11:00 +0000 - - fpga_arch - - legend - - - - - - - FPGA - - - - - - - - x - - - - - - - - y - - - - - chain - - - - - CLB - [1][12] - - - - - - - - SC_HEAD - - - - - - - CLB - [1][11] - - - - - - - - - - - … - - - - - - - CLB - [1][2] - - - - - - - - - - CLB - [1][1] - - - - - - - - - - CLB - [2][12] - - - - - - - - - - CLB - [2][11] - - - - - - - - - - - … - - - - - - - CLB - [2][2] - - - - - - - - - - CLB - [2][1] - - - - - - - - - - - - - CLB - [11][12] - - - - - - - - - - CLB - [11][11] - - - - - - - - - - - … - - - - - - - CLB - [11][2] - - - - - - - - - - CLB - [11][1] - - - - - - - - - - CLB - [12][12] - - - - - - - - - - CLB - [12][11] - - - - - - - - - - - … - - - - - - - CLB - [12][2] - - - - - - - - - - CLB - [12][1] - - - - - - - - - - - … - - - - - SC_TAIL - - - - - … - - - - - … - - - - - … - - - - - … - - - - - diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_arch.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_arch.svg deleted file mode 100644 index 59678b3..0000000 --- a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_arch.svg +++ /dev/null @@ -1,1089 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Produced by OmniGraffle 7.18\n2020-11-17 16:24:14 +0000 - - fpga_arch - - tiles - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - legend - - - Programmable Fabric - - - - - - - - - - - Routing Tracks - - - - - - - - - - Tile - - - - - - - I/O TileA - - - - - - - - - - - - - - I/O TileB - - - - - - - - - - - 12 - - - - - - - - - 12 - - - - - - - - tile_details - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Tile - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Switch - Block - - - - - - - Configurable - Logic - Block - - - - - - - - - - - ... - - - - - ... - - - - - ... - - - - - ... - - - - - ... - - - - - ... - - - - - - - X-direction - Connection - Block - - - - - - - Y-direction - Connection - Block - - - - - - - - - - - diff --git a/DOC/source/datasheet/qlsofa_hd/index.rst b/DOC/source/datasheet/qlsofa_hd/index.rst index 09e8665..b736ea8 100644 --- a/DOC/source/datasheet/qlsofa_hd/index.rst +++ b/DOC/source/datasheet/qlsofa_hd/index.rst @@ -1,4 +1,4 @@ -.. _datasheet_sofa_hd: +.. _datasheet_qlsofa_hd: QLSOFA HD QLSOFA HD diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst index 90d527b..47cc326 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst @@ -8,29 +8,14 @@ Circuit Designs I/O Circuit ^^^^^^^^^^^ -As shown in :numref:`fig_qlsofa_hd_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_qlsofa_hd_fpga_arch`) is an digital I/O cell with +QLSOFA HD FPGA share the same I/O circuit design as SOFA HD FPGA. +See details at :ref:`sofa_hd_circuit_design_io`. -- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized. +.. _sofa_hd_circuit_design_mux: - .. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality! +Multiplexer +^^^^^^^^^^^ -- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid - - - ``SOC_OUT`` port outputs any random signal when the I/O is in input mode - - ``FPGA_IN`` port is driven by any random signal when the I/O is output mode +QLSOFA HD FPGA share the same multiplexer design as SOFA HD FPGA. +See details at :ref:`sofa_hd_circuit_design_mux`. -- An internal configurable memory element to control the direction of I/O cell - -The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where - -- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode - -- When configuration bit (FF output) is logic ``0``, the I/O cell is in output mode - -.. _fig_qlsofa_hd_embedded_io_schematic: - -.. figure:: ./figures/qlsofa_hd_embedded_io_schematic.svg - :scale: 30% - :alt: Schematic of embedded I/O cell used in FPGA - - Schematic of embedded I/O cell used in FPGA diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst index f1d079d..ae457b0 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst @@ -8,21 +8,8 @@ Architecture Floorplan ^^^^^^^^^ - -:numref:`fig_qlsofa_hd_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric. -The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric. -I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`qlsofa_hd_io_resource`). - -.. _fig_qlsofa_hd_fpga_arch: - -.. figure:: ./figures/qlsofa_hd_fpga_arch.svg - :scale: 25% - :alt: Tile-based FPGA architecture - - Tile-based FPGA architecture - - -.. _qlsofa_hd_fpga_arch_tiles: +QLSOFA HD FPGA share the same floroplan as SOFA HD FPGA. +See details at :ref:`sofa_hd_fpga_arch_floorplan`. Tiles ^^^^^ @@ -64,19 +51,5 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra Scan-chain ^^^^^^^^^^ -There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`qlsofa_hd_clb_arch_scan_chain`), as illustrated in :numref:`fig_qlsofa_hd_fabric_scan_chain`. - -When `Test_en` signal is active, users can - -- overwrite the contents of all the D-type flip-flops in the FPGA by feeding signals to the `SC_HEAD` port -- readback the contents of all the D-type flip-flops in the FPGA through the `SC_TAIL` port. - -.. _fig_qlsofa_hd_fabric_scan_chain: - -.. figure:: ./figures/qlsofa_hd_fabric_scan_chain.svg - :scale: 25% - :alt: Built-in scan-chain across FPGA - - Built-in scan-chain across FPGA - - +QLSOFA HD FPGA share the same floroplan as SOFA HD FPGA. +See details at :ref:`sofa_hd_fpga_arch_scan_chain`. diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst index fc2badb..f8cbf4f 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst @@ -6,7 +6,7 @@ I/O Resources Pin Assignment ^^^^^^^^^^^^^^ -The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`. +The QLSOFA HD FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`. Among the 144 I/Os, @@ -26,14 +26,14 @@ Among the 144 I/Os, :scale: 20% :alt: I/O arrangement of FPGA IP - I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface + I/O arrangement of QLSOFA HD FPGA IP: switchable between logic analyzer and wishbone bus interface .. _io_resource_qlsofa_hd_external_io: External I/Os ^^^^^^^^^^^^^ -A SOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os. +A QLSOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os. Full details are summarized in the following table. diff --git a/DOC/source/datasheet/sofa_chd/figures/custom_mux_cells.svg b/DOC/source/datasheet/sofa_chd/figures/custom_mux_cells.svg new file mode 100644 index 0000000..1e2df15 --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/figures/custom_mux_cells.svg @@ -0,0 +1,433 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-12-10 00:31:01 +0000 + + MUX3 + + + Layer 1 + + + + + + + + + + + + + + + + + + + in[2] + + + + + GND + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + V + DD + + + + + + + + in[1] + + + + + GND + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + V + DD + + + + + + + + + + + + + + + + + + + + + + + + + + + + + S[1] + + + + + S[1] + + + + + + + + + + + + + + + + + + + + in[0] + + + + + GND + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + V + DD + + + + + + + + + + + + + + + + + + + + + + + + + + + + + S[0] + + + + + S[0] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + S[2] + + + + + S[2] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + out + + + + + + + + diff --git a/DOC/source/datasheet/sofa_chd/figures/sofa_chd_mux_circuit.svg b/DOC/source/datasheet/sofa_chd/figures/sofa_chd_mux_circuit.svg new file mode 100644 index 0000000..3e1c341 --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/figures/sofa_chd_mux_circuit.svg @@ -0,0 +1,1241 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-12-10 00:13:32 +0000 + + v1.0 + + Arch + + + + + + + + + + Switch Block + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ... + + + + + + + + Routing + Multiplexer + + + + + + + + + Connection Block + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + … + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + Mux + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + out + + + + + + + + + + + + + + + + + in[0] + + + + + in[1] + + + + + in[2] + + + + + + + + + + + + + + in[3] + + + + + in[4] + + + + + in[5] + + + + + + + + + + + + + + in[6] + + + + + in[7] + + + + + GND + + + + + + + + + + + + + + + + + 2to3 Local + Encoder + + + + + + + + + + + + + + + + + + + + + 2to3 Local + Encoder + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + legend + + + + + + + + + + + + + + + + + Configurable Memory + + + + + + + + + + + Routing Tracks + + + + + + + + + Custom MUX3 Cell + + + + + Two-level Multiplexer Design + + + + + + + + diff --git a/DOC/source/datasheet/sofa_chd/index.rst b/DOC/source/datasheet/sofa_chd/index.rst new file mode 100644 index 0000000..a35e5fe --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/index.rst @@ -0,0 +1,16 @@ +.. _datasheet_sofa_chd: + SOFA CHD + +SOFA CHD +-------- + +.. toctree:: + :maxdepth: 2 + + sofa_chd_fpga_arch + + sofa_chd_io_resource + + sofa_chd_clb_arch + + sofa_chd_circuit_design diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_circuit_design.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_circuit_design.rst new file mode 100644 index 0000000..f5cfbaa --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_circuit_design.rst @@ -0,0 +1,42 @@ +.. _sofa_chd_circuit_design: + +Circuit Designs +--------------- + +.. _sofa_chd_circuit_design_io: + +I/O Circuit +^^^^^^^^^^^ + +SOFA CHD FPGA share the same I/O circuit design as SOFA HD FPGA. +See details at :ref:`sofa_hd_circuit_design_io`. + +.. _sofa_hd_circuit_design_mux: + +Multiplexer +^^^^^^^^^^^ + +Routing multiplexer are designed by using a few custom cells based on the Skywater *High-Density* (HD) PDK, as shown in :numref:`fig_sofa_chd_mux_circuit`. +The multiplexer design follows a two-level structure, which is applied to all the routing multiplexers in logic elements, connection blocks and switch blocks across the FPGA fabric. + +.. _fig_sofa_chd_mux_circuit: + +.. figure:: ./figures/sofa_chd_mux_circuit.svg + :scale: 30% + :alt: Schematic of multiplexer design in SOFA CHD FPGA + + Schematic of multiplexer design in SOFA CHD FPGA + +Each primitive in the two-level structure could be a 2/3/4-input custom cell, depending on the input size of the routing multiplexer. +Each custom cell is built with input inverters and transmission-gates. +For instance, :numref:`fig_sofa_chd_custom_mux_cells` shows the transistor-level design of a 3-input custom cell. + +.. _fig_sofa_chd_custom_mux_cells: + +.. figure:: ./figures/custom_mux_cells.svg + :scale: 40% + :alt: Detailed schematic of a 3-input custom cell in SOFA CHD FPGA + + Detailed schematic of a 3-input custom cell in SOFA CHD FPGA + +.. note:: Each routing multiplexer has a dedicated input which is connected to ground (GND) signal. When it is not used, the output will be driven by the ground, working as a constant generator. diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_clb_arch.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_clb_arch.rst new file mode 100644 index 0000000..933fcb5 --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_clb_arch.rst @@ -0,0 +1,7 @@ +.. _sofa_chd_clb_arch: + +Configurable Logic Block +------------------------ + +The SOFA CHD FPGA IP share the same *Configurable Logic Block* (CLB) architecture as QLSOFA HD FPGA IP. +See details at :ref:`qlsofa_hd_clb_arch`. diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_fpga_arch.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_fpga_arch.rst new file mode 100644 index 0000000..2380b03 --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_fpga_arch.rst @@ -0,0 +1,7 @@ +.. _sofa_chd_fpga_arch: + +Architecture +------------- + +SOFA CHD FPGA share the same architecture as QLSOFA HD FPGA. +See full details at :ref:`qlsofa_hd_fpga_arch`. diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_io_resource.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_io_resource.rst new file mode 100644 index 0000000..5b4b96f --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_io_resource.rst @@ -0,0 +1,7 @@ +.. _sofa_chd_io_resource: + +I/O Resources +------------- + +The SOFA CHD FPGA IP share the same I/O resource arragement as QLSOFA HD FPGA IP. +See details at :ref:`qlsofa_hd_io_resource`. diff --git a/DOC/source/datasheet/sofa_hd/figures/sofa_hd_embedded_io_schematic.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_embedded_io_schematic.svg index 75482cb..d2b829b 100644 --- a/DOC/source/datasheet/sofa_hd/figures/sofa_hd_embedded_io_schematic.svg +++ b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_embedded_io_schematic.svg @@ -1,6 +1,6 @@ - + @@ -28,8 +28,8 @@ - Produced by OmniGraffle 7.18\n2020-11-19 23:01:04 +0000 - + Produced by OmniGraffle 7.18\n2020-12-11 18:21:49 +0000 + switch boundary @@ -38,7 +38,7 @@ - + @@ -76,7 +76,7 @@ base - + SOC_IN @@ -86,13 +86,13 @@ - + - + @@ -103,7 +103,7 @@ - + FPGA_IN @@ -111,31 +111,28 @@ - - - - + SOC_DIR - - + + - - + + - + - + - + @@ -158,7 +155,7 @@ - + @@ -169,7 +166,7 @@ - + @@ -179,8 +176,8 @@ - - + + @@ -199,12 +196,12 @@ - - + + - - + + @@ -229,8 +226,8 @@ - - + + @@ -248,6 +245,21 @@ + + + + + + + + + + + + + + + diff --git a/DOC/source/datasheet/sofa_hd/figures/sofa_hd_embedded_io_test_waveform.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_embedded_io_test_waveform.svg new file mode 100644 index 0000000..d5061c6 --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_embedded_io_test_waveform.svg @@ -0,0 +1,4 @@ + + + +CLKIO_ISOL_NFPGA_DIRSOC_DIRSOC_INFPGA_INFPGA_OUTSOC_OUT \ No newline at end of file diff --git a/DOC/source/datasheet/sofa_hd/figures/sofa_hd_mux_circuit.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_mux_circuit.svg new file mode 100644 index 0000000..517196a --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_mux_circuit.svg @@ -0,0 +1,1236 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-12-10 00:13:59 +0000 + + v1.0 + + Arch + + + + + + + + + + Switch Block + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ... + + + + + + + + Routing + Multiplexer + + + + + + + + + Connection Block + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + … + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + Mux + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + in[0] + + + + + in[1] + + + + + in[2] + + + + + in[3] + + + + + in[4] + + + + + in[5] + + + + + in[6] + + + + + GND + + + + + out + + + + + + + + + + + + legend + + + + + + + + + + + + + + + + + Configurable Memory + + + + + + + + + + + Routing Tracks + + + + + + + + + Standard cell MUX2 + + + + + Tree -like Multiplexer Design + + + + + + + + diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst index 3a1d824..b304368 100644 --- a/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst @@ -21,7 +21,7 @@ As shown in :numref:`fig_sofa_hd_embedded_io_schematic`, the I/O circuit used in - An internal configurable memory element to control the direction of I/O cell -The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where +The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC (which requires an active-low signal to enable output directionality), where - When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode @@ -34,3 +34,36 @@ The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, :alt: Schematic of embedded I/O cell used in FPGA Schematic of embedded I/O cell used in FPGA + +:numref:`fig_sofa_hd_embedded_io_test_waveform` shows an example waveform about how the I/O cell works: + +- When ``IO_ISOL_N`` is enabled/disabled +- When operates in input mode +- When operates in output mode + +.. _fig_sofa_hd_embedded_io_test_waveform: + +.. figure:: ./figures/sofa_hd_embedded_io_test_waveform.svg + :scale: 30% + :alt: Schematic of embedded I/O cell used in FPGA + + An example of waveforms of embedded I/O cell used in FPGA + + +.. _sofa_hd_circuit_design_mux: + +Multiplexer +^^^^^^^^^^^ + +Routing multiplexer are designed by using the skywater *High-Density* (HD) 2-input MUX cell, as shown in :numref:`fig_sofa_hd_mux_circuit`. +The tree-like multiplexer design is applied to all the routing multiplexers in logic elements, connection blocks and switch blocks across the FPGA fabric. + +.. _fig_sofa_hd_mux_circuit: + +.. figure:: ./figures/sofa_hd_mux_circuit.svg + :scale: 30% + :alt: Schematic of multiplexer design in SOFA HD FPGA + + Schematic of multiplexer design in SOFA HD FPGA + +.. note:: Each routing multiplexer has a dedicated input which is connected to ground (GND) signal. When it is not used, the output will be driven by the ground, working as a constant generator. diff --git a/DOC/source/device/figures/sofa_motivation.png b/DOC/source/device/figures/sofa_motivation.png new file mode 100644 index 0000000..9486a00 Binary files /dev/null and b/DOC/source/device/figures/sofa_motivation.png differ diff --git a/DOC/source/device/hd_fpga/hd_device_comp.rst b/DOC/source/device/hd_fpga/hd_device_comp.rst index 940efe4..6d0bb33 100644 --- a/DOC/source/device/hd_fpga/hd_device_comp.rst +++ b/DOC/source/device/hd_fpga/hd_device_comp.rst @@ -7,27 +7,27 @@ The High Density (HD) FPGAs are embedded FPGAs built with the Skywater 130nm Hig .. table:: Logic capacity of High Density (HD) FPGA IPs - +-------------------------------+------------+-----------+ - | Resource/Capacity | SOFA HD | QLSOFA HD | - +===============================+============+===========+ - | Look-Up Tables [1]_ | 1152 | 1152 | - +-------------------------------+------------+-----------+ - | Flip-flops | 2304 | 2304 | - +-------------------------------+------------+-----------+ - | Soft Adders [2]_ | N/A | 1152 | - +-------------------------------+------------+-----------+ - | Routing Channel Width [3]_ | 40 | 60 | - +-------------------------------+------------+-----------+ - | Max. Configuration Speed [4]_ | 50MHz | 50MHz | - +-------------------------------+------------+-----------+ - | Max. Operating Speed [4]_ | 50MHz | 50 MHz | - +-------------------------------+------------+-----------+ - | User I/O Pins [5]_ | 144 | 144 | - +-------------------------------+------------+-----------+ - | Max. I/O Speed [4]_ | 33MHz | 33 MHz | - +-------------------------------+------------+-----------+ - | Core Voltage | 1.8V | 1.8V | - +-------------------------------+------------+-----------+ + +-------------------------------+------------+-----------+----------+ + | Resource/Capacity | SOFA HD | QLSOFA HD | SOFA CHD | + +===============================+============+===========+==========+ + | Look-Up Tables [1]_ | 1152 | 1152 | 1152 | + +-------------------------------+------------+-----------+----------+ + | Flip-flops | 2304 | 2304 | 2304 | + +-------------------------------+------------+-----------+----------+ + | Soft Adders [2]_ | N/A | 1152 | 1152 | + +-------------------------------+------------+-----------+----------+ + | Routing Channel Width [3]_ | 40 | 60 | 60 | + +-------------------------------+------------+-----------+----------+ + | Max. Configuration Speed [4]_ | 50MHz | 50MHz | 50MHz | + +-------------------------------+------------+-----------+----------+ + | Max. Operating Speed [4]_ | 50MHz | 50 MHz | 50MHz | + +-------------------------------+------------+-----------+----------+ + | User I/O Pins [5]_ | 144 | 144 | 144 | + +-------------------------------+------------+-----------+----------+ + | Max. I/O Speed [4]_ | 33MHz | 33MHz | 33MHz | + +-------------------------------+------------+-----------+----------+ + | Core Voltage | 1.8V | 1.8V | 1.8V | + +-------------------------------+------------+-----------+----------+ .. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT. diff --git a/DOC/source/device/introduction.rst b/DOC/source/device/introduction.rst index 24f163e..f0eb135 100644 --- a/DOC/source/device/introduction.rst +++ b/DOC/source/device/introduction.rst @@ -3,9 +3,18 @@ Introduction ------------ -All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII. -All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK. -The devices are embedded FPGA IPs, which are designed to interface the caravel SoC interface. -We aims to empower embedded applications with its low-cost design approach but high-density architecture. -Operating temperature ranging from 0 :math:`^\circ C` to 85 :math:`^\circ C` +*Skywater Opensource FpgA* (SOFA) is a fully open-source embedded FPGA IP library, from the architecture description to production ready layouts. +As illustrated in :numref:`fig_sofa_motivation`, SOFA IPs are designed through the Skywater 130nm PDK, OpenFPGA framework and Synopsys IC Compiler II. +The runtime of the design flow for each IP is within 24 hours. + +All the SOFA FPGAs are designed to interface the Caravel SoC interface. +We aims to empower embedded applications with its low-cost design approach but high-density architecture. + +.. _fig_sofa_motivation: + +.. figure:: ./figures/sofa_motivation.png + :scale: 15% + :alt: 24-hour FPGA IP development: from PDK to production-ready layout + + 24-hour FPGA IP development: from PDK to production-ready layout diff --git a/DOC/source/index.rst b/DOC/source/index.rst index cbf7d6e..9600c26 100644 --- a/DOC/source/index.rst +++ b/DOC/source/index.rst @@ -3,8 +3,8 @@ You can adapt this file completely to your liking, but it should at least contain the root `toctree` directive. -Welcome to SKywater-OpenFPGA documentation! -=========================================== +Welcome to SOFA documentation! +============================== .. toctree:: :caption: Device Family diff --git a/HDL/common/caravel_gl_include_netlists.v b/HDL/common/caravel_gl_include_netlists.v new file mode 100644 index 0000000..16a6b40 --- /dev/null +++ b/HDL/common/caravel_gl_include_netlists.v @@ -0,0 +1,41 @@ +//------------------------------------------- +// A file to include all the dependency HDL codes +// required by Caravel gate-level netlists +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +`define USE_POWER_PINS 1 + +//////////////////////////////////// +// Skywater standard cell netlists +// I/O cells +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v" +// High density cells +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v" +// High voltage cells +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v" + +// Gate-level netlists +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/DFFRAM.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/caravel.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/chip_io.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/digital_pll.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/mgmt_core.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/storage.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/user_id_programming.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/user_proj_example.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/user_project_wrapper.v" + +// Use RTL codes for the following module as the gate-level netlists are buggy +// in handling power pins +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/defines.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/mgmt_protect.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/mgmt_protect_hv.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/gpio_control_block.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/simple_por.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v" diff --git a/HDL/common/custom_cell_mux_primitive_generator.py b/HDL/common/custom_cell_mux_primitive_generator.py index 50131a2..39099a9 100644 --- a/HDL/common/custom_cell_mux_primitive_generator.py +++ b/HDL/common/custom_cell_mux_primitive_generator.py @@ -58,9 +58,9 @@ custom_nlist = open(args.output_verilog, "w") ####################################################################### # A function to generate Verilog codes for a MUX3 custom cell # Given an input index -def generate_verilog_codes_custom_cell_mux3(first_input_index, instance_index): +def generate_verilog_codes_custom_cell_mux3(first_input_index, instance_index, add_inverter_follower): lines = [] - + # Instanciate a 3-input MUX cell lines.append("\tscs8hd_muxinv3_1 scs8hd_muxinv3_1_" + str(instance_index) + "(") lines.append("\t .Q1(in[" + str(first_input_index) + "]),") lines.append("\t .Q2(in[" + str(first_input_index + 1) + "]),") @@ -71,17 +71,28 @@ def generate_verilog_codes_custom_cell_mux3(first_input_index, instance_index): lines.append("\t .S1B(mem_inv[" + str(first_input_index + 1) + "]),") lines.append("\t .S2(mem[" + str(first_input_index + 2) + "]),") lines.append("\t .S2B(mem_inv[" + str(first_input_index + 2) + "]),") - lines.append("\t .Z(out[0])") + if (add_inverter_follower): + lines.append("\t .Z(out_inv[0])") + else: + lines.append("\t .Z(out[0])") lines.append("\t );") + # Instanciate an inverter follower to pair the MUX cells (which has input inverters) + if (add_inverter_follower): + lines.append("\tsky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower" + str(instance_index) + "(") + lines.append("\t .A(out_inv[0]),") + lines.append("\t .Y(out[0])") + lines.append("\t );") + return lines ####################################################################### # A function to generate Verilog codes for a MUX3 custom cell # Given an input index -def generate_verilog_codes_custom_cell_mux2(first_input_index, instance_index): +def generate_verilog_codes_custom_cell_mux2(first_input_index, instance_index, add_inverter_follower): lines = [] + # Instanciate a 2-input MUX cell lines.append("\tscs8hd_muxinv2_1 scs8hd_muxinv2_1_" + str(instance_index) + "(") lines.append("\t .Q1(in[" + str(first_input_index) + "]),") lines.append("\t .Q2(in[" + str(first_input_index + 1) + "]),") @@ -89,9 +100,19 @@ def generate_verilog_codes_custom_cell_mux2(first_input_index, instance_index): lines.append("\t .S0B(mem_inv[" + str(first_input_index) + "]),") lines.append("\t .S1(mem[" + str(first_input_index + 1) + "]),") lines.append("\t .S1B(mem_inv[" + str(first_input_index + 1) + "]),") - lines.append("\t .Z(out[0])") + if (add_inverter_follower): + lines.append("\t .Z(out_inv[0])") + else: + lines.append("\t .Z(out[0])") lines.append("\t );") + # Instanciate an inverter follower to pair the MUX cells (which has input inverters) + if (add_inverter_follower): + lines.append("\tsky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower" + str(instance_index) + "(") + lines.append("\t .A(out_inv[0]),") + lines.append("\t .Y(out[0])") + lines.append("\t );") + return lines ####################################################################### @@ -116,8 +137,12 @@ def generate_verilog_codes_standard_cell_mux2(first_input_index, instance_index) # In this case, an standard cell will be outputted # - If the memory size is larger than 1, the input size should be the same # as memory size. In this case, we will output custom cells -def write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size): +def write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size, add_inverter_follower): lines = [] + + if (add_inverter_follower): + lines.append("wire [0:0] out_inv;") + if (1 == mem_size): assert(2 == input_size) # Output a standard cell, currently we support HD cell MUX2 @@ -132,17 +157,17 @@ def write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size): # - a few MUX2 cells if (1 == input_size % 2): assert(3 <= input_size) - for line in generate_verilog_codes_custom_cell_mux3(0, 0): + for line in generate_verilog_codes_custom_cell_mux3(0, 0, add_inverter_follower): lines.append(line) for mux2_inst in range(int((input_size - 3) / 2)): - for line in generate_verilog_codes_custom_cell_mux2(3 + 2 * mux2_inst, mux2_inst): + for line in generate_verilog_codes_custom_cell_mux2(3 + 2 * mux2_inst, mux2_inst, add_inverter_follower): lines.append(line) # - If the input size is an even number, we will use # - a few MUX2 cells else: assert (0 == input_size % 2) for mux2_inst in range(int(input_size / 2)): - for line in generate_verilog_codes_custom_cell_mux2(2 * mux2_inst, mux2_inst): + for line in generate_verilog_codes_custom_cell_mux2(2 * mux2_inst, mux2_inst, add_inverter_follower): lines.append(line) # Output lines to file @@ -154,6 +179,7 @@ with open(args.template_netlist, "r") as wp: template_nlist = wp.readlines() # A flag for write the current line or skip output_action = "copy" + mux_structure = "1level" input_size = 0 mem_size = 0 for line_num, curr_line in enumerate(template_nlist): @@ -168,6 +194,12 @@ with open(args.template_netlist, "r") as wp: mem_size = int(re.findall("input(\d+)_mem(\d+)\(", curr_line)[0][1]) assert(input_size > 0) assert(mem_size > 0) + # Find the MUX structure levels + if (re.search("1level", curr_line)): + mux_structure = "1level" + else: + assert(re.search("2level", curr_line)) + mux_structure = "2level" # Change status indicating that we are now inside a module output_action = "copy" @@ -179,7 +211,7 @@ with open(args.template_netlist, "r") as wp: # Reaching the end of the current module # Now output the custom cell instanciation if (curr_line.startswith("endmodule")): - write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size) + write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size, "1level" != mux_structure) output_action = "copy" if ("skip" != output_action): diff --git a/HDL/common/digital_io_hd.v b/HDL/common/digital_io_hd.v index b88390b..e1b6ea9 100644 --- a/HDL/common/digital_io_hd.v +++ b/HDL/common/digital_io_hd.v @@ -37,7 +37,7 @@ module EMBEDDED_IO_HD ( sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (.B_N(IO_ISOL_N), .A(FPGA_DIR), .X(SOC_DIR) - ); + ); // Use drive-strength 4 for a high fan-out from global routing architecture sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR), .Y(SOC_DIR_N)); diff --git a/MSIM/common/run_post_pnr_msim_task.py b/MSIM/common/run_post_pnr_msim_task.py index f0ffff2..3aac9be 100644 --- a/MSIM/common/run_post_pnr_msim_task.py +++ b/MSIM/common/run_post_pnr_msim_task.py @@ -16,6 +16,9 @@ import argparse import logging import subprocess import glob +import threading +import multiprocessing +import run_post_pnr_msim_test ##################################################################### # Initialize logger @@ -64,15 +67,16 @@ num_sim_finished = 0 msim_testrun_script_abspath = os.path.abspath(__file__) msim_testrun_script_abspath = re.sub(os.path.basename(msim_testrun_script_abspath), "run_post_pnr_msim_test.py", msim_testrun_script_abspath) +threads = [] for testbench_file in testbench_files: # Find testbench name testbench_name = re.findall("(\w+)_include_netlists.v", os.path.basename(testbench_file))[0] - cmd = "python3 " + msim_testrun_script_abspath \ - + " --verilog_testbench " + testbench_file \ - + " --project_path " + msim_task_dir_abspath + "/" + testbench_name \ - + " --testbench_name " + testbench_name + "_autocheck_top_tb" - subprocess.run(cmd, shell=True, check=True) - num_sim_finished += 1 + process = multiprocessing.Process(target=run_post_pnr_msim_test.run_msim, args=(testbench_file, msim_task_dir_abspath + "/" + testbench_name, testbench_name + "_autocheck_top_tb",)) + process.start() + threads.append(process) + +for process in threads: + process.join() logging.info("Done") -logging.info("Finish " + str(num_sim_finished) + " ModelSim simulations") +logging.info("Finish " + str(len(threads)) + " ModelSim simulations") diff --git a/MSIM/common/run_post_pnr_msim_test.py b/MSIM/common/run_post_pnr_msim_test.py index 83942d4..ee465fb 100644 --- a/MSIM/common/run_post_pnr_msim_test.py +++ b/MSIM/common/run_post_pnr_msim_test.py @@ -6,6 +6,7 @@ # - Analyze output log files and return succeed or failure ##################################################################### +import sys import os from os.path import dirname, abspath, isfile import shutil @@ -18,138 +19,150 @@ import subprocess # Initialize logger ##################################################################### logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.INFO) +##################################################################### +# Main function of this script, so that it can be called by other scripts +##################################################################### +def main(args): + ##################################################################### + # Parse the options + ##################################################################### + parser = argparse.ArgumentParser(description='Run ModelSim verification for a testbench') + parser.add_argument('--verilog_testbench', required=True, + help='Specify the file path for the Verilog testbench as input') + parser.add_argument('--project_path', required=True, + help='Specify the file path to create the ModelSim project') + parser.add_argument('--testbench_name', required=True, + help='Specify the top-level module of the testbench') + args = parser.parse_args(args) + + run_msim(args.verilog_testbench, args.project_path, args.testbench_name) ##################################################################### -# Parse the options +# Main function of this script, so that it can be called by other scripts ##################################################################### -parser = argparse.ArgumentParser(description='Run ModelSim verification for a testbench') -parser.add_argument('--verilog_testbench', required=True, - help='Specify the file path for the Verilog testbench as input') -parser.add_argument('--project_path', required=True, - help='Specify the file path to create the ModelSim project') -parser.add_argument('--testbench_name', required=True, - help='Specify the top-level module of the testbench') -args = parser.parse_args() +def run_msim(verilog_testbench, project_path, testbench_name): + ##################################################################### + # Check options: + # - Input testbench file must be valid + # Otherwise, error out + # - If the modelsim project path does not exist, create it + ##################################################################### + if not isfile(verilog_testbench): + logging.error("Invalid Verilog testbench: " + verilog_testbench + "\nFile does not exist!\n") + exit(1) + + project_abs_path = os.path.abspath(project_path) + if not os.path.isdir(project_abs_path): + logging.debug("Creating ModelSim project directory : " + project_abs_path + " ...\n") + os.makedirs(project_abs_path, exist_ok=True) + logging.debug("Done\n") + + ##################################################################### + # Create the Tcl script for Modelsim + ##################################################################### + # Get modelsim process tcl file path + msim_proc_tcl_path = os.path.abspath(__file__) + msim_proc_tcl_path = re.sub(os.path.basename(msim_proc_tcl_path), "modelsim_proc.tcl", msim_proc_tcl_path) + if not isfile(msim_proc_tcl_path): + logging.error("Invalid process script for ModelSim: " + msim_proc_tcl_path + "\nFile does not exist!\n") + exit(1) + + # Create output file handler + tcl_file_path = project_abs_path + "/" + os.path.basename(testbench_name) + ".tcl" + logging.debug("Generating Tcl script for ModelSim: " + tcl_file_path) + tcl_file = open(tcl_file_path, "w") + + # A string buffer to write tcl content + tcl_lines = [] + + tcl_lines.append("echo \"==============================\"") + tcl_lines.append("pwd") + tcl_lines.append("echo \"==============================\"") + tcl_lines.append("\n") + tcl_lines.append("set project_name " + testbench_name) + tcl_lines.append("set top_tb " + testbench_name) + tcl_lines.append("\n") + tcl_lines.append("set project_path \"" + project_abs_path + "\"") + tcl_lines.append("set verilog_files \"" + os.path.abspath(verilog_testbench) + "\"") + tcl_lines.append("\n") + tcl_lines.append("source " + msim_proc_tcl_path) + tcl_lines.append("\n") + tcl_lines.append("try {") + tcl_lines.append("\ttop_create_new_project $project_name $verilog_files $project_path $top_tb") + tcl_lines.append("} finally {") + tcl_lines.append("\tquit") + tcl_lines.append("}") + + for line in tcl_lines: + tcl_file.write(line + "\n") + + tcl_file.close() + logging.debug("Done") + + ##################################################################### + # Run ModelSim simulation + ##################################################################### + curr_dir = os.getcwd() + # Change to the project directory + os.chdir(project_abs_path) + logging.debug("Changed to directory: " + project_abs_path) + + # Run ModelSim + vsim_log_file_path = project_abs_path + "/vsim_run_log" + vsim_bin = "/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/bin/vsim" + vsim_cmd = vsim_bin + " -c -do " + os.path.abspath(tcl_file_path) + " > " + vsim_log_file_path + logging.debug("Running modelsim by : " + vsim_cmd) + subprocess.run(vsim_cmd, shell=True, check=True) + + # Go back to current directory + os.chdir(curr_dir) + + ##################################################################### + # Parse log files and report any errors + ##################################################################### + vsim_log_file = open(vsim_log_file_path, "r") + + # Error counter + num_err = 0 + num_err_lines_found = 0 + verification_passed = False + + for line in vsim_log_file: + # Check errors from self-testing testbench output + if line.startswith("# Simulation finish with") : + num_sim_err = int(re.findall("# Simulation finish with(\s+)(\d+) errors", line)[0][1]) + num_err_lines_found += 1 + if (0 < num_sim_err) : + logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n") + # Add to total errors + num_err += num_sim_err + if line.startswith("# Simulation Failed with") : + print (line) + num_sim_err = int(re.findall("# Simulation Failed with(\s+)(\d+) error\(s\)", line)[0][1]) + num_err_lines_found += 1 + if (0 < num_sim_err) : + logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n") + # Add to total errors + num_err += num_sim_err + # Check total errors by Modelsim + if line.startswith("# Errors:") : + num_msim_err = int(re.findall("# Errors:(\s)(\d+),", line)[0][1]) + num_err_lines_found += 1 + num_err += num_msim_err + + vsim_log_file.close() + + if (0 == num_err_lines_found) : + logging.error("No error lines found!Something wrong in setting up modelsim simulation\n") + elif (0 < num_err) : + logging.error("ModelSim failed with " + str(num_err) + " errors!\n") + else : + verification_passed = True + + if (verification_passed) : + logging.info(testbench_name + "...[Passed]\n") + else : + logging.error(testbench_name + "...[Failed]\n") -##################################################################### -# Check options: -# - Input testbench file must be valid -# Otherwise, error out -# - If the modelsim project path does not exist, create it -##################################################################### -if not isfile(args.verilog_testbench): - logging.error("Invalid Verilog testbench: " + args.verilog_testbench + "\nFile does not exist!\n") - exit(1) - -project_abs_path = os.path.abspath(args.project_path) -if not os.path.isdir(project_abs_path): - logging.debug("Creating ModelSim project directory : " + project_abs_path + " ...\n") - os.makedirs(project_abs_path, exist_ok=True) - logging.debug("Done\n") - -##################################################################### -# Create the Tcl script for Modelsim -##################################################################### -# Get modelsim process tcl file path -msim_proc_tcl_path = os.path.abspath(__file__) -msim_proc_tcl_path = re.sub(os.path.basename(msim_proc_tcl_path), "modelsim_proc.tcl", msim_proc_tcl_path) -if not isfile(msim_proc_tcl_path): - logging.error("Invalid process script for ModelSim: " + msim_proc_tcl_path + "\nFile does not exist!\n") - exit(1) - -# Create output file handler -tcl_file_path = project_abs_path + "/" + os.path.basename(args.testbench_name) + ".tcl" -logging.debug("Generating Tcl script for ModelSim: " + tcl_file_path) -tcl_file = open(tcl_file_path, "w") - -# A string buffer to write tcl content -tcl_lines = [] - -tcl_lines.append("echo \"==============================\"") -tcl_lines.append("pwd") -tcl_lines.append("echo \"==============================\"") -tcl_lines.append("\n") -tcl_lines.append("set project_name " + args.testbench_name) -tcl_lines.append("set top_tb " + args.testbench_name) -tcl_lines.append("\n") -tcl_lines.append("set project_path \"" + project_abs_path + "\"") -tcl_lines.append("set verilog_files \"" + os.path.abspath(args.verilog_testbench) + "\"") -tcl_lines.append("\n") -tcl_lines.append("source " + msim_proc_tcl_path) -tcl_lines.append("\n") -tcl_lines.append("try {") -tcl_lines.append("\ttop_create_new_project $project_name $verilog_files $project_path $top_tb") -tcl_lines.append("} finally {") -tcl_lines.append("\tquit") -tcl_lines.append("}") - -for line in tcl_lines: - tcl_file.write(line + "\n") - -tcl_file.close() -logging.debug("Done") - -##################################################################### -# Run ModelSim simulation -##################################################################### -curr_dir = os.getcwd() -# Change to the project directory -os.chdir(project_abs_path) -logging.debug("Changed to directory: " + project_abs_path) - -# Run ModelSim -vsim_log_file_path = project_abs_path + "/vsim_run_log" -vsim_bin = "/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/bin/vsim" -vsim_cmd = vsim_bin + " -c -do " + os.path.abspath(tcl_file_path) + " > " + vsim_log_file_path -logging.debug("Running modelsim by : " + vsim_cmd) -subprocess.run(vsim_cmd, shell=True, check=True) - -# Go back to current directory -os.chdir(curr_dir) - -##################################################################### -# Parse log files and report any errors -##################################################################### -vsim_log_file = open(vsim_log_file_path, "r") - -# Error counter -num_err = 0 -num_err_lines_found = 0 -verification_passed = False - -for line in vsim_log_file: - # Check errors from self-testing testbench output - if line.startswith("# Simulation finish with") : - num_sim_err = int(re.findall("# Simulation finish with(\s+)(\d+) errors", line)[0][1]) - num_err_lines_found += 1 - if (0 < num_sim_err) : - logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n") - # Add to total errors - num_err += num_sim_err - if line.startswith("# Simulation Failed with") : - print (line) - num_sim_err = int(re.findall("# Simulation Failed with(\s+)(\d+) error\(s\)", line)[0][1]) - num_err_lines_found += 1 - if (0 < num_sim_err) : - logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n") - # Add to total errors - num_err += num_sim_err - # Check total errors by Modelsim - if line.startswith("# Errors:") : - num_msim_err = int(re.findall("# Errors:(\s)(\d+),", line)[0][1]) - num_err_lines_found += 1 - num_err += num_msim_err - -vsim_log_file.close() - -if (0 == num_err_lines_found) : - logging.error("No error lines found!Something wrong in setting up modelsim simulation\n") -elif (0 < num_err) : - logging.error("ModelSim failed with " + str(num_err) + " errors!\n") -else : - verification_passed = True - -if (verification_passed) : - logging.info(args.testbench_name + "...[Passed]\n") -else : - logging.error(args.testbench_name + "...[Failed]\n") +if __name__ == "__main__": + main(sys.argv[1:]) diff --git a/SNPS_DC/README.md b/SNPS_DC/README.md new file mode 100644 index 0000000..99cb9d8 --- /dev/null +++ b/SNPS_DC/README.md @@ -0,0 +1,10 @@ +# Skywater PDK +This directory is the workspace for running Synopsys Design Compiler for FPGA primitives +This required to synthesis decoders in FPGA fabrics +Please keep this directory clean and organize as follows: +- **HDL**: Any HDL to synthesis +- **SCRIPT**: Scripts to enable Design Compile runs +- **RPT**: Report files from Design Compiler runs +- **TEMP**: workspace for Design Compiler projects +- READMD is the only file allowed in the directory, others should be sub-directories. + diff --git a/SNPS_DC/SCRIPTS/dc_template.tcl b/SNPS_DC/SCRIPTS/dc_template.tcl new file mode 100644 index 0000000..2d4f70d --- /dev/null +++ b/SNPS_DC/SCRIPTS/dc_template.tcl @@ -0,0 +1,51 @@ +########################################################## +# Template scripts to synthesize a combinational circuit +# using Design Compiler +# Author: Xifan Tang +# Organization: University of Utah +# Date: September 4th, 2020 +########################################################## + +# Variable declaration +set CTRITICAL_PATH 1; # [ns] + +# Make sure a clean start +remove_design -all + +set DB_FILE "/research/ece/lnis/CAD_TOOLS/DKITS/skywater/skywater-pdk/vendor/synopsys/results/lib/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" + +# Read standard cell library +# Here we consider the Skywater 130nm High Density(HD) cell library +read_db ${DB_FILE} +set target_library ${DB_FILE} +set link_library ${DB_FILE} + +set DESIGN_NAME DESIGN_NAME_VAR +set RTL_NETLIST RTL_NETLIST_VAR + +# Parse the HDL +analyze -f verilog ${RTL_NETLIST} +elaborate ${DESIGN_NAME} + +# Set constraints +# Push to 0 for the minimum area +set_max_area 0 + +# Link to technology library and start compilation +link +compile -map_effort high + +# Output netlist +write -format Verilog -output ../GATE_NETLISTS/${DESIGN_NAME}_post_synth.v + +# Report results +report_unit > ../RPT/${DESIGN_NAME}_unit.rpt +report_area > ../RPT/${DESIGN_NAME}_area.rpt +report_timing > ../RPT/${DESIGN_NAME}_timing.rpt +report_power > ../RPT/${DESIGN_NAME}_power.rpt +report_reference > ../RPT/${DESIGN_NAME}_reference.rpt + +# Finish here +exit + + diff --git a/SNPS_DC/SCRIPTS/run_dc_synth.py b/SNPS_DC/SCRIPTS/run_dc_synth.py new file mode 100644 index 0000000..64cd650 --- /dev/null +++ b/SNPS_DC/SCRIPTS/run_dc_synth.py @@ -0,0 +1,144 @@ +##################################################################### +# Python script to execute Design Compiler Synthesis for a given template tcl script +# This script will +# - Create the tcl script as synthesis recipe +# - Run Design Compiler +# - Analyze output log files and return succeed or failure +##################################################################### + +import sys +import os +from os.path import dirname, abspath, isfile +import shutil +import re +import argparse +import logging +import subprocess + +##################################################################### +# Initialize logger +##################################################################### +logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.INFO) +##################################################################### +# Main function of this script, so that it can be called by other scripts +##################################################################### +def main(args): + ##################################################################### + # Parse the options + ##################################################################### + parser = argparse.ArgumentParser(description='Run Synopsys Design Compiler Synthesis for an input netlist') + parser.add_argument('--rtl_netlist', required=True, + help='Specify the file path to the RTL netlist as input') + parser.add_argument('--recipe_template', required=True, + help='Specify the file path to tcl script contain template synthesis recipe') + parser.add_argument('--technology_library', required=True, + help='Specify the technology library which the RTL netlist will be mapped to') + parser.add_argument('--project_workspace', required=True, + help='Specify the directory to run Design Compiler') + args = parser.parse_args(args) + + run_dc_batch_synth(args.rtl_netlist, args.recipe_template, args.technology_library, args.project_workspace) + +##################################################################### +# A function to execute a single-run of Design Compiler for a RTL design +##################################################################### +def run_dc_synth(rtl_netlist, rtl_design_name, recipe_template, technology_library, project_workspace): + project_abs_path = os.path.abspath(project_workspace) + if not os.path.isdir(project_abs_path): + logging.debug("Creating Design Compiler project directory : " + project_abs_path + " ...\n") + os.makedirs(project_abs_path, exist_ok=True) + logging.debug("Done\n") + + ##################################################################### + # Create the Tcl script for Design Compiler + ##################################################################### + # Get absolute path to the template tcl script, it must be valid + template_tcl_path = os.path.abspath(recipe_template) + assert(isfile(template_tcl_path)) + + # Create output file handler + tcl_file_path = project_abs_path + "/" + os.path.basename(rtl_design_name) + "_dc.tcl" + logging.debug("Generating Tcl script from template recipe: " + tcl_file_path) + + tcl_file = open(tcl_file_path, "w") + + with open(template_tcl_path, "r") as wp: + template_tcl_file = wp.readlines() + for line_num, curr_line in enumerate(template_tcl_file): + line2output = curr_line + # Replace keywords with custom values + line2output = re.sub("TECH_DB_VAR", technology_library, curr_line) + line2output = re.sub("DESIGN_NAME_VAR", rtl_design_name, curr_line) + line2output = re.sub("RTL_NETLIST_VAR", rtl_netlist, curr_line) + # Finished processing + # Output the line + tcl_file.write(line2output) + + tcl_file.close() + logging.debug("Done") + + ##################################################################### + # Run Design Compiler + ##################################################################### + curr_dir = os.getcwd() + # Change to the project directory + os.chdir(project_abs_path) + logging.debug("Changed to directory: " + project_abs_path) + + # Run Design Compiler + dc_log_file_path = project_abs_path + "/" + os.path.basename(rtl_design_name) + "_dc.log" + dc_shell_bin = "dc_shell" + dc_shell_cmd = dc_shell_bin + " -f " + os.path.abspath(tcl_file_path) + " > " + dc_log_file_path + logging.debug("Running Design Compiler by : " + dc_shell_cmd) + subprocess.run(dc_shell_cmd, shell=True, check=True) + + # Go back to current directory + os.chdir(curr_dir) + +##################################################################### +# Main function of this script, so that it can be called by other scripts +##################################################################### +def run_dc_batch_synth(rtl_netlist, recipe_template, technology_library, project_workspace): + ##################################################################### + # Check options: + # - Input files must be valid + # Otherwise, error out + ##################################################################### + if not isfile(rtl_netlist): + logging.error("Invalid RTL netlist: " + rtr_netlist + "\nFile does not exist!\n") + exit(1) + + if not isfile(recipe_template): + logging.error("Invalid recipe template: " + recipe_template + "\nFile does not exist!\n") + exit(1) + + if not isfile(technology_library): + logging.error("Invalid technology library: " + technology_library + "\nFile does not exist!\n") + exit(1) + + ##################################################################### + # Collect all the RTL designs to synthesis from the RTL netlist + ##################################################################### + rtl_design_names = [] + with open(rtl_netlist, "r") as wp: + rtl_file = wp.readlines() + # If a line starts with 'module', it is an RTL design to be synthesized + for line_num, curr_line in enumerate(rtl_file): + if (curr_line.startswith("module")): + # Get the design name + rtl_design_name = re.findall("module(\s+)(\w+)\(", curr_line)[0][1] + rtl_design_names.append(rtl_design_name) + + logging.info("Found " + str(len(rtl_design_names)) + " RTL designs to synthesize") + + # Get absolute path to the template tcl script, it must be valid + rtl_netlist_abs_path = os.path.abspath(rtl_netlist) + assert(isfile(rtl_netlist_abs_path)) + + for rtl_design_name in rtl_design_names: + logging.info("Running Design Compiler for design: " + rtl_design_name) + run_dc_synth(rtl_netlist_abs_path, rtl_design_name, recipe_template, technology_library, project_workspace) + logging.info("Done") + +if __name__ == "__main__": + main(sys.argv[1:]) diff --git a/SNPS_DC/synth_local_encoders.sh b/SNPS_DC/synth_local_encoders.sh new file mode 100644 index 0000000..c9c2c6e --- /dev/null +++ b/SNPS_DC/synth_local_encoders.sh @@ -0,0 +1 @@ +python3 SCRIPTS/run_dc_synth.py --rtl_netlist ../HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/SRC/sub_module/local_encoder.v --recipe_template SCRIPTS/dc_template.tcl --technology_library ../PDK/skywater-pdk/vendor/synopsys/results/lib/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db --project_workspace ./TEMP diff --git a/TESTBENCH/common/caravel_fpga_io_test_include_netlists.v b/TESTBENCH/common/caravel_fpga_io_test_include_netlists.v new file mode 100644 index 0000000..8a43b0f --- /dev/null +++ b/TESTBENCH/common/caravel_fpga_io_test_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:a13d2d93139126328833d3a1433c351eb044b0d4772ba56d214d65017a3e8c37 +size 608 diff --git a/TESTBENCH/common/post_pnr_fpga_cells.v b/TESTBENCH/common/post_pnr_fpga_cells.v index 5bfa734..8b2b063 100644 --- a/TESTBENCH/common/post_pnr_fpga_cells.v +++ b/TESTBENCH/common/post_pnr_fpga_cells.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid 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a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v new file mode 100644 index 0000000..e27d149 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:85f5b1181ea1f96068bf3cf1400a5e91906d5d03e1f24078af2f22cf337d3985 +size 1381 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..ea37b84 --- /dev/null +++ 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