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[HDL] Revert I/O cell back to the current design in GDS

This commit is contained in:
tangxifan 2020-12-11 11:26:46 -07:00
parent 88f522026a
commit 52d98eb7ca
1 changed files with 6 additions and 11 deletions
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17
HDL/common/digital_io_hd.v
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@ -32,30 +32,25 @@ module EMBEDDED_IO_HD (
);
wire SOC_DIR_N;
wire SOC_DIR_WIRE;
// Use drive-strength 4 for a high fan-out from SoC components
sky130_fd_sc_hd__or2b_1 ISOL_EN_GATE (.B_N(IO_ISOL_N),
.A(FPGA_DIR),
.X(SOC_DIR_WIRE)
);
sky130_fd_sc_hd__ebufn_4 DIR_PROTECT_GATE (.TE_B(SOC_DIR),
.A(SOC_DIR),
.Z(SOC_DIR)
);
.X(SOC_DIR)
);
// Use drive-strength 4 for a high fan-out from global routing architecture
sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR_WIRE), .Y(SOC_DIR_N));
sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR), .Y(SOC_DIR_N));
sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE (.TE_B(SOC_DIR_N),
.A(SOC_IN),
.Z(FPGA_IN)
);
);
// Use drive-strength 4 for a potential high fan-out from SoC components
sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE (.TE_B(SOC_DIR_WIRE),
sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE (.TE_B(SOC_DIR),
.A(FPGA_OUT),
.Z(SOC_OUT)
);
);
endmodule