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[HDL] Bug fix in VSS port naming

This commit is contained in:
tangxifan 2020-12-16 13:40:09 -07:00
parent 3b56703c35
commit 3897c18ebe
1 changed files with 1 additions and 1 deletions
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2
HDL/common/user_project_wrapper.v
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@ -70,7 +70,7 @@ module user_project_wrapper #(
.vssd1(vssd1), // User area 1 digital ground
.vssd2(vssd2), // User area 2 digital ground
.VDD(vccd1),
.VCC(vssd1),
.VSS(vssd1),
`endif
// MGMT core clock and reset