From 3897c18ebe87708d3be80876d402923b098312fb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 16 Dec 2020 13:40:09 -0700
Subject: [PATCH] [HDL] Bug fix in VSS port naming

---
 HDL/common/user_project_wrapper.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/HDL/common/user_project_wrapper.v b/HDL/common/user_project_wrapper.v
index 53fa9c4..1ae9b2d 100644
--- a/HDL/common/user_project_wrapper.v
+++ b/HDL/common/user_project_wrapper.v
@@ -70,7 +70,7 @@ module user_project_wrapper #(
 	.vssd1(vssd1),	// User area 1 digital ground
 	.vssd2(vssd2),	// User area 2 digital ground
     .VDD(vccd1),
-    .VCC(vssd1),
+    .VSS(vssd1),
     `endif
 
 	// MGMT core clock and reset