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Merge pull request #63 from lnis-uofu/xt_dev 

Fine-tune architecture file to be consistent in port naming of SOFA CHD
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tangxifan 2020-12-09 14:05:20 -07:00 committed by GitHub
parent 0c761ebc05 e7fd8e7d92
commit 5a567644db
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2 changed files with 5 additions and 4 deletions
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5
ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
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@ -103,7 +103,8 @@
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
<!-- Trick OpenFPGA to avoid auto-generating TGATE modules, which are not used in PnR -->
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/fd_hd_mux_custom_cells_tt.v">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
@ -288,7 +289,7 @@
</direct_connection>
<tile_annotations>
<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
<global_port name="reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
<global_port name="Reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
</tile_annotations>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->

BIN
TESTBENCH/common/post_pnr_fpga_cells.v (Stored with Git LFS)
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