From 73622b1df50a28f351f0316d19b2971725ada5a7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 9 Dec 2020 12:12:14 -0700
Subject: [PATCH 1/2] [TESTBENCH] Add more cells that are used by post-PNR CHD
 FPGA

---
 TESTBENCH/common/post_pnr_fpga_cells.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/TESTBENCH/common/post_pnr_fpga_cells.v b/TESTBENCH/common/post_pnr_fpga_cells.v
index 5bfa734..8b2b063 100644
--- a/TESTBENCH/common/post_pnr_fpga_cells.v
+++ b/TESTBENCH/common/post_pnr_fpga_cells.v
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:89b4703e97499ddd03efb70998f547462d7a8fa5d27e2c2d2af132b2050e195d
-size 7942
+oid sha256:13373f025cd88fee0174c4e7a6121fafd658ac735c112267e55f989f60c882f3
+size 8407

From e7fd8e7d92af619626689cad149cb92cd5b5e725 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 9 Dec 2020 12:12:40 -0700
Subject: [PATCH 2/2] [Arch] Fine-tune architecture file to be consistent in
 port naming as post-PnR netlist

---
 ...n_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
index 479c05b..eca3577 100644
--- a/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_customhd_cc_openfpga.xml
@@ -103,7 +103,8 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+    <!--  Trick OpenFPGA to avoid auto-generating TGATE modules, which are not used in PnR -->
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/fd_hd_mux_custom_cells_tt.v">
       <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
       <device_technology device_model_name="logic"/>
       <input_buffer exist="false"/>
@@ -288,7 +289,7 @@
   </direct_connection>
   <tile_annotations>
     <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
-    <global_port name="reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
+    <global_port name="Reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
   </tile_annotations>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->