Merge pull request #64 from lnis-uofu/xt_dev

Release of Testbenches for SOFA CHD version and Documentation Update
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tangxifan 2020-12-09 20:55:06 -07:00 committed by GitHub
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34 changed files with 3100 additions and 1747 deletions

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sofa_hd/index
qlsofa_hd/index
sofa_chd/index

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@ -1,4 +1,4 @@
.. _datasheet_sofa_hd:
.. _datasheet_qlsofa_hd:
QLSOFA HD
QLSOFA HD

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@ -8,29 +8,14 @@ Circuit Designs
I/O Circuit
^^^^^^^^^^^
As shown in :numref:`fig_qlsofa_hd_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_qlsofa_hd_fpga_arch`) is an digital I/O cell with
QLSOFA HD FPGA share the same I/O circuit design as SOFA HD FPGA.
See details at :ref:`sofa_hd_circuit_design_io`.
- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized.
.. _sofa_hd_circuit_design_mux:
.. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality!
Multiplexer
^^^^^^^^^^^
- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid
- ``SOC_OUT`` port outputs any random signal when the I/O is in input mode
- ``FPGA_IN`` port is driven by any random signal when the I/O is output mode
QLSOFA HD FPGA share the same multiplexer design as SOFA HD FPGA.
See details at :ref:`sofa_hd_circuit_design_mux`.
- An internal configurable memory element to control the direction of I/O cell
The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where
- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode
- When configuration bit (FF output) is logic ``0``, the I/O cell is in output mode
.. _fig_qlsofa_hd_embedded_io_schematic:
.. figure:: ./figures/qlsofa_hd_embedded_io_schematic.svg
:scale: 30%
:alt: Schematic of embedded I/O cell used in FPGA
Schematic of embedded I/O cell used in FPGA

View File

@ -8,21 +8,8 @@ Architecture
Floorplan
^^^^^^^^^
:numref:`fig_qlsofa_hd_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric.
The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric.
I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`qlsofa_hd_io_resource`).
.. _fig_qlsofa_hd_fpga_arch:
.. figure:: ./figures/qlsofa_hd_fpga_arch.svg
:scale: 25%
:alt: Tile-based FPGA architecture
Tile-based FPGA architecture
.. _qlsofa_hd_fpga_arch_tiles:
QLSOFA HD FPGA share the same floroplan as SOFA HD FPGA.
See details at :ref:`sofa_hd_fpga_arch_floorplan`.
Tiles
^^^^^
@ -64,19 +51,5 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra
Scan-chain
^^^^^^^^^^
There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`qlsofa_hd_clb_arch_scan_chain`), as illustrated in :numref:`fig_qlsofa_hd_fabric_scan_chain`.
When `Test_en` signal is active, users can
- overwrite the contents of all the D-type flip-flops in the FPGA by feeding signals to the `SC_HEAD` port
- readback the contents of all the D-type flip-flops in the FPGA through the `SC_TAIL` port.
.. _fig_qlsofa_hd_fabric_scan_chain:
.. figure:: ./figures/qlsofa_hd_fabric_scan_chain.svg
:scale: 25%
:alt: Built-in scan-chain across FPGA
Built-in scan-chain across FPGA
QLSOFA HD FPGA share the same floroplan as SOFA HD FPGA.
See details at :ref:`sofa_hd_fpga_arch_scan_chain`.

View File

@ -6,7 +6,7 @@ I/O Resources
Pin Assignment
^^^^^^^^^^^^^^
The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`.
The QLSOFA HD FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`.
Among the 144 I/Os,
@ -26,14 +26,14 @@ Among the 144 I/Os,
:scale: 20%
:alt: I/O arrangement of FPGA IP
I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface
I/O arrangement of QLSOFA HD FPGA IP: switchable between logic analyzer and wishbone bus interface
.. _io_resource_qlsofa_hd_external_io:
External I/Os
^^^^^^^^^^^^^
A SOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os.
A QLSOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os.
Full details are summarized in the following table.

View File

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.. _datasheet_sofa_chd:
SOFA CHD
SOFA CHD
--------
.. toctree::
:maxdepth: 2
sofa_chd_fpga_arch
sofa_chd_io_resource
sofa_chd_clb_arch
sofa_chd_circuit_design

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.. _sofa_chd_circuit_design:
Circuit Designs
---------------
.. _sofa_chd_circuit_design_io:
I/O Circuit
^^^^^^^^^^^
SOFA CHD FPGA share the same I/O circuit design as SOFA HD FPGA.
See details at :ref:`sofa_hd_circuit_design_io`.
.. _sofa_hd_circuit_design_mux:
Multiplexer
^^^^^^^^^^^
Routing multiplexer are designed by using a few custom cells based on the Skywater *High-Density* (HD) PDK, as shown in :numref:`fig_sofa_chd_mux_circuit`.
The multiplexer design follows a two-level structure, which is applied to all the routing multiplexers in logic elements, connection blocks and switch blocks across the FPGA fabric.
.. _fig_sofa_chd_mux_circuit:
.. figure:: ./figures/sofa_chd_mux_circuit.svg
:scale: 30%
:alt: Schematic of multiplexer design in SOFA CHD FPGA
Schematic of multiplexer design in SOFA CHD FPGA
Each primitive in the two-level structure could be a 2/3/4-input custom cell, depending on the input size of the routing multiplexer.
Each custom cell is built with input inverters and transmission-gates.
For instance, :numref:`fig_sofa_chd_custom_mux_cells` shows the transistor-level design of a 3-input custom cell.
.. _fig_sofa_chd_custom_mux_cells:
.. figure:: ./figures/custom_mux_cells.svg
:scale: 40%
:alt: Detailed schematic of a 3-input custom cell in SOFA CHD FPGA
Detailed schematic of a 3-input custom cell in SOFA CHD FPGA
.. note:: Each routing multiplexer has a dedicated input which is connected to ground (GND) signal. When it is not used, the output will be driven by the ground, working as a constant generator.

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.. _sofa_chd_clb_arch:
Configurable Logic Block
------------------------
The SOFA CHD FPGA IP share the same *Configurable Logic Block* (CLB) architecture as QLSOFA HD FPGA IP.
See details at :ref:`qlsofa_hd_clb_arch`.

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.. _sofa_chd_fpga_arch:
Architecture
-------------
SOFA CHD FPGA share the same architecture as QLSOFA HD FPGA.
See full details at :ref:`qlsofa_hd_fpga_arch`.

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.. _sofa_chd_io_resource:
I/O Resources
-------------
The SOFA CHD FPGA IP share the same I/O resource arragement as QLSOFA HD FPGA IP.
See details at :ref:`qlsofa_hd_io_resource`.

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@ -34,3 +34,21 @@ The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC,
:alt: Schematic of embedded I/O cell used in FPGA
Schematic of embedded I/O cell used in FPGA
.. _sofa_hd_circuit_design_mux:
Multiplexer
^^^^^^^^^^^
Routing multiplexer are designed by using the skywater *High-Density* (HD) 2-input MUX cell, as shown in :numref:`fig_sofa_hd_mux_circuit`.
The tree-like multiplexer design is applied to all the routing multiplexers in logic elements, connection blocks and switch blocks across the FPGA fabric.
.. _fig_sofa_hd_mux_circuit:
.. figure:: ./figures/sofa_hd_mux_circuit.svg
:scale: 30%
:alt: Schematic of multiplexer design in SOFA HD FPGA
Schematic of multiplexer design in SOFA HD FPGA
.. note:: Each routing multiplexer has a dedicated input which is connected to ground (GND) signal. When it is not used, the output will be driven by the ground, working as a constant generator.

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@ -7,27 +7,27 @@ The High Density (HD) FPGAs are embedded FPGAs built with the Skywater 130nm Hig
.. table:: Logic capacity of High Density (HD) FPGA IPs
+-------------------------------+------------+-----------+
| Resource/Capacity | SOFA HD | QLSOFA HD |
+===============================+============+===========+
| Look-Up Tables [1]_ | 1152 | 1152 |
+-------------------------------+------------+-----------+
| Flip-flops | 2304 | 2304 |
+-------------------------------+------------+-----------+
| Soft Adders [2]_ | N/A | 1152 |
+-------------------------------+------------+-----------+
| Routing Channel Width [3]_ | 40 | 60 |
+-------------------------------+------------+-----------+
| Max. Configuration Speed [4]_ | 50MHz | 50MHz |
+-------------------------------+------------+-----------+
| Max. Operating Speed [4]_ | 50MHz | 50 MHz |
+-------------------------------+------------+-----------+
| User I/O Pins [5]_ | 144 | 144 |
+-------------------------------+------------+-----------+
| Max. I/O Speed [4]_ | 33MHz | 33 MHz |
+-------------------------------+------------+-----------+
| Core Voltage | 1.8V | 1.8V |
+-------------------------------+------------+-----------+
+-------------------------------+------------+-----------+----------+
| Resource/Capacity | SOFA HD | QLSOFA HD | SOFA CHD |
+===============================+============+===========+==========+
| Look-Up Tables [1]_ | 1152 | 1152 | 1152 |
+-------------------------------+------------+-----------+----------+
| Flip-flops | 2304 | 2304 | 2304 |
+-------------------------------+------------+-----------+----------+
| Soft Adders [2]_ | N/A | 1152 | 1152 |
+-------------------------------+------------+-----------+----------+
| Routing Channel Width [3]_ | 40 | 60 | 60 |
+-------------------------------+------------+-----------+----------+
| Max. Configuration Speed [4]_ | 50MHz | 50MHz | 50MHz |
+-------------------------------+------------+-----------+----------+
| Max. Operating Speed [4]_ | 50MHz | 50 MHz | 50MHz |
+-------------------------------+------------+-----------+----------+
| User I/O Pins [5]_ | 144 | 144 | 144 |
+-------------------------------+------------+-----------+----------+
| Max. I/O Speed [4]_ | 33MHz | 33MHz | 33MHz |
+-------------------------------+------------+-----------+----------+
| Core Voltage | 1.8V | 1.8V | 1.8V |
+-------------------------------+------------+-----------+----------+
.. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT.

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Introduction
------------
All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII.
All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK.
The devices are embedded FPGA IPs, which are designed to interface the caravel SoC interface.
We aims to empower embedded applications with its low-cost design approach but high-density architecture.
Operating temperature ranging from 0 :math:`^\circ C` to 85 :math:`^\circ C`
*Skywater Opensource FpgA* (SOFA) is a fully open-source embedded FPGA IP library, from the architecture description to production ready layouts.
As illustrated in :numref:`fig_sofa_motivation`, SOFA IPs are designed through the Skywater 130nm PDK, OpenFPGA framework and Synopsys IC Compiler II.
The runtime of the design flow for each IP is within 24 hours.
All the SOFA FPGAs are designed to interface the Caravel SoC interface.
We aims to empower embedded applications with its low-cost design approach but high-density architecture.
.. _fig_sofa_motivation:
.. figure:: ./figures/sofa_motivation.png
:scale: 15%
:alt: 24-hour FPGA IP development: from PDK to production-ready layout
24-hour FPGA IP development: from PDK to production-ready layout

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You can adapt this file completely to your liking, but it should at least
contain the root `toctree` directive.
Welcome to SKywater-OpenFPGA documentation!
===========================================
Welcome to SOFA documentation!
==============================
.. toctree::
:caption: Device Family