diff --git a/DOC/source/datasheet/index.rst b/DOC/source/datasheet/index.rst index ef6404f..1aaddde 100644 --- a/DOC/source/datasheet/index.rst +++ b/DOC/source/datasheet/index.rst @@ -7,3 +7,5 @@ sofa_hd/index qlsofa_hd/index + + sofa_chd/index diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_embedded_io_schematic.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_embedded_io_schematic.svg deleted file mode 100644 index 75482cb..0000000 --- a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_embedded_io_schematic.svg +++ /dev/null @@ -1,253 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Produced by OmniGraffle 7.18\n2020-11-19 23:01:04 +0000 - - switch - - boundary - - - - - - - - - - - - - CCFF_IN - - - - - - - - CCFF_OUT - - - - - - - - FPGA Fabric - - - - - SoC Interface - - - - - - - - base - - - SOC_IN - - - - - SOC_OUT - - - - - - - - - - - - - - - - - FPGA_OUT - - - - - FPGA_IN - - - - - - - - - - - - SOC_DIR - - - - - - - - - - - - - - - - - - - - - - - - - - FF - - - - - - - - - - - - PROG_CLK - - - - - - - - - - - IO_ISOL_N - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - output pin - - - - - input pin - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fabric_scan_chain.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fabric_scan_chain.svg deleted file mode 100644 index 0bf9cc5..0000000 --- a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fabric_scan_chain.svg +++ /dev/null @@ -1,320 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Produced by OmniGraffle 7.18\n2020-11-17 17:11:00 +0000 - - fpga_arch - - legend - - - - - - - FPGA - - - - - - - - x - - - - - - - - y - - - - - chain - - - - - CLB - [1][12] - - - - - - - - SC_HEAD - - - - - - - CLB - [1][11] - - - - - - - - - - - - - - - - - - CLB - [1][2] - - - - - - - - - - CLB - [1][1] - - - - - - - - - - CLB - [2][12] - - - - - - - - - - CLB - [2][11] - - - - - - - - - - - - - - - - - - CLB - [2][2] - - - - - - - - - - CLB - [2][1] - - - - - - - - - - - - - CLB - [11][12] - - - - - - - - - - CLB - [11][11] - - - - - - - - - - - - - - - - - - CLB - [11][2] - - - - - - - - - - CLB - [11][1] - - - - - - - - - - CLB - [12][12] - - - - - - - - - - CLB - [12][11] - - - - - - - - - - - - - - - - - - CLB - [12][2] - - - - - - - - - - CLB - [12][1] - - - - - - - - - - - - - - - - SC_TAIL - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_arch.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_arch.svg deleted file mode 100644 index 59678b3..0000000 --- a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_arch.svg +++ /dev/null @@ -1,1089 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Produced by OmniGraffle 7.18\n2020-11-17 16:24:14 +0000 - - fpga_arch - - tiles - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - legend - - - Programmable Fabric - - - - - - - - - - - Routing Tracks - - - - - - - - - - Tile - - - - - - - I/O TileA - - - - - - - - - - - - - - I/O TileB - - - - - - - - - - - 12 - - - - - - - - - 12 - - - - - - - - tile_details - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Tile - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Switch - Block - - - - - - - Configurable - Logic - Block - - - - - - - - - - - ... - - - - - ... - - - - - ... - - - - - ... - - - - - ... - - - - - ... - - - - - - - X-direction - Connection - Block - - - - - - - Y-direction - Connection - Block - - - - - - - - - - - diff --git a/DOC/source/datasheet/qlsofa_hd/index.rst b/DOC/source/datasheet/qlsofa_hd/index.rst index 09e8665..b736ea8 100644 --- a/DOC/source/datasheet/qlsofa_hd/index.rst +++ b/DOC/source/datasheet/qlsofa_hd/index.rst @@ -1,4 +1,4 @@ -.. _datasheet_sofa_hd: +.. _datasheet_qlsofa_hd: QLSOFA HD QLSOFA HD diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst index 90d527b..47cc326 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst @@ -8,29 +8,14 @@ Circuit Designs I/O Circuit ^^^^^^^^^^^ -As shown in :numref:`fig_qlsofa_hd_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_qlsofa_hd_fpga_arch`) is an digital I/O cell with +QLSOFA HD FPGA share the same I/O circuit design as SOFA HD FPGA. +See details at :ref:`sofa_hd_circuit_design_io`. -- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized. +.. _sofa_hd_circuit_design_mux: - .. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality! +Multiplexer +^^^^^^^^^^^ -- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid - - - ``SOC_OUT`` port outputs any random signal when the I/O is in input mode - - ``FPGA_IN`` port is driven by any random signal when the I/O is output mode +QLSOFA HD FPGA share the same multiplexer design as SOFA HD FPGA. +See details at :ref:`sofa_hd_circuit_design_mux`. -- An internal configurable memory element to control the direction of I/O cell - -The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where - -- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode - -- When configuration bit (FF output) is logic ``0``, the I/O cell is in output mode - -.. _fig_qlsofa_hd_embedded_io_schematic: - -.. figure:: ./figures/qlsofa_hd_embedded_io_schematic.svg - :scale: 30% - :alt: Schematic of embedded I/O cell used in FPGA - - Schematic of embedded I/O cell used in FPGA diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst index f1d079d..ae457b0 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst @@ -8,21 +8,8 @@ Architecture Floorplan ^^^^^^^^^ - -:numref:`fig_qlsofa_hd_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric. -The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric. -I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`qlsofa_hd_io_resource`). - -.. _fig_qlsofa_hd_fpga_arch: - -.. figure:: ./figures/qlsofa_hd_fpga_arch.svg - :scale: 25% - :alt: Tile-based FPGA architecture - - Tile-based FPGA architecture - - -.. _qlsofa_hd_fpga_arch_tiles: +QLSOFA HD FPGA share the same floroplan as SOFA HD FPGA. +See details at :ref:`sofa_hd_fpga_arch_floorplan`. Tiles ^^^^^ @@ -64,19 +51,5 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra Scan-chain ^^^^^^^^^^ -There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`qlsofa_hd_clb_arch_scan_chain`), as illustrated in :numref:`fig_qlsofa_hd_fabric_scan_chain`. - -When `Test_en` signal is active, users can - -- overwrite the contents of all the D-type flip-flops in the FPGA by feeding signals to the `SC_HEAD` port -- readback the contents of all the D-type flip-flops in the FPGA through the `SC_TAIL` port. - -.. _fig_qlsofa_hd_fabric_scan_chain: - -.. figure:: ./figures/qlsofa_hd_fabric_scan_chain.svg - :scale: 25% - :alt: Built-in scan-chain across FPGA - - Built-in scan-chain across FPGA - - +QLSOFA HD FPGA share the same floroplan as SOFA HD FPGA. +See details at :ref:`sofa_hd_fpga_arch_scan_chain`. diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst index fc2badb..f8cbf4f 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst @@ -6,7 +6,7 @@ I/O Resources Pin Assignment ^^^^^^^^^^^^^^ -The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`. +The QLSOFA HD FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`. Among the 144 I/Os, @@ -26,14 +26,14 @@ Among the 144 I/Os, :scale: 20% :alt: I/O arrangement of FPGA IP - I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface + I/O arrangement of QLSOFA HD FPGA IP: switchable between logic analyzer and wishbone bus interface .. _io_resource_qlsofa_hd_external_io: External I/Os ^^^^^^^^^^^^^ -A SOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os. +A QLSOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os. Full details are summarized in the following table. diff --git a/DOC/source/datasheet/sofa_chd/figures/custom_mux_cells.svg b/DOC/source/datasheet/sofa_chd/figures/custom_mux_cells.svg new file mode 100644 index 0000000..1e2df15 --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/figures/custom_mux_cells.svg @@ -0,0 +1,433 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-12-10 00:31:01 +0000 + + MUX3 + + + Layer 1 + + + + + + + + + + + + + + + + + + + in[2] + + + + + GND + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + V + DD + + + + + + + + in[1] + + + + + GND + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + V + DD + + + + + + + + + + + + + + + + + + + + + + + + + + + + + S[1] + + + + + S[1] + + + + + + + + + + + + + + + + + + + + in[0] + + + + + GND + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + V + DD + + + + + + + + + + + + + + + + + + + + + + + + + + + + + S[0] + + + + + S[0] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + S[2] + + + + + S[2] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + out + + + + + + + + diff --git a/DOC/source/datasheet/sofa_chd/figures/sofa_chd_mux_circuit.svg b/DOC/source/datasheet/sofa_chd/figures/sofa_chd_mux_circuit.svg new file mode 100644 index 0000000..3e1c341 --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/figures/sofa_chd_mux_circuit.svg @@ -0,0 +1,1241 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-12-10 00:13:32 +0000 + + v1.0 + + Arch + + + + + + + + + + Switch Block + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ... + + + + + + + + Routing + Multiplexer + + + + + + + + + Connection Block + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + Mux + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + out + + + + + + + + + + + + + + + + + in[0] + + + + + in[1] + + + + + in[2] + + + + + + + + + + + + + + in[3] + + + + + in[4] + + + + + in[5] + + + + + + + + + + + + + + in[6] + + + + + in[7] + + + + + GND + + + + + + + + + + + + + + + + + 2to3 Local + Encoder + + + + + + + + + + + + + + + + + + + + + 2to3 Local + Encoder + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + legend + + + + + + + + + + + + + + + + + Configurable Memory + + + + + + + + + + + Routing Tracks + + + + + + + + + Custom MUX3 Cell + + + + + Two-level Multiplexer Design + + + + + + + + diff --git a/DOC/source/datasheet/sofa_chd/index.rst b/DOC/source/datasheet/sofa_chd/index.rst new file mode 100644 index 0000000..a35e5fe --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/index.rst @@ -0,0 +1,16 @@ +.. _datasheet_sofa_chd: + SOFA CHD + +SOFA CHD +-------- + +.. toctree:: + :maxdepth: 2 + + sofa_chd_fpga_arch + + sofa_chd_io_resource + + sofa_chd_clb_arch + + sofa_chd_circuit_design diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_circuit_design.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_circuit_design.rst new file mode 100644 index 0000000..f5cfbaa --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_circuit_design.rst @@ -0,0 +1,42 @@ +.. _sofa_chd_circuit_design: + +Circuit Designs +--------------- + +.. _sofa_chd_circuit_design_io: + +I/O Circuit +^^^^^^^^^^^ + +SOFA CHD FPGA share the same I/O circuit design as SOFA HD FPGA. +See details at :ref:`sofa_hd_circuit_design_io`. + +.. _sofa_hd_circuit_design_mux: + +Multiplexer +^^^^^^^^^^^ + +Routing multiplexer are designed by using a few custom cells based on the Skywater *High-Density* (HD) PDK, as shown in :numref:`fig_sofa_chd_mux_circuit`. +The multiplexer design follows a two-level structure, which is applied to all the routing multiplexers in logic elements, connection blocks and switch blocks across the FPGA fabric. + +.. _fig_sofa_chd_mux_circuit: + +.. figure:: ./figures/sofa_chd_mux_circuit.svg + :scale: 30% + :alt: Schematic of multiplexer design in SOFA CHD FPGA + + Schematic of multiplexer design in SOFA CHD FPGA + +Each primitive in the two-level structure could be a 2/3/4-input custom cell, depending on the input size of the routing multiplexer. +Each custom cell is built with input inverters and transmission-gates. +For instance, :numref:`fig_sofa_chd_custom_mux_cells` shows the transistor-level design of a 3-input custom cell. + +.. _fig_sofa_chd_custom_mux_cells: + +.. figure:: ./figures/custom_mux_cells.svg + :scale: 40% + :alt: Detailed schematic of a 3-input custom cell in SOFA CHD FPGA + + Detailed schematic of a 3-input custom cell in SOFA CHD FPGA + +.. note:: Each routing multiplexer has a dedicated input which is connected to ground (GND) signal. When it is not used, the output will be driven by the ground, working as a constant generator. diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_clb_arch.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_clb_arch.rst new file mode 100644 index 0000000..933fcb5 --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_clb_arch.rst @@ -0,0 +1,7 @@ +.. _sofa_chd_clb_arch: + +Configurable Logic Block +------------------------ + +The SOFA CHD FPGA IP share the same *Configurable Logic Block* (CLB) architecture as QLSOFA HD FPGA IP. +See details at :ref:`qlsofa_hd_clb_arch`. diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_fpga_arch.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_fpga_arch.rst new file mode 100644 index 0000000..2380b03 --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_fpga_arch.rst @@ -0,0 +1,7 @@ +.. _sofa_chd_fpga_arch: + +Architecture +------------- + +SOFA CHD FPGA share the same architecture as QLSOFA HD FPGA. +See full details at :ref:`qlsofa_hd_fpga_arch`. diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_io_resource.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_io_resource.rst new file mode 100644 index 0000000..5b4b96f --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_io_resource.rst @@ -0,0 +1,7 @@ +.. _sofa_chd_io_resource: + +I/O Resources +------------- + +The SOFA CHD FPGA IP share the same I/O resource arragement as QLSOFA HD FPGA IP. +See details at :ref:`qlsofa_hd_io_resource`. diff --git a/DOC/source/datasheet/sofa_hd/figures/sofa_hd_mux_circuit.svg b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_mux_circuit.svg new file mode 100644 index 0000000..517196a --- /dev/null +++ b/DOC/source/datasheet/sofa_hd/figures/sofa_hd_mux_circuit.svg @@ -0,0 +1,1236 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-12-10 00:13:59 +0000 + + v1.0 + + Arch + + + + + + + + + + Switch Block + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ... + + + + + + + + Routing + Multiplexer + + + + + + + + + Connection Block + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4-LUT + + + + + + + + + + + in3 + + + + + in0 + + + + + in1 + + + + + in2 + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[0] + + + + + + + + + M + U + X + + + + + + + + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + out[1] + + + + + + + + + LUT4_out + + + + + + + + + + + + + + LUT3_out[0] + + + + + LUT3_out[1] + + + + + + + + scin + + + + + + + + + + + scout + + + + + + + + + + + + + + + + + + + + regin + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + + + regout + + + + + CLK + + + + + + + + + + + + + + + + + + + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + M + U + X + + + + + + + + + + + + + + + + Mux + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + in[0] + + + + + in[1] + + + + + in[2] + + + + + in[3] + + + + + in[4] + + + + + in[5] + + + + + in[6] + + + + + GND + + + + + out + + + + + + + + + + + + legend + + + + + + + + + + + + + + + + + Configurable Memory + + + + + + + + + + + Routing Tracks + + + + + + + + + Standard cell MUX2 + + + + + Tree -like Multiplexer Design + + + + + + + + diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst index 3a1d824..3ef3230 100644 --- a/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_circuit_design.rst @@ -34,3 +34,21 @@ The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, :alt: Schematic of embedded I/O cell used in FPGA Schematic of embedded I/O cell used in FPGA + +.. _sofa_hd_circuit_design_mux: + +Multiplexer +^^^^^^^^^^^ + +Routing multiplexer are designed by using the skywater *High-Density* (HD) 2-input MUX cell, as shown in :numref:`fig_sofa_hd_mux_circuit`. +The tree-like multiplexer design is applied to all the routing multiplexers in logic elements, connection blocks and switch blocks across the FPGA fabric. + +.. _fig_sofa_hd_mux_circuit: + +.. figure:: ./figures/sofa_hd_mux_circuit.svg + :scale: 30% + :alt: Schematic of multiplexer design in SOFA HD FPGA + + Schematic of multiplexer design in SOFA HD FPGA + +.. note:: Each routing multiplexer has a dedicated input which is connected to ground (GND) signal. When it is not used, the output will be driven by the ground, working as a constant generator. diff --git a/DOC/source/device/figures/sofa_motivation.png b/DOC/source/device/figures/sofa_motivation.png new file mode 100644 index 0000000..9486a00 Binary files /dev/null and b/DOC/source/device/figures/sofa_motivation.png differ diff --git a/DOC/source/device/hd_fpga/hd_device_comp.rst b/DOC/source/device/hd_fpga/hd_device_comp.rst index 940efe4..6d0bb33 100644 --- a/DOC/source/device/hd_fpga/hd_device_comp.rst +++ b/DOC/source/device/hd_fpga/hd_device_comp.rst @@ -7,27 +7,27 @@ The High Density (HD) FPGAs are embedded FPGAs built with the Skywater 130nm Hig .. table:: Logic capacity of High Density (HD) FPGA IPs - +-------------------------------+------------+-----------+ - | Resource/Capacity | SOFA HD | QLSOFA HD | - +===============================+============+===========+ - | Look-Up Tables [1]_ | 1152 | 1152 | - +-------------------------------+------------+-----------+ - | Flip-flops | 2304 | 2304 | - +-------------------------------+------------+-----------+ - | Soft Adders [2]_ | N/A | 1152 | - +-------------------------------+------------+-----------+ - | Routing Channel Width [3]_ | 40 | 60 | - +-------------------------------+------------+-----------+ - | Max. Configuration Speed [4]_ | 50MHz | 50MHz | - +-------------------------------+------------+-----------+ - | Max. Operating Speed [4]_ | 50MHz | 50 MHz | - +-------------------------------+------------+-----------+ - | User I/O Pins [5]_ | 144 | 144 | - +-------------------------------+------------+-----------+ - | Max. I/O Speed [4]_ | 33MHz | 33 MHz | - +-------------------------------+------------+-----------+ - | Core Voltage | 1.8V | 1.8V | - +-------------------------------+------------+-----------+ + +-------------------------------+------------+-----------+----------+ + | Resource/Capacity | SOFA HD | QLSOFA HD | SOFA CHD | + +===============================+============+===========+==========+ + | Look-Up Tables [1]_ | 1152 | 1152 | 1152 | + +-------------------------------+------------+-----------+----------+ + | Flip-flops | 2304 | 2304 | 2304 | + +-------------------------------+------------+-----------+----------+ + | Soft Adders [2]_ | N/A | 1152 | 1152 | + +-------------------------------+------------+-----------+----------+ + | Routing Channel Width [3]_ | 40 | 60 | 60 | + +-------------------------------+------------+-----------+----------+ + | Max. Configuration Speed [4]_ | 50MHz | 50MHz | 50MHz | + +-------------------------------+------------+-----------+----------+ + | Max. Operating Speed [4]_ | 50MHz | 50 MHz | 50MHz | + +-------------------------------+------------+-----------+----------+ + | User I/O Pins [5]_ | 144 | 144 | 144 | + +-------------------------------+------------+-----------+----------+ + | Max. I/O Speed [4]_ | 33MHz | 33MHz | 33MHz | + +-------------------------------+------------+-----------+----------+ + | Core Voltage | 1.8V | 1.8V | 1.8V | + +-------------------------------+------------+-----------+----------+ .. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT. diff --git a/DOC/source/device/introduction.rst b/DOC/source/device/introduction.rst index 24f163e..f0eb135 100644 --- a/DOC/source/device/introduction.rst +++ b/DOC/source/device/introduction.rst @@ -3,9 +3,18 @@ Introduction ------------ -All the FPGA devices in this project are fully open-source, from the architecture description to the physical design outputs, e.g., GDSII. -All the devices are designed through the OpenFPGA framework and the Skywater 130nm PDK. -The devices are embedded FPGA IPs, which are designed to interface the caravel SoC interface. -We aims to empower embedded applications with its low-cost design approach but high-density architecture. -Operating temperature ranging from 0 :math:`^\circ C` to 85 :math:`^\circ C` +*Skywater Opensource FpgA* (SOFA) is a fully open-source embedded FPGA IP library, from the architecture description to production ready layouts. +As illustrated in :numref:`fig_sofa_motivation`, SOFA IPs are designed through the Skywater 130nm PDK, OpenFPGA framework and Synopsys IC Compiler II. +The runtime of the design flow for each IP is within 24 hours. + +All the SOFA FPGAs are designed to interface the Caravel SoC interface. +We aims to empower embedded applications with its low-cost design approach but high-density architecture. + +.. _fig_sofa_motivation: + +.. figure:: ./figures/sofa_motivation.png + :scale: 15% + :alt: 24-hour FPGA IP development: from PDK to production-ready layout + + 24-hour FPGA IP development: from PDK to production-ready layout diff --git a/DOC/source/index.rst b/DOC/source/index.rst index cbf7d6e..9600c26 100644 --- a/DOC/source/index.rst +++ b/DOC/source/index.rst @@ -3,8 +3,8 @@ You can adapt this file completely to your liking, but it should at least contain the root `toctree` directive. -Welcome to SKywater-OpenFPGA documentation! -=========================================== +Welcome to SOFA documentation! +============================== .. toctree:: :caption: Device Family diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v new file mode 100644 index 0000000..e27d149 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:85f5b1181ea1f96068bf3cf1400a5e91906d5d03e1f24078af2f22cf337d3985 +size 1381 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..ea37b84 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7aa52f799ee631d959d1b6c59e8265e9029c8cbe9fe815fd5246080c1250b794 +size 1485 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v new file mode 100644 index 0000000..4f2d3fd --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:feb9721724bd09416b7668d84abf841dcc7805e55c70d098a6edb6601c0f98d3 +size 1377 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..777ac6d --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:983e4841c7ec003427faacb444ac6f70d44f44d42b63da875e66339182a8c81a +size 1481 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v new file mode 100644 index 0000000..f1189e3 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b5787e2a130f304b78e0befa5a84943ef0bfe5d95336d1fe01f516fca63f85a8 +size 1369 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..b553d71 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:79dd997c27286dbc5a868f683eca4392b3f04b358d425f02878a63656bf2ddff +size 1473 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v new file mode 100644 index 0000000..ac118c1 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7fc917a8779c191c7e916af5a6341513d7b341b43eee284d0932414c75c08aaf +size 1321 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..7f1732f --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d6c23fdce319f8b4e5cf60e07d89aaf83b7479fb1076220d13e894e7627d69bd +size 1495 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v new file mode 100644 index 0000000..1182769 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1f3a008a9118f5b619a8c0a2f88830fb596db5d0a7d7a4cf8c36f24832e2b216 +size 1375 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v new file mode 100644 index 0000000..84f9214 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:02e6b21df8939982ee211d8ed61ccb7f6ceb31fa903b2c2c0d9c25971062fb1b +size 1385 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..96eaa84 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:37c31aee9713b1ec359dd5636668defb6220ab6cc8885eee2810b6b359b4a0f7 +size 1489 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v new file mode 100644 index 0000000..296749a --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:01cf35ae46aa3f5b4b4f4033461c558876b9317832db844d3ffe841439208e58 +size 1320 diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..2a2fd2a --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:003df834b79a1294510fe7f0a081e9a987557f92878eff24bbb28bfb441b4beb +size 1494