mirror of https://github.com/lnis-uofu/SOFA.git
[Testbench] Start building caravel testbench
This commit is contained in:
tangxifan
parent
e24d643cbd
commit
f5d78fc0fa
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#ifndef _STRIVE_H_
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#define _STRIVE_H_
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#include <stdint.h>
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#include <stdbool.h>
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// a pointer to this is a null pointer, but the compiler does not
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// know that because "sram" is a linker symbol from sections.lds.
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extern uint32_t sram;
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// Pointer to firmware flash routines
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extern uint32_t flashio_worker_begin;
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extern uint32_t flashio_worker_end;
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// Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
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#define reg_rw_block0 (*(volatile uint32_t*)0x01000000)
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#define reg_rw_block1 (*(volatile uint32_t*)0x01100000)
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#define reg_ro_block0 (*(volatile uint32_t*)0x02000000)
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// UART (0x2000_0000)
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#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
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#define reg_uart_data (*(volatile uint32_t*)0x20000004)
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#define reg_uart_enable (*(volatile uint32_t*)0x20000008)
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// GPIO (0x2100_0000)
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#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
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#define reg_gpio_ena (*(volatile uint32_t*)0x21000004)
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#define reg_gpio_pu (*(volatile uint32_t*)0x21000008)
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#define reg_gpio_pd (*(volatile uint32_t*)0x2100000c)
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// Logic Analyzer (0x2200_0000)
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#define reg_la0_data (*(volatile uint32_t*)0x25000000)
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#define reg_la1_data (*(volatile uint32_t*)0x25000004)
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#define reg_la2_data (*(volatile uint32_t*)0x25000008)
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#define reg_la3_data (*(volatile uint32_t*)0x2500000c)
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#define reg_la0_ena (*(volatile uint32_t*)0x25000010)
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#define reg_la1_ena (*(volatile uint32_t*)0x25000014)
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#define reg_la2_ena (*(volatile uint32_t*)0x25000018)
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#define reg_la3_ena (*(volatile uint32_t*)0x2500001c)
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// User Project Control (0x2300_0000)
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#define reg_mprj_xfer (*(volatile uint32_t*)0x26000000)
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#define reg_mprj_pwr (*(volatile uint32_t*)0x26000004)
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#define reg_mprj_datal (*(volatile uint32_t*)0x26000008)
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#define reg_mprj_datah (*(volatile uint32_t*)0x2600000c)
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#define reg_mprj_io_0 (*(volatile uint32_t*)0x26000020)
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#define reg_mprj_io_1 (*(volatile uint32_t*)0x26000024)
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#define reg_mprj_io_2 (*(volatile uint32_t*)0x26000028)
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#define reg_mprj_io_3 (*(volatile uint32_t*)0x2600002c)
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#define reg_mprj_io_4 (*(volatile uint32_t*)0x26000030)
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#define reg_mprj_io_5 (*(volatile uint32_t*)0x26000034)
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#define reg_mprj_io_6 (*(volatile uint32_t*)0x26000038)
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#define reg_mprj_io_7 (*(volatile uint32_t*)0x2600003c)
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#define reg_mprj_io_8 (*(volatile uint32_t*)0x26000040)
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#define reg_mprj_io_9 (*(volatile uint32_t*)0x26000044)
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#define reg_mprj_io_10 (*(volatile uint32_t*)0x26000048)
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#define reg_mprj_io_11 (*(volatile uint32_t*)0x2600004c)
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#define reg_mprj_io_12 (*(volatile uint32_t*)0x26000050)
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#define reg_mprj_io_13 (*(volatile uint32_t*)0x26000054)
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#define reg_mprj_io_14 (*(volatile uint32_t*)0x26000058)
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#define reg_mprj_io_15 (*(volatile uint32_t*)0x2600005c)
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#define reg_mprj_io_16 (*(volatile uint32_t*)0x26000060)
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#define reg_mprj_io_17 (*(volatile uint32_t*)0x26000064)
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#define reg_mprj_io_18 (*(volatile uint32_t*)0x26000068)
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#define reg_mprj_io_19 (*(volatile uint32_t*)0x2600006c)
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#define reg_mprj_io_20 (*(volatile uint32_t*)0x26000070)
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#define reg_mprj_io_21 (*(volatile uint32_t*)0x26000074)
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#define reg_mprj_io_22 (*(volatile uint32_t*)0x26000078)
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#define reg_mprj_io_23 (*(volatile uint32_t*)0x2600007c)
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#define reg_mprj_io_24 (*(volatile uint32_t*)0x26000080)
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#define reg_mprj_io_25 (*(volatile uint32_t*)0x26000084)
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#define reg_mprj_io_26 (*(volatile uint32_t*)0x26000088)
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#define reg_mprj_io_27 (*(volatile uint32_t*)0x2600008c)
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#define reg_mprj_io_28 (*(volatile uint32_t*)0x26000090)
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#define reg_mprj_io_29 (*(volatile uint32_t*)0x26000094)
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#define reg_mprj_io_30 (*(volatile uint32_t*)0x26000098)
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#define reg_mprj_io_31 (*(volatile uint32_t*)0x2600009c)
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#define reg_mprj_io_32 (*(volatile uint32_t*)0x260000a0)
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#define reg_mprj_io_33 (*(volatile uint32_t*)0x260000a4)
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#define reg_mprj_io_34 (*(volatile uint32_t*)0x260000a8)
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#define reg_mprj_io_35 (*(volatile uint32_t*)0x260000ac)
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#define reg_mprj_io_36 (*(volatile uint32_t*)0x260000b0)
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#define reg_mprj_io_37 (*(volatile uint32_t*)0x260000b4)
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// User Project Slaves (0x3000_0000)
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#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
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// Flash Control SPI Configuration (2D00_0000)
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#define reg_spictrl (*(volatile uint32_t*)0x2d000000)
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// Bit fields for Flash SPI control
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#define FLASH_BITBANG_IO0 0x00000001
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#define FLASH_BITBANG_IO1 0x00000002
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#define FLASH_BITBANG_CLK 0x00000010
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#define FLASH_BITBANG_CSB 0x00000020
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#define FLASH_BITBANG_OEB0 0x00000100
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#define FLASH_BITBANG_OEB1 0x00000200
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#define FLASH_ENABLE 0x80000000
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// Counter-Timer 0 Configuration
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#define reg_timer0_config (*(volatile uint32_t*)0x22000000)
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#define reg_timer0_value (*(volatile uint32_t*)0x22000004)
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#define reg_timer0_data (*(volatile uint32_t*)0x22000008)
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// Counter-Timer 1 Configuration
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#define reg_timer1_config (*(volatile uint32_t*)0x23000000)
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#define reg_timer1_value (*(volatile uint32_t*)0x23000004)
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#define reg_timer1_data (*(volatile uint32_t*)0x23000008)
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// Bit fields for Counter-timer configuration
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#define TIMER_ENABLE 0x01
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#define TIMER_ONESHOT 0x02
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#define TIMER_UPCOUNT 0x04
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#define TIMER_CHAIN 0x08
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#define TIMER_IRQ_ENABLE 0x10
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// SPI Master Configuration
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#define reg_spimaster_config (*(volatile uint32_t*)0x24000000)
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#define reg_spimaster_data (*(volatile uint32_t*)0x24000004)
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// Bit fields for SPI master configuration
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#define SPI_MASTER_DIV_MASK 0x00ff
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#define SPI_MASTER_MLB 0x0100
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#define SPI_MASTER_INV_CSB 0x0200
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#define SPI_MASTER_INV_CLK 0x0400
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#define SPI_MASTER_MODE_1 0x0800
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#define SPI_MASTER_STREAM 0x1000
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#define SPI_MASTER_ENABLE 0x2000
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#define SPI_MASTER_IRQ_ENABLE 0x4000
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#define SPI_HOUSEKEEPING_CONN 0x8000
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// System Area (0x2F00_0000)
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#define reg_power_good (*(volatile uint32_t*)0x2F000000)
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#define reg_clk_out_dest (*(volatile uint32_t*)0x2F000004)
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#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000008)
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#define reg_irq_source (*(volatile uint32_t*)0x2F00000C)
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// Bit fields for reg_power_good
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#define USER1_VCCD_POWER_GOOD 0x01
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#define USER2_VCCD_POWER_GOOD 0x02
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#define USER1_VDDA_POWER_GOOD 0x04
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#define USER2_VDDA_POWER_GOOD 0x08
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// Bit fields for reg_clk_out_dest
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#define CLOCK1_MONITOR 0x01
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#define CLOCK2_MONITOR 0x02
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// Bit fields for reg_irq_source
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#define IRQ7_SOURCE 0x01
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#define IRQ8_SOURCE 0x02
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// Individual bit fields for the GPIO pad control
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#define MGMT_ENABLE 0x0001
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#define OUTPUT_DISABLE 0x0002
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#define HOLD_OVERRIDE 0x0004
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#define INPUT_DISABLE 0x0008
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#define MODE_SELECT 0x0010
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#define ANALOG_ENABLE 0x0020
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#define ANALOG_SELECT 0x0040
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#define ANALOG_POLARITY 0x0080
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#define SLOW_SLEW_MODE 0x0100
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#define TRIPPOINT_SEL 0x0200
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#define DIGITAL_MODE_MASK 0x1c00
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// Useful GPIO mode values
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#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
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#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0803
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#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c03
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#define GPIO_MODE_MGMT_STD_OUTPUT 0x1809
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#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
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#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0802
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#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c02
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#define GPIO_MODE_USER_STD_OUTPUT 0x1808
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// --------------------------------------------------------
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#endif
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@ -0,0 +1,58 @@
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MEMORY {
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FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x400000 /* 4MB */
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RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x0400 /* 256 words (1 KB) */
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}
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SECTIONS {
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/* The program code and other data goes into FLASH */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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*(.srodata) /* .srodata sections (constants, strings, etc.) */
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*(.srodata*) /* .srodata*sections (constants, strings, etc.) */
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. = ALIGN(4);
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_etext = .; /* define a global symbol at end of code */
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_sidata = _etext; /* This is used by the startup to initialize data */
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} >FLASH
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/* Initialized data section */
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.data : AT ( _sidata )
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{
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. = ALIGN(4);
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_sdata = .;
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_ram_start = .;
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. = ALIGN(4);
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*(.data)
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*(.data*)
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*(.sdata)
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*(.sdata*)
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. = ALIGN(4);
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_edata = .;
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} >RAM
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/* Uninitialized data section */
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.bss :
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{
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. = ALIGN(4);
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_sbss = .;
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*(.bss)
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*(.bss*)
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*(.sbss)
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*(.sbss*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .;
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} >RAM
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/* Define the start of the heap */
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.heap :
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{
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. = ALIGN(4);
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_heap_start = .;
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} >RAM
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}
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@ -0,0 +1,159 @@
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.section .text
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start:
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# zero-initialize register file
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addi x1, zero, 0
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# x2 (sp) is initialized by reset
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addi x3, zero, 0
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addi x4, zero, 0
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addi x5, zero, 0
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addi x6, zero, 0
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addi x7, zero, 0
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addi x8, zero, 0
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addi x9, zero, 0
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addi x10, zero, 0
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addi x11, zero, 0
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addi x12, zero, 0
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addi x13, zero, 0
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addi x14, zero, 0
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addi x15, zero, 0
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addi x16, zero, 0
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addi x17, zero, 0
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addi x18, zero, 0
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addi x19, zero, 0
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addi x20, zero, 0
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addi x21, zero, 0
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addi x22, zero, 0
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addi x23, zero, 0
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addi x24, zero, 0
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addi x25, zero, 0
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addi x26, zero, 0
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addi x27, zero, 0
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addi x28, zero, 0
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addi x29, zero, 0
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addi x30, zero, 0
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addi x31, zero, 0
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# zero initialize scratchpad memory
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# setmemloop:
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# sw zero, 0(x1)
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# addi x1, x1, 4
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# blt x1, sp, setmemloop
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# copy data section
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la a0, _sidata
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la a1, _sdata
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la a2, _edata
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bge a1, a2, end_init_data
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loop_init_data:
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lw a3, 0(a0)
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sw a3, 0(a1)
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addi a0, a0, 4
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addi a1, a1, 4
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blt a1, a2, loop_init_data
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end_init_data:
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# zero-init bss section
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la a0, _sbss
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la a1, _ebss
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bge a0, a1, end_init_bss
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loop_init_bss:
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sw zero, 0(a0)
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addi a0, a0, 4
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blt a0, a1, loop_init_bss
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end_init_bss:
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# call main
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call main
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loop:
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j loop
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.global flashio_worker_begin
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.global flashio_worker_end
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.balign 4
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flashio_worker_begin:
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# a0 ... data pointer
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# a1 ... data length
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# a2 ... optional WREN cmd (0 = disable)
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# address of SPI ctrl reg
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li t0, 0x28000000
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# Set CS high, IO0 is output
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li t1, 0x120
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sh t1, 0(t0)
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# Enable Manual SPI Ctrl
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sb zero, 3(t0)
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# Send optional WREN cmd
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beqz a2, flashio_worker_L1
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li t5, 8
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andi t2, a2, 0xff
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flashio_worker_L4:
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srli t4, t2, 7
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sb t4, 0(t0)
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ori t4, t4, 0x10
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sb t4, 0(t0)
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slli t2, t2, 1
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andi t2, t2, 0xff
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addi t5, t5, -1
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bnez t5, flashio_worker_L4
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sb t1, 0(t0)
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# SPI transfer
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flashio_worker_L1:
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# If byte count is zero, we're done
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beqz a1, flashio_worker_L3
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# Set t5 to count down 32 bits
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li t5, 32
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# Load t2 from address a0 (4 bytes)
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lw t2, 0(a0)
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flashio_worker_LY:
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# Set t6 to count down 8 bits
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li t6, 8
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flashio_worker_L2:
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# Clock out the bit (msb first) on IO0 and read bit in from IO1
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srli t4, t2, 31
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sb t4, 0(t0)
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ori t4, t4, 0x10
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sb t4, 0(t0)
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lbu t4, 0(t0)
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andi t4, t4, 2
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srli t4, t4, 1
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slli t2, t2, 1
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or t2, t2, t4
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# Decrement 32 bit count
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addi t5, t5, -1
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bnez t5, flashio_worker_LX
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sw t2, 0(a0)
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addi a0, a0, 4
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lw t2, 0(a0)
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flashio_worker_LX:
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addi t6, t6, -1
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bnez t6, flashio_worker_L2
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addi a1, a1, -1
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bnez a1, flashio_worker_LY
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beqz t5, flashio_worker_L3
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sw t2, 0(a0)
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flashio_worker_L3:
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# Back to MEMIO mode
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li t1, 0x80
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sb t1, 3(t0)
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ret
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.balign 4
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flashio_worker_end:
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@ -0,0 +1,30 @@
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FIRMWARE_PATH = ../common
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GCC_PATH?=/var/tmp/xtang/riscv32i/bin
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GCC_PREFIX?=riscv32-unknown-elf
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.SUFFIXES:
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PATTERN = scff_test_caravel
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all: ${PATTERN:=.hex}
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hex: ${PATTERN:=.hex}
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%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
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${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
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|
||||
%.hex: %.elf
|
||||
${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
|
||||
# to fix flash base address
|
||||
sed -i 's/@10000000/@00000000/g' $@
|
||||
|
||||
%.bin: %.elf
|
||||
${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
|
||||
|
||||
# ---- Clean ----
|
||||
|
||||
clean:
|
||||
rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
|
||||
|
||||
.PHONY: clean hex all
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
#include "../common/defs.h"
|
||||
|
||||
/*
|
||||
* Scan-chain Test:
|
||||
* - Configures directions for control ports
|
||||
* +==========+===============+===========+
|
||||
* | GPIO | Functionality | Direction |
|
||||
* +==========+===============+===========+
|
||||
* | GPIO[0] | TEST_EN | input |
|
||||
* +----------+---------------+-----------+
|
||||
* | GPIO[1] | IO_ISOL_N | input |
|
||||
* +----------+---------------+-----------+
|
||||
* | GPIO[2] | RESET | input |
|
||||
* +----------+---------------+-----------+
|
||||
* | GPIO[3] | PROG_RESET | input |
|
||||
* +----------+---------------+-----------+
|
||||
* | GPIO[11] | SC_TAIL | output |
|
||||
* +----------+---------------+-----------+
|
||||
* | GPIO[12] | CCFF_HEAD | input |
|
||||
* +----------+---------------+-----------+
|
||||
* | GPIO[25] | MODE_SWITCH) | input |
|
||||
* +----------+---------------+-----------+
|
||||
* | GPIO[26] | SC_HEAD | input |
|
||||
* +----------+---------------+-----------+
|
||||
* | GPIO[35] | CCFF_TAIL | output |
|
||||
* +----------+---------------+-----------+
|
||||
* | GPIO[36] | CLK | input |
|
||||
* +----------+---------------+-----------+
|
||||
* | GPIO[37] | PROG_CLK | input |
|
||||
* +----------+---------------+-----------+
|
||||
*
|
||||
* - Configure FPGA data I/Os to be input
|
||||
*/
|
||||
|
||||
void main() {
|
||||
/*
|
||||
IO Control Registers
|
||||
| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
|
||||
| 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
|
||||
|
||||
Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
|
||||
| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
|
||||
| 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
|
||||
|
||||
|
||||
Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
|
||||
| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
|
||||
| 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
|
||||
*/
|
||||
|
||||
// By default all the I/Os are in input mode
|
||||
// Only specify those should be in output mode
|
||||
reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
|
||||
/* Apply configuration */
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
@00000000
|
||||
93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00
|
||||
13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00
|
||||
13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00
|
||||
13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00
|
||||
13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00
|
||||
13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00
|
||||
13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00
|
||||
13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 85 11
|
||||
93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1
|
||||
11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00
|
||||
63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 71 28
|
||||
01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00
|
||||
A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00
|
||||
23 80 D2 01 93 EE 0E 01 23 80 D2 01 86 03 93 F3
|
||||
F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F
|
||||
00 02 83 23 05 00 A1 4F 93 DE F3 01 23 80 D2 01
|
||||
93 EE 0E 01 23 80 D2 01 83 CE 02 00 93 FE 2E 00
|
||||
93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F 63 17 0F 00
|
||||
23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC
|
||||
FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08
|
||||
A3 81 62 00 82 80 01 00 00 00 41 11 22 C6 00 08
|
||||
B7 07 00 26 93 87 C7 04 09 67 13 07 87 80 98 C3
|
||||
B7 07 00 26 93 87 C7 0A 09 67 13 07 87 80 98 C3
|
||||
B7 07 00 26 05 47 98 C3 01 00 B7 07 00 26 98 43
|
||||
85 47 E3 0C F7 FE 01 00 32 44 41 01 82 80 00 00
|
||||
|
|
@ -0,0 +1,245 @@
|
|||
`timescale 1 ns / 1 ps
|
||||
|
||||
`define POWER_UP_TIME_PERIOD 200
|
||||
`define SOC_SETUP_TIME_PERIOD 2000
|
||||
`define SOC_CLOCK_PERIOD 12.5
|
||||
`define FPGA_CLOCK_PERIOD 12.5
|
||||
|
||||
module scff_test_caravel;
|
||||
reg clock;
|
||||
reg RSTB;
|
||||
reg power1, power2;
|
||||
reg power3, power4;
|
||||
|
||||
wire gpio;
|
||||
wire [37:0] mprj_io;
|
||||
|
||||
// ----- Local wires for control ports of FPGA fabric -----
|
||||
wire [0:0] pReset;
|
||||
reg [0:0] prog_clock_reg;
|
||||
wire [0:0] prog_clk;
|
||||
wire [0:0] Test_en;
|
||||
wire [0:0] Reset;
|
||||
reg [0:0] op_clock_reg;
|
||||
wire [0:0] op_clk;
|
||||
reg [0:0] prog_reset;
|
||||
reg [0:0] greset;
|
||||
|
||||
// ---- Configuration-chain head -----
|
||||
wire [0:0] ccff_head;
|
||||
// ---- Configuration-chain tail -----
|
||||
wire [0:0] ccff_tail;
|
||||
|
||||
// ---- Scan-chain head -----
|
||||
reg [0:0] sc_head;
|
||||
// ---- Scan-chain tail -----
|
||||
wire [0:0] sc_tail;
|
||||
|
||||
wire [0:0] IO_ISOL_N;
|
||||
|
||||
// ----- Counters for error checking -----
|
||||
integer num_clock_cycles = 0;
|
||||
integer num_errors = 0;
|
||||
integer num_checked_points = 0;
|
||||
|
||||
// Indicate when SoC setup phase should be finished
|
||||
reg soc_setup_done = 0;
|
||||
// Indicate when configuration should be finished
|
||||
reg scan_done = 0;
|
||||
|
||||
initial
|
||||
begin
|
||||
scan_done = 1'b0;
|
||||
soc_setup_done = 1'b0;
|
||||
end
|
||||
|
||||
// ----- Begin raw programming clock signal generation -----
|
||||
initial
|
||||
begin
|
||||
prog_clock_reg[0] = 1'b0;
|
||||
end
|
||||
// ----- End raw programming clock signal generation -----
|
||||
|
||||
// ----- Begin raw operating clock signal generation -----
|
||||
initial
|
||||
begin
|
||||
op_clock_reg[0] = 1'b0;
|
||||
end
|
||||
always
|
||||
begin
|
||||
#(`FPGA_CLOCK_PERIOD) op_clock_reg[0] = ~op_clock_reg[0];
|
||||
end
|
||||
// ----- End raw operating clock signal generation -----
|
||||
// ----- Actual operating clock is triggered only when scan_done is enabled -----
|
||||
assign prog_clock[0] = prog_clock_reg[0] & ~greset;
|
||||
assign op_clock[0] = op_clock_reg[0] & ~greset;
|
||||
|
||||
// ----- Begin programming reset signal generation -----
|
||||
initial
|
||||
begin
|
||||
prog_reset[0] = 1'b0;
|
||||
end
|
||||
|
||||
// ----- End programming reset signal generation -----
|
||||
|
||||
// ----- Begin operating reset signal generation -----
|
||||
// ----- Reset signal is disabled always -----
|
||||
initial
|
||||
begin
|
||||
greset[0] = 1'b1;
|
||||
#(`SOC_SETUP_TIME_PERIOD + 2 * `FPGA_CLOCK_PERIOD) greset[0] = 1'b0;
|
||||
end
|
||||
// ----- End operating reset signal generation -----
|
||||
|
||||
// ----- Begin connecting global ports of FPGA fabric to stimuli -----
|
||||
assign op_clk[0] = op_clock[0];
|
||||
assign prog_clk[0] = prog_clock[0];
|
||||
assign pReset[0] = ~prog_reset[0];
|
||||
assign Reset[0] = ~greset[0];
|
||||
assign Test_en[0] = ~greset;
|
||||
assign ccff_head[0] = 1'b0;
|
||||
assign IO_ISOL_N[0] = 1'b0;
|
||||
// ----- End connecting global ports of FPGA fabric to stimuli -----
|
||||
|
||||
assign mprj_io[0] = Test_en;
|
||||
assign mprj_io[1] = IO_ISOL_N;
|
||||
assign mprj_io[2] = Reset;
|
||||
assign mprj_io[3] = pReset;
|
||||
assign mprj_io[12] = ccff_head;
|
||||
assign mprj_io[25] = 1'b0; // Set FPGA to interface logic analyzer by default
|
||||
assign mprj_io[26] = sc_head;
|
||||
assign mprj_io[36] = op_clk;
|
||||
assign mprj_io[37] = prog_clk;
|
||||
|
||||
assign sc_tail = mprj_io[11];
|
||||
assign ccff_tail = mprj_io[35];
|
||||
|
||||
assign mprj_io[10:4] = {7{1'b0}};
|
||||
assign mprj_io[24:13] = {12{1'b0}};
|
||||
assign mprj_io[34:27] = {8{1'b0}};
|
||||
|
||||
// Generate a pulse after operating reset is disabled (in the 2nd clock
|
||||
// cycle). Then the head of scan chain should be always zero
|
||||
always @(negedge op_clock[0]) begin
|
||||
sc_head = 1'b1;
|
||||
if (0 != num_clock_cycles) begin
|
||||
sc_head = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// ----- Count the number of programming cycles -------
|
||||
always @(posedge op_clock[0]) begin
|
||||
num_clock_cycles = num_clock_cycles + 1;
|
||||
// Indicate when scan chain loading is suppose to end
|
||||
if (`FPGA_SCANCHAIN_SIZE + 1 == num_clock_cycles) begin
|
||||
scan_done = 1'b1;
|
||||
end
|
||||
|
||||
// Check the tail of scan-chain when configuration is done
|
||||
if (1'b1 == scan_done) begin
|
||||
// The tail should spit a pulse after configuration is done
|
||||
// So it should be at logic '1' and then pulled down to logic '0'
|
||||
if (0 == num_checked_points) begin
|
||||
if (sc_tail !== 1'b1) begin
|
||||
$display("Error: sc_tail = %b", sc_tail);
|
||||
num_errors = num_errors + 1;
|
||||
end
|
||||
end
|
||||
if (1 <= num_checked_points) begin
|
||||
if (sc_tail !== 1'b0) begin
|
||||
$display("Error: sc_tail = %b", sc_tail);
|
||||
num_errors = num_errors + 1;
|
||||
end
|
||||
end
|
||||
num_checked_points = num_checked_points + 1;
|
||||
end
|
||||
|
||||
if (2 < num_checked_points) begin
|
||||
$display("Simulation finish with %d errors", num_errors);
|
||||
|
||||
// End simulation
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
// External clock is used by default. Make this artificially fast for the
|
||||
// simulation. Normally this would be a slow clock and the digital PLL
|
||||
// would be the fast clock.
|
||||
|
||||
always #(`SOC_CLOCK_PERIOD) clock <= (clock === 1'b0);
|
||||
|
||||
initial begin
|
||||
clock = 0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
RSTB <= 1'b0;
|
||||
soc_setup_done <= 1'b1;
|
||||
#(`SOC_SETUP_TIME_PERIOD);
|
||||
RSTB <= 1'b1; // Release reset
|
||||
soc_setup_done <= 1'b1; // We can start scff test
|
||||
end
|
||||
|
||||
initial begin // Power-up sequence
|
||||
power1 <= 1'b0;
|
||||
power2 <= 1'b0;
|
||||
power3 <= 1'b0;
|
||||
power4 <= 1'b0;
|
||||
#(`POWER_UP_TIME_PERIOD);
|
||||
power1 <= 1'b1;
|
||||
#(`POWER_UP_TIME_PERIOD);
|
||||
power2 <= 1'b1;
|
||||
#(`POWER_UP_TIME_PERIOD);
|
||||
power3 <= 1'b1;
|
||||
#(`POWER_UP_TIME_PERIOD);
|
||||
power4 <= 1'b1;
|
||||
end
|
||||
|
||||
wire flash_csb;
|
||||
wire flash_clk;
|
||||
wire flash_io0;
|
||||
wire flash_io1;
|
||||
|
||||
wire VDD3V3 = power1;
|
||||
wire VDD1V8 = power2;
|
||||
wire USER_VDD3V3 = power3;
|
||||
wire USER_VDD1V8 = power4;
|
||||
wire VSS = 1'b0;
|
||||
|
||||
caravel uut (
|
||||
.vddio (VDD3V3),
|
||||
.vssio (VSS),
|
||||
.vdda (VDD3V3),
|
||||
.vssa (VSS),
|
||||
.vccd (VDD1V8),
|
||||
.vssd (VSS),
|
||||
.vdda1 (USER_VDD3V3),
|
||||
.vdda2 (USER_VDD3V3),
|
||||
.vssa1 (VSS),
|
||||
.vssa2 (VSS),
|
||||
.vccd1 (USER_VDD1V8),
|
||||
.vccd2 (USER_VDD1V8),
|
||||
.vssd1 (VSS),
|
||||
.vssd2 (VSS),
|
||||
.clock (clock),
|
||||
.gpio (gpio),
|
||||
.mprj_io (mprj_io),
|
||||
.flash_csb(flash_csb),
|
||||
.flash_clk(flash_clk),
|
||||
.flash_io0(flash_io0),
|
||||
.flash_io1(flash_io1),
|
||||
.resetb (RSTB)
|
||||
);
|
||||
|
||||
spiflash #(
|
||||
.FILENAME("/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.hex")
|
||||
) spiflash (
|
||||
.csb(flash_csb),
|
||||
.clk(flash_clk),
|
||||
.io0(flash_io0),
|
||||
.io1(flash_io1),
|
||||
.io2(), // not used
|
||||
.io3() // not used
|
||||
);
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue