mirror of https://github.com/lnis-uofu/SOFA.git
[SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending
This commit is contained in:
Ganesh Gore
parent
0672f01e3a
commit
9f9897c5e2
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@ -6,6 +6,7 @@
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**/*_task/skywater
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**/*_Verilog/SRC_Skeleton
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**/*_Verilog/SRCBackup
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**/SRC/top_top_formal_verification.v
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**/DOC/build
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**/SRC**/*_tb.v
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**/SDC/**/*.sdc
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@ -48,6 +48,7 @@ Untracked files:
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openfpga_flow/tasks/FPGA1212_FC_HD_SKY_task
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openfpga_flow/tasks/FPGA1212_FLAT_HD_SKY_task
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openfpga_flow/tasks/FPGA1212_HIER_SKY_SC_MS_task
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openfpga_flow/tasks/FPGA1212_QLSOFA_HD_task
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openfpga_flow/tasks/FPGA1212_RESET_HD_SKY_task
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openfpga_flow/tasks/FPGA1212_SOFA_CHD_task
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openfpga_flow/tasks/FPGA128128_FLAT_task
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@ -36,6 +36,7 @@ output [0:0] out;
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//
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//
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wire [0:0] out_inv;
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scs8hd_muxinv2_1 scs8hd_muxinv2_1_0(
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.Q1(in[0]),
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.Q2(in[1]),
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@ -43,7 +44,11 @@ output [0:0] out;
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.S0B(mem_inv[0]),
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.S1(mem[1]),
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.S1B(mem_inv[1]),
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.Z(out[0])
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.Z(out_inv[0])
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);
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sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0(
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.A(out_inv[0]),
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.Y(out[0])
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);
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scs8hd_muxinv2_1 scs8hd_muxinv2_1_1(
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.Q1(in[2]),
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@ -52,7 +57,11 @@ output [0:0] out;
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.S0B(mem_inv[2]),
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.S1(mem[3]),
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.S1B(mem_inv[3]),
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.Z(out[0])
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.Z(out_inv[0])
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);
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sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1(
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.A(out_inv[0]),
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.Y(out[0])
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);
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endmodule
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//
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@ -87,6 +96,7 @@ output [0:0] out;
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//
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//
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wire [0:0] out_inv;
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scs8hd_muxinv2_1 scs8hd_muxinv2_1_0(
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.Q1(in[0]),
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.Q2(in[1]),
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@ -94,7 +104,11 @@ output [0:0] out;
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.S0B(mem_inv[0]),
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.S1(mem[1]),
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.S1B(mem_inv[1]),
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.Z(out[0])
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.Z(out_inv[0])
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);
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sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0(
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.A(out_inv[0]),
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.Y(out[0])
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);
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endmodule
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//
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@ -129,6 +143,7 @@ output [0:0] out;
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//
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//
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wire [0:0] out_inv;
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scs8hd_muxinv3_1 scs8hd_muxinv3_1_0(
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.Q1(in[0]),
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.Q2(in[1]),
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@ -139,7 +154,11 @@ output [0:0] out;
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.S1B(mem_inv[1]),
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.S2(mem[2]),
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.S2B(mem_inv[2]),
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.Z(out[0])
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.Z(out_inv[0])
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);
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sky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower0(
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.A(out_inv[0]),
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.Y(out[0])
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);
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endmodule
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//
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@ -174,6 +193,7 @@ output [0:0] out;
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//
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//
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wire [0:0] out_inv;
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scs8hd_muxinv2_1 scs8hd_muxinv2_1_0(
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.Q1(in[0]),
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.Q2(in[1]),
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@ -181,7 +201,11 @@ output [0:0] out;
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.S0B(mem_inv[0]),
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.S1(mem[1]),
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.S1B(mem_inv[1]),
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.Z(out[0])
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.Z(out_inv[0])
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);
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sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0(
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.A(out_inv[0]),
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.Y(out[0])
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);
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endmodule
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//
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@ -216,6 +240,7 @@ output [0:0] out;
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//
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//
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wire [0:0] out_inv;
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scs8hd_muxinv2_1 scs8hd_muxinv2_1_0(
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.Q1(in[0]),
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.Q2(in[1]),
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@ -223,7 +248,11 @@ output [0:0] out;
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.S0B(mem_inv[0]),
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.S1(mem[1]),
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.S1B(mem_inv[1]),
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.Z(out[0])
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.Z(out_inv[0])
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);
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sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower0(
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.A(out_inv[0]),
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.Y(out[0])
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);
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scs8hd_muxinv2_1 scs8hd_muxinv2_1_1(
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.Q1(in[2]),
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@ -232,7 +261,11 @@ output [0:0] out;
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.S0B(mem_inv[2]),
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.S1(mem[3]),
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.S1B(mem_inv[3]),
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.Z(out[0])
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.Z(out_inv[0])
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);
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sky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower1(
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.A(out_inv[0]),
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.Y(out[0])
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);
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endmodule
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//
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@ -267,6 +300,7 @@ output [0:0] out;
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//
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//
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wire [0:0] out_inv;
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sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0(
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.A1(in[0]),
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.A0(in[1]),
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@ -2,7 +2,7 @@
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- Fabric bitstream
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- Author: Xifan TANG
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- Organization: University of Utah
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- Date: Tue Dec 8 15:34:09 2020
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- Date: Sun Dec 13 16:23:01 2020
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-->
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<fabric_bitstream>
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@ -2,7 +2,7 @@
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- Architecture independent bitstream
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- Author: Xifan TANG
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- Organization: University of Utah
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- Date: Tue Dec 8 15:34:08 2020
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- Date: Sun Dec 13 16:23:00 2020
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-->
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<bitstream_block name="fpga_top" hierarchy_level="0">
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@ -281,12 +281,12 @@ Device Utilization: 0.02 (target 1.00)
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Netlist conversion complete.
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# Packing took 0.03 seconds (max_rss 10.7 MiB, delta_rss +0.7 MiB)
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# Packing took 0.01 seconds (max_rss 10.7 MiB, delta_rss +0.7 MiB)
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# Load Packing
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Begin loading packed FPGA netlist file.
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Netlist generated from file 'top.net'.
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Detected 0 constant generators (to see names run with higher pack verbosity)
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Finished loading packed FPGA netlist file (took 0.02 seconds).
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Finished loading packed FPGA netlist file (took 0 seconds).
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Warning 65: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
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# Load Packing took 0.01 seconds (max_rss 10.7 MiB, delta_rss +0.1 MiB)
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Warning 66: Netlist contains 0 global net to non-global architecture pin connections
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@ -374,10 +374,10 @@ Warning 105: in check_rr_node: RR node: 1645 type: OPIN location: (12,1) pin: 53
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Warning 106: in check_rr_node: RR node: 1646 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
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Warning 107: in check_rr_graph: fringe node 15912 CHANX at (1,1) has no fanin.
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This is possible on a fringe node based on low Fc_out, N, and certain lengths.
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## Build tileable routing resource graph took 0.19 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB)
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## Build tileable routing resource graph took 0.29 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB)
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RR Graph Nodes: 23404
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RR Graph Edges: 121880
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# Create Device took 0.19 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB)
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# Create Device took 0.29 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB)
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# Placement
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## Computing placement delta delay look-up
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@ -418,12 +418,12 @@ Warning 140: in check_rr_node: RR node: 13066 type: OPIN location: (11,1) pin: 5
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Warning 141: in check_rr_node: RR node: 14352 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
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Warning 142: in check_rr_node: RR node: 14353 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
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Warning 143: in check_rr_node: RR node: 14354 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
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### Build routing resource graph took 0.08 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB)
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### Build routing resource graph took 0.10 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB)
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RR Graph Nodes: 23120
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RR Graph Edges: 105560
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### Computing delta delays
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### Computing delta delays took 0.03 seconds (max_rss 20.8 MiB, delta_rss +0.0 MiB)
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## Computing placement delta delay look-up took 0.11 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB)
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### Computing delta delays took 0.04 seconds (max_rss 20.8 MiB, delta_rss +0.0 MiB)
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## Computing placement delta delay look-up took 0.15 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB)
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There are 3 point to point connections in this circuit.
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@ -526,7 +526,7 @@ Placement total # of swap attempts: 232
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Swaps aborted : 0 ( 0.0 %)
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Aborted Move Reasons:
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# Placement took 0.11 seconds (max_rss 21.2 MiB, delta_rss +1.1 MiB)
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# Placement took 0.15 seconds (max_rss 21.2 MiB, delta_rss +1.1 MiB)
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# Routing
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## Build tileable routing resource graph
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@ -570,7 +570,7 @@ Warning 178: in check_rr_node: RR node: 1645 type: OPIN location: (12,1) pin: 53
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Warning 179: in check_rr_node: RR node: 1646 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
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Warning 180: in check_rr_graph: fringe node 15912 CHANX at (1,1) has no fanin.
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This is possible on a fringe node based on low Fc_out, N, and certain lengths.
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## Build tileable routing resource graph took 0.14 seconds (max_rss 21.5 MiB, delta_rss +0.3 MiB)
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## Build tileable routing resource graph took 0.19 seconds (max_rss 21.5 MiB, delta_rss +0.3 MiB)
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RR Graph Nodes: 23404
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RR Graph Edges: 121880
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Confirming router algorithm: TIMING_DRIVEN.
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@ -583,7 +583,7 @@ Restoring best routing
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Critical path: 0.69331 ns
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Successfully routed after 1 routing iterations.
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Router Stats: total_nets_routed: 3 total_connections_routed: 3 total_heap_pushes: 124 total_heap_pops: 52
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# Routing took 0.15 seconds (max_rss 22.3 MiB, delta_rss +1.1 MiB)
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# Routing took 0.20 seconds (max_rss 22.3 MiB, delta_rss +1.1 MiB)
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Checking to ensure routing is legal...
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Completed routing consistency check successfully.
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@ -701,9 +701,9 @@ Setup slack histogram:
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[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
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[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
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Timing analysis took 0.000266012 seconds (0.000240965 STA, 2.5047e-05 slack) (43 full updates: 41 setup, 0 hold, 2 combined).
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Timing analysis took 0.000354561 seconds (0.000323356 STA, 3.1205e-05 slack) (43 full updates: 41 setup, 0 hold, 2 combined).
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VPR suceeded
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The entire flow of VPR took 0.53 seconds (max_rss 22.5 MiB)
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The entire flow of VPR took 0.72 seconds (max_rss 22.5 MiB)
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Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
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@ -935,7 +935,7 @@ Annotating previous nodes for rr_node...Done with 15 nodes mapping
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[99%] Backannotated GSB[12][11]
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[100%] Backannotated GSB[12][12]
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Backannotated 169 General Switch Blocks (GSBs).
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# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 22.8 MiB, delta_rss +0.0 MiB)
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# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.01 seconds (max_rss 22.8 MiB, delta_rss +0.0 MiB)
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# Sort incoming edges for each routing track output node of General Switch Block(GSB)
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[0%] Sorted edges for GSB[0][0]
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[1%] Sorted edges for GSB[0][1]
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@ -1107,7 +1107,7 @@ Backannotated 169 General Switch Blocks (GSBs).
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[99%] Sorted edges for GSB[12][11]
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[100%] Sorted edges for GSB[12][12]
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Sorted edges for 169 General Switch Blocks (GSBs).
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# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.07 seconds (max_rss 23.3 MiB, delta_rss +0.5 MiB)
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# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.09 seconds (max_rss 23.3 MiB, delta_rss +0.5 MiB)
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# Build a library of physical multiplexers
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Built a multiplexer library of 16 physical multiplexers.
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Maximum multiplexer size is 16.
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@ -1124,7 +1124,7 @@ Average net density: 0.42
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Median net density: 0.00
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Average net density after weighting: 0.42
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Will apply 2 operating clock cycles to simulations
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Link OpenFPGA architecture to VPR architecture took 0.08 seconds (max_rss 23.6 MiB, delta_rss +0.8 MiB)
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Link OpenFPGA architecture to VPR architecture took 0.10 seconds (max_rss 23.6 MiB, delta_rss +0.8 MiB)
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Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA1212_SOFA_CHD_task/arch/fabric_key.xml
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@ -1138,7 +1138,7 @@ Confirm selected options when call command 'build_fabric':
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--verbose: off
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Identify unique General Switch Blocks (GSBs)
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Detected 9 unique general switch blocks from a total of 169 (compression rate=1777.78%)
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Identify unique General Switch Blocks (GSBs) took 0.12 seconds (max_rss 23.6 MiB, delta_rss +0.0 MiB)
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Identify unique General Switch Blocks (GSBs) took 0.16 seconds (max_rss 23.6 MiB, delta_rss +0.0 MiB)
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Read Fabric Key
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Read Fabric Key took 0.00 seconds (max_rss 23.7 MiB, delta_rss +0.1 MiB)
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@ -1180,9 +1180,9 @@ Building physical tiles...Done
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## Add module nets for inter-tile connections
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## Add module nets for inter-tile connections took 0.00 seconds (max_rss 53.1 MiB, delta_rss +0.5 MiB)
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## Add module nets for configuration buses
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## Add module nets for configuration buses took 0.03 seconds (max_rss 55.1 MiB, delta_rss +1.5 MiB)
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# Build FPGA fabric module took 0.19 seconds (max_rss 55.1 MiB, delta_rss +27.1 MiB)
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Build fabric module graph took 0.21 seconds (max_rss 55.1 MiB, delta_rss +31.4 MiB)
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## Add module nets for configuration buses took 0.01 seconds (max_rss 55.1 MiB, delta_rss +1.5 MiB)
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# Build FPGA fabric module took 0.17 seconds (max_rss 55.1 MiB, delta_rss +27.1 MiB)
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Build fabric module graph took 0.19 seconds (max_rss 55.1 MiB, delta_rss +31.4 MiB)
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Create I/O location mapping for top module
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Create I/O location mapping for top module took 0.00 seconds (max_rss 55.1 MiB, delta_rss +0.0 MiB)
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Create global port info for top module
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@ -1217,10 +1217,10 @@ Generating bitstream for X-direction Connection blocks ...Done
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Generating bitstream for Y-direction Connection blocks ...Done
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Build fabric-independent bitstream for implementation 'top'
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took 0.26 seconds (max_rss 60.4 MiB, delta_rss +5.2 MiB)
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took 0.15 seconds (max_rss 60.4 MiB, delta_rss +5.2 MiB)
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Warning 185: Directory path is empty and nothing will be created.
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Write 81452 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
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Write 81452 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.73 seconds (max_rss 60.4 MiB, delta_rss +0.0 MiB)
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Write 81452 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.60 seconds (max_rss 60.4 MiB, delta_rss +0.0 MiB)
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Command line to execute: build_fabric_bitstream
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@ -1231,7 +1231,7 @@ Build fabric dependent bitstream
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Build fabric dependent bitstream
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took 0.09 seconds (max_rss 65.5 MiB, delta_rss +5.2 MiB)
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took 0.04 seconds (max_rss 65.5 MiB, delta_rss +5.2 MiB)
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Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
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@ -1251,7 +1251,7 @@ Confirm selected options when call command 'write_fabric_bitstream':
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--verbose: off
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Warning 187: Directory path is empty and nothing will be created.
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Write 81452 fabric bitstream into xml file 'fabric_bitstream.xml'
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Write 81452 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.16 seconds (max_rss 65.5 MiB, delta_rss +0.0 MiB)
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Write 81452 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.14 seconds (max_rss 65.5 MiB, delta_rss +0.0 MiB)
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Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --verbose
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||||
|
||||
|
|
@ -1314,7 +1314,7 @@ Building physical tiles...Done
|
|||
Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done
|
||||
Written 92 Verilog modules in total
|
||||
Write Verilog netlists for FPGA fabric
|
||||
took 0.64 seconds (max_rss 68.4 MiB, delta_rss +2.8 MiB)
|
||||
took 0.45 seconds (max_rss 68.4 MiB, delta_rss +2.8 MiB)
|
||||
|
||||
Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
|
||||
|
||||
|
|
@ -1336,17 +1336,17 @@ Write Verilog testbenches for FPGA fabric
|
|||
|
||||
Warning 189: Directory './SRC' already exists. Will overwrite contents
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top'
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 3.54 seconds (max_rss 68.4 MiB, delta_rss +0.0 MiB)
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 3.67 seconds (max_rss 68.4 MiB, delta_rss +0.0 MiB)
|
||||
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top'
|
||||
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 68.4 MiB, delta_rss +0.0 MiB)
|
||||
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top'
|
||||
Will use 81453 configuration clock cycles to top testbench
|
||||
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.21 seconds (max_rss 68.5 MiB, delta_rss +0.1 MiB)
|
||||
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.23 seconds (max_rss 68.5 MiB, delta_rss +0.1 MiB)
|
||||
Succeed to create directory './SimulationDeck'
|
||||
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini'
|
||||
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 68.5 MiB, delta_rss +0.0 MiB)
|
||||
Write Verilog testbenches for FPGA fabric
|
||||
took 3.77 seconds (max_rss 68.5 MiB, delta_rss +0.1 MiB)
|
||||
took 3.93 seconds (max_rss 68.5 MiB, delta_rss +0.2 MiB)
|
||||
|
||||
Command line to execute: write_pnr_sdc --file ./SDC
|
||||
|
||||
|
|
@ -1370,17 +1370,17 @@ Succeed to create directory './SDC'
|
|||
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc'
|
||||
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' took 0.00 seconds (max_rss 68.5 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc'
|
||||
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.01 seconds (max_rss 68.6 MiB, delta_rss +0.1 MiB)
|
||||
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.01 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc'
|
||||
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.07 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.05 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc'
|
||||
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' took 0.00 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC for constrain Switch Block timing for P&R flow
|
||||
Write SDC for constrain Switch Block timing for P&R flow took 0.04 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC for constrain Connection Block timing for P&R flow
|
||||
Write SDC for constrain Connection Block timing for P&R flow took 0.02 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC for constrain Connection Block timing for P&R flow took 0.01 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC for constraining grid timing for P&R flow
|
||||
Write SDC for constraining grid timing for P&R flow took 0.02 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC for constraining grid timing for P&R flow took 0.01 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
|
||||
|
||||
|
|
@ -1390,7 +1390,7 @@ Confirm selected options when call command 'write_sdc_disable_timing_configure_p
|
|||
--verbose: off
|
||||
Warning 190: Directory './SDC' already exists. Will overwrite contents
|
||||
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc'
|
||||
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.10 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.11 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: write_analysis_sdc --file ./SDC_analysis
|
||||
|
||||
|
|
@ -1401,7 +1401,7 @@ Confirm selected options when call command 'write_analysis_sdc':
|
|||
--time_unit: off
|
||||
Succeed to create directory './SDC_analysis'
|
||||
Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc'
|
||||
Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' took 0.97 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' took 1.01 seconds (max_rss 68.6 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: exit
|
||||
|
||||
|
|
@ -1409,6 +1409,6 @@ Confirm selected options when call command 'exit':
|
|||
|
||||
Finish execution with 0 errors
|
||||
|
||||
The entire OpenFPGA flow took 7.48 seconds
|
||||
The entire OpenFPGA flow took 7.3 seconds
|
||||
|
||||
Thank you for using OpenFPGA!
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
## FPGA1212_SOFA_CHD_PNR
|
||||
|
||||
https://skywater-openfpga.readthedocs.io/en/latest/datasheet/qlsofa_hd/
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
|
||||
## = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
## Verification makefile for FPGA1212_RESET_HD_SKY_PNR (Caravel-QLSOFA-HD)
|
||||
## = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
SHELL=bash
|
||||
PYTHON_EXEC=python3.8
|
||||
RERUN = 0
|
||||
TB = top
|
||||
OPTIONS =
|
||||
SIM = modelsim
|
||||
TEST_FILE = fpga_reset_hd_sky_pnr
|
||||
|
||||
.SILENT:
|
||||
.ONESHELL:
|
||||
|
||||
## Copy all the POSTPnR files from realease directory
|
||||
UpdatePostPnRNetlist:
|
||||
source ../config.sh
|
||||
DESIGN_NAME=$${TOP_MODULE:-$${DESIGN_NAME}}
|
||||
echo "Collecting files $${DESIGN_NAME}"
|
||||
cp ../pnr/$${DESIGN_NAME}/outputs_icc2/$${DESIGN_NAME}_icv_in_design.pt.v . || \
|
||||
cp ../$${DESIGN_NAME}/outputs_icc2/$${DESIGN_NAME}_icv_in_design.pt.v . || :
|
||||
|
||||
|
||||
## Create symbolic links and run test
|
||||
RunPostPnRTest:
|
||||
source ../config.sh
|
||||
INCLUDE_POSTPNR=$${INCLUDE_POSTPNR:-include_postpnr}
|
||||
DESIGN_NAME=$${TOP_MODULE:-$${DESIGN_NAME}}
|
||||
VerificationFile=$${TEST_FILE:-${TEST_FILE}}
|
||||
# = = = = = = = = = = = = = = Log Information = = = = = = = = = = = =
|
||||
echo "DESIGN_NAME = $${DESIGN_NAME}"
|
||||
echo "VerificationFile = $${DESIGN_NAME}"
|
||||
echo "INCLUDE_FILE = $${INCLUDE_POSTPNR}"
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
echo $${VerificationFile}
|
||||
if [ ! -f "./$${VerificationFile}.py" ]; then
|
||||
echo "Test file not found $${VerificationFile}.py"
|
||||
fi
|
||||
echo "Using test file $${VerificationFile}.py"
|
||||
Tests=`grep -A 1 "^@cocotb.test" ./$${VerificationFile}.py | grep "def" | sed "s/.*def \(.*\)(.*/\1/g"`
|
||||
select RUN_TB in $${Tests}
|
||||
do
|
||||
echo "Running $${RUN_TB} Test"
|
||||
if [[ -d "$${RUN_TB}_run" ]] && [[ -z "$${RERUN}" ]]; then
|
||||
echo "Skipping copying source, which will skip the compilations";
|
||||
cp *_tests.py ./$${RUN_TB}_run;
|
||||
cd $${RUN_TB}_run; break;
|
||||
fi
|
||||
|
||||
# = = = = = = = = = = = Prepare Netlist = = = = = = = = = = = = = =
|
||||
# = = = = = = = = = = = Copy python test = = = = = = = = = = = = =
|
||||
mkdir -p "$${RUN_TB}_run"
|
||||
cp $${VerificationFile}.py ./$${RUN_TB}_run
|
||||
cp $${DESIGN_NAME}_icv_in_design.pt.v ./$${RUN_TB}_run/$${DESIGN_NAME}_cocosim.v
|
||||
|
||||
TaskDir=`readlink -f ../*_Verilog/TaskConfigCopy`
|
||||
TaskDir2=`readlink -f ../*_task`
|
||||
if [ -d "$$TaskDir" ]; then
|
||||
rm -rf ./$${RUN_TB}_run/TaskConfigCopy && ln -s $${TaskDir} ./$${RUN_TB}_run
|
||||
elif [ -d "$$TaskDir2" ]; then
|
||||
TaskDir=`readlink -f ../*_task`
|
||||
rm -rf ./$${RUN_TB}_run/TaskConfigCopy && ln -s $${TaskDir} ./$${RUN_TB}_run/TaskConfigCopy
|
||||
else
|
||||
echo "Task configuration directory not found"
|
||||
fi
|
||||
# = = = = = = = = = = = Enter Run Directory = = = = = = = = = = = = =
|
||||
cd $${RUN_TB}_run
|
||||
cp ../INIT/$${INCLUDE_POSTPNR}.v ./fabric_netlists_cocosim.v
|
||||
echo "\`include \"$$(readlink -f $${DESIGN_NAME}_cocosim.v)\"" >> ./fabric_netlists_cocosim.v
|
||||
|
||||
# = = = = = = = = = = = Insert Init Signals = = = = = = = = = = = =
|
||||
if test -f "../INIT/$${RUN_TB}_init.v"; then
|
||||
echo "Found Initialization file [../INIT/$${RUN_TB}_init.v]"
|
||||
modLineNo=$$(grep -n "module fpga_top" $${DESIGN_NAME}_cocosim.v | cut -f1 -d:)
|
||||
echo $${modLineNo}
|
||||
sed -i "$${modLineNo},\$${/endmodule/d}" $${DESIGN_NAME}_cocosim.v
|
||||
cat ../INIT/$${RUN_TB}_init.v >> $${DESIGN_NAME}_cocosim.v
|
||||
printf "\nendmodule" >> $${DESIGN_NAME}_cocosim.v
|
||||
else
|
||||
echo "No Initialization file found [../INIT/$${RUN_TB}_init.v]"
|
||||
fi
|
||||
|
||||
# = = = = = = = = Create Makefile to run = = = = = = = = = = = = = =
|
||||
echo "TOPLEVEL_LANG = verilog" > Makefile
|
||||
echo "VERILOG_SOURCES = fabric_netlists_cocosim.v" >> Makefile
|
||||
echo "TOPLEVEL = $${DESIGN_NAME}" >> Makefile
|
||||
echo "MODULE = $${VerificationFile}" >> Makefile
|
||||
echo "TESTCASE = $${RUN_TB}" >> Makefile
|
||||
echo "" >> Makefile
|
||||
echo "include $(shell cocotb-config --makefiles)/Makefile.sim" >> Makefile
|
||||
break
|
||||
done
|
||||
if [ -z "$$DRY_RUN" ]; then make SIM=$${SIM:-${SIM}}; fi
|
||||
|
|
@ -0,0 +1,349 @@
|
|||
import random
|
||||
import os
|
||||
import sys
|
||||
import glob
|
||||
import math
|
||||
import cocotb
|
||||
import logging
|
||||
import filecmp
|
||||
from logging.handlers import RotatingFileHandler
|
||||
from collections import OrderedDict
|
||||
from pprint import pprint
|
||||
from xml.dom import minidom
|
||||
from cocotb.binary import BinaryValue
|
||||
from cocotb.log import SimLogFormatter
|
||||
from cocotb.clock import Clock
|
||||
from cocotb import wavedrom
|
||||
from cocotb.utils import get_sim_time
|
||||
from cocotb.handle import Force, Release, Deposit
|
||||
from cocotb.monitors import Monitor
|
||||
from cocotb.scoreboard import Scoreboard
|
||||
from cocotb.result import SimTimeoutError, TestFailure, SimTimeoutError, TestSuccess
|
||||
from cocotb.triggers import FallingEdge, RisingEdge, Timer, ClockCycles, with_timeout, First
|
||||
|
||||
root_logger = logging.getLogger()
|
||||
|
||||
|
||||
file_handler = RotatingFileHandler(
|
||||
"run.log", maxBytes=(5 * 1024 * 1024), backupCount=2)
|
||||
root_logger.addHandler(file_handler)
|
||||
|
||||
# Caravel interface pin mapping
|
||||
FromPinAlias = {
|
||||
"prog_clk": "io_in[37]",
|
||||
"clk": "io_in[36]",
|
||||
"pReset": "io_in[3]",
|
||||
"Reset": "io_in[2]",
|
||||
"test_en": "io_in[0]",
|
||||
"sc_head": "io_in[26]",
|
||||
"sc_tail": "io_in[11]",
|
||||
"ccff_head": "io_in[12]",
|
||||
"ccff_tail": "io_in[35]",
|
||||
}
|
||||
|
||||
|
||||
def getFromPinAlias(dut, pinName):
|
||||
''' Get DUT pin from alias '''
|
||||
return eval(f"dut.{FromPinAlias[pinName]}")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def ConfigChainTestFull(dut):
|
||||
# = = = = = = = Get Design Variable = = = = = = = = = = = = = = = = =
|
||||
PConf = getConfig()
|
||||
clk = getFromPinAlias(dut, "clk")
|
||||
prog_clk = getFromPinAlias(dut, "prog_clk")
|
||||
test_en = getFromPinAlias(dut, "test_en")
|
||||
pReset = getFromPinAlias(dut, "pReset")
|
||||
Reset = getFromPinAlias(dut, "Reset")
|
||||
ccff_head = getFromPinAlias(dut, "ccff_head")
|
||||
ccff_tail = getFromPinAlias(dut, "ccff_tail")
|
||||
PCLK_PERIOD = 10 # in nanoseconds
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
clk <= 0 # Disable prog clock
|
||||
Reset <= 0 # Disable reset
|
||||
pReset <= 0 # Reset all configuration FF
|
||||
pclock = Clock(prog_clk, PCLK_PERIOD*0.5, units="ns")
|
||||
cocotb.fork(pclock.start()) # Start the clock
|
||||
|
||||
# Clock Preamble Ticks 2
|
||||
await ClockCycles(prog_clk, 2)
|
||||
await FallingEdge(prog_clk)
|
||||
pReset <= 1
|
||||
|
||||
# Pass 1 bit logic to CCFF chain
|
||||
ccff_head <= 1
|
||||
await FallingEdge(prog_clk)
|
||||
ccff_head <= 0
|
||||
|
||||
# Check CCFF_tail of each module in sequence
|
||||
CCFFChain = filter(lambda x: not "grid_io" in x, CreateCCFFChain())
|
||||
try:
|
||||
start_ccff_time = get_sim_time(units='ns')
|
||||
for ModuleName in CCFFChain:
|
||||
InstPtr = eval(f"dut.fpga_core_uut.{ModuleName}.ccff_tail")
|
||||
|
||||
# Wait for tick
|
||||
start_time_ns = get_sim_time(units='ns')
|
||||
await with_timeout(FallingEdge(InstPtr), 200*PCLK_PERIOD, 'ns')
|
||||
edge_time_ns = get_sim_time(units='ns')
|
||||
|
||||
# Verify
|
||||
CLKTick = math.ceil((edge_time_ns-start_time_ns)/PCLK_PERIOD)
|
||||
dut._log.info(
|
||||
f"Signal received at {ModuleName} at {CLKTick}")
|
||||
if (CLKTick != 8):
|
||||
TestFailure(
|
||||
f"Expected 8 ticks on module {ModuleName} received {CLKTick}")
|
||||
end_ccff_time = get_sim_time(units='ns')
|
||||
await ClockCycles(prog_clk, 10)
|
||||
TotalClock = math.ceil((end_ccff_time-start_ccff_time)/PCLK_PERIOD)
|
||||
dut._log.info(f"Simulation Finished in clocks {TotalClock}")
|
||||
except SimTimeoutError:
|
||||
raise TestFailure(f"Failed to receive signal on {ModuleName}")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def ScanChainTestFull(dut):
|
||||
# = = = = = = = Get Design Variable = = = = = = = = = = = = = = = = =
|
||||
PConf = getConfig()
|
||||
clk = getFromPinAlias(dut, "clk")
|
||||
prog_clk = getFromPinAlias(dut, "prog_clk")
|
||||
pReset = getFromPinAlias(dut, "pReset")
|
||||
Reset = getFromPinAlias(dut, "Reset")
|
||||
test_en = getFromPinAlias(dut, "test_en")
|
||||
sc_head = getFromPinAlias(dut, "sc_head")
|
||||
sc_tail = getFromPinAlias(dut, "sc_tail")
|
||||
CLK_PERIOD = 10 # in nanoseconds
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
prog_clk <= 0 # Disable prog clock
|
||||
pReset <= 0 # Disable programming reset
|
||||
Reset <= 0 # Disable reset
|
||||
clock = Clock(clk, CLK_PERIOD*0.5, units="ns")
|
||||
cocotb.fork(clock.start()) # Start the clock
|
||||
|
||||
# Clock Preamble Ticks 2
|
||||
await ClockCycles(clk, 2)
|
||||
|
||||
# Setup control signals
|
||||
await FallingEdge(clk)
|
||||
test_en <= 1
|
||||
Reset <= 1
|
||||
|
||||
# Pass 1 bit logic to SCFF chain
|
||||
sc_head <= 1
|
||||
await FallingEdge(clk)
|
||||
sc_head <= 0
|
||||
|
||||
try:
|
||||
start_scff_time = get_sim_time(units='ns')
|
||||
for X in range(1, 1+PConf["FPGA_SIZE_X"]):
|
||||
Yrange = range(1, 1+PConf["FPGA_SIZE_X"])
|
||||
Yrange = reversed(Yrange) if (X % 2) else Yrange
|
||||
for Y in Yrange:
|
||||
ModuleName = f"grid_clb_{X}__{Y}_"
|
||||
PinName = "SC_OUT_BOT" if (X % 2) else "SC_OUT_TOP"
|
||||
InstPtr = eval(f"dut.fpga_core_uut.{ModuleName}.{PinName}")
|
||||
# Wait for tick
|
||||
start_time_ns = get_sim_time(units='ns')
|
||||
await with_timeout(FallingEdge(InstPtr), 50*CLK_PERIOD, 'ns')
|
||||
edge_time_ns = get_sim_time(units='ns')
|
||||
|
||||
# Verify
|
||||
CLKTick = math.ceil((edge_time_ns-start_time_ns)/CLK_PERIOD)
|
||||
dut._log.info(
|
||||
f"Signal received at {ModuleName} at {CLKTick}")
|
||||
if (CLKTick != 8):
|
||||
TestFailure(
|
||||
f"Expected 8 ticks on module {ModuleName} received {CLKTick}")
|
||||
end_scff_time = get_sim_time(units='ns')
|
||||
TotalClock = math.ceil((end_scff_time-start_scff_time)/CLK_PERIOD)
|
||||
await ClockCycles(clk, 10)
|
||||
dut._log.info(f"Simulation Finished in clocks {TotalClock}")
|
||||
dut._log.info(f"Per Grid {TotalClock/(PConf['FPGA_SIZE_X']**2)}")
|
||||
except SimTimeoutError:
|
||||
raise TestFailure(f"Failed to receive signal on {ModuleName}")
|
||||
|
||||
|
||||
# ###================================================================
|
||||
# = = = = = = = = = = Utils Functions = = = = = = = = = = = = = = = =
|
||||
# ###================================================================
|
||||
|
||||
|
||||
def getConfig():
|
||||
"""
|
||||
return config.sh varaibles with default values
|
||||
"""
|
||||
return {
|
||||
"TECHNOLOGY": os.environ.get('TECHNOLOGY', 'skywater'),
|
||||
"PROJ_NAME": os.environ.get('PROJ_NAME', None),
|
||||
"DESIGN_STYLE": os.environ.get('DESIGN_STYLE', "hier"),
|
||||
"FPGA_SIZE_X": int(os.environ.get('FPGA_SIZE_X', 0)),
|
||||
"FPGA_SIZE_Y": int(os.environ.get('FPGA_SIZE_Y', 0)),
|
||||
}
|
||||
|
||||
|
||||
@cocotb.coroutine
|
||||
async def ProgramPhase(dut, BitFile, maxCycles=sys.maxsize):
|
||||
dut.pReset_pad = 0
|
||||
bitCount = 0
|
||||
with open(BitFile, "r") as fp:
|
||||
dut._log.info(f"Bitfile opened : {BitFile}")
|
||||
while bitCount < maxCycles:
|
||||
c = fp.read(1)
|
||||
if not c in ["0", "1"]:
|
||||
dut._log.info(f"Configured device with {bitCount} bits")
|
||||
break
|
||||
bitCount += 1
|
||||
if (bitCount % 50) == 0:
|
||||
dut._log.info(f"Writen {bitCount} bits")
|
||||
dut.ccff_head_pad = int(c)
|
||||
await FallingEdge(dut.prog_clk_pad)
|
||||
|
||||
|
||||
@cocotb.coroutine
|
||||
async def AutoConfigure(dut, BitFile, ccPaths, BitstreamLen):
|
||||
TotalBitsCount = 0
|
||||
PreviousSync = 0
|
||||
# Locking Signal
|
||||
with open(BitFile, "r") as fp:
|
||||
dut._log.info(f"Bitfile opened {BitFile}")
|
||||
syncPts = math.ceil(BitstreamLen/4800)
|
||||
InitialBits = [int(i) for i in list(fp.read(syncPts+1))]
|
||||
dut._log.info(f"Will make total {syncPts} sync {InitialBits}")
|
||||
for inst, eachModule in ccPaths.items():
|
||||
BitsCount = 0
|
||||
for eachPath in eachModule:
|
||||
size = eachPath["width"]
|
||||
BitsCount += size
|
||||
try:
|
||||
Stream = fp.read(size)
|
||||
bits = int(Stream, 2)
|
||||
except:
|
||||
dut._log.info(f"Padding Zero")
|
||||
bits = 0
|
||||
eachPath["obj"] <= Force(bits)
|
||||
TotalBitsCount += BitsCount
|
||||
dut._log.info(f"Configured {inst} with {BitsCount} bits ")
|
||||
dut.ccff_head_pad <= InitialBits.pop()
|
||||
await FallingEdge(dut.prog_clk_pad)
|
||||
|
||||
# Releasing Signals
|
||||
PreviousSync = 0
|
||||
TotalBitsCount = 0
|
||||
for inst, eachModule in ccPaths.items():
|
||||
for eachPath in eachModule:
|
||||
eachPath["obj"] <= Release()
|
||||
TotalBitsCount += eachPath["width"]
|
||||
if (TotalBitsCount-PreviousSync) > 4800:
|
||||
dut.ccff_head_pad <= InitialBits.pop()
|
||||
await FallingEdge(dut.prog_clk_pad)
|
||||
PreviousSync = TotalBitsCount
|
||||
dut._log.info(f"Releasing config of {inst}")
|
||||
dut.ccff_head_pad <= InitialBits.pop()
|
||||
await FallingEdge(dut.prog_clk_pad)
|
||||
dut._log.info(f"Configured {TotalBitsCount} bits")
|
||||
|
||||
|
||||
def SaveConfiguration(CFFPaths, filename, style="default"):
|
||||
lineW = 0
|
||||
with open(filename, "w") as fp:
|
||||
for _, eachModule in CFFPaths.items():
|
||||
for eachPath in eachModule:
|
||||
val = eachPath["obj"].value.binstr
|
||||
if style == 'default':
|
||||
val = "\n".join(list(val))
|
||||
fp.write(val+"\n")
|
||||
elif style == "bitstream":
|
||||
fp.write(val)
|
||||
elif style == "detailed":
|
||||
fp.write(f"{eachPath['name']} {val}\n")
|
||||
elif style == "adjusted":
|
||||
for eachC in val:
|
||||
fp.write(eachC)
|
||||
lineW += 1
|
||||
if (lineW == 32):
|
||||
fp.write("\n")
|
||||
lineW = 0
|
||||
|
||||
|
||||
def CreateCCFFChain():
|
||||
CCFFChain = []
|
||||
mydoc = minidom.parse(
|
||||
glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
|
||||
items = mydoc.getElementsByTagName('key')
|
||||
for elem in items:
|
||||
CCFFChain.append(elem.attributes['alias'].value)
|
||||
return CCFFChain
|
||||
|
||||
|
||||
def returnPaths(Node, PathList):
|
||||
Nodes = [e for e in Node.childNodes if not isinstance(e, minidom.Text)]
|
||||
# pprint(Nodes)
|
||||
for eachN in Nodes:
|
||||
eachNChild = [
|
||||
e for e in eachN.childNodes if not isinstance(e, minidom.Text)]
|
||||
Bitstream = [e for e in eachNChild if e.tagName == "bitstream"]
|
||||
if Bitstream:
|
||||
Hier = eachN.getElementsByTagName("hierarchy")[0]
|
||||
path = [each.attributes["name"].value
|
||||
for each in Hier.getElementsByTagName("instance")]
|
||||
path = ".".join(path).replace('fpga_top', 'dut.fpga_core_uut')
|
||||
|
||||
bitEles = Bitstream[0].getElementsByTagName("bit")
|
||||
ports = [path + "." + each.attributes["memory_port"].value.split("[")[0]
|
||||
for each in bitEles[:1]]
|
||||
length = len(bitEles)
|
||||
value = "".join([e.attributes["value"].value for e in bitEles])
|
||||
PathList.append({
|
||||
"name": ports[0],
|
||||
"width": length,
|
||||
"value": value
|
||||
})
|
||||
elif eachN.tagName == "bitstream_block":
|
||||
returnPaths(eachN, PathList)
|
||||
|
||||
|
||||
def get_modules():
|
||||
FabricKey = minidom.parse(
|
||||
glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
|
||||
items = FabricKey.getElementsByTagName('key')
|
||||
return [elem.attributes['alias'].value for elem in items]
|
||||
|
||||
|
||||
def CreateCCFFChainPaths(dut):
|
||||
BitstreamXML = minidom.parse(
|
||||
glob.glob("./TESTBENCH/top/fabric_indepenent_bitstream.xml")[0])
|
||||
|
||||
ModulesDict = {}
|
||||
BT_BLocks = BitstreamXML.getElementsByTagName('bitstream_block')
|
||||
for element in BT_BLocks:
|
||||
if element.getAttribute('hierarchy_level') == "1":
|
||||
ModulesDict[element.attributes['name'].value] = element
|
||||
|
||||
FabricKey = minidom.parse(
|
||||
glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
|
||||
items = FabricKey.getElementsByTagName('key')
|
||||
|
||||
pathList = OrderedDict()
|
||||
chainLength = 0
|
||||
|
||||
for elem in items:
|
||||
modulePaths = []
|
||||
moduleLen = 0
|
||||
inst = elem.attributes['alias'].value
|
||||
returnPaths(ModulesDict[inst], modulePaths)
|
||||
for eachEle in modulePaths:
|
||||
eachEle["obj"] = eval(eachEle["name"])
|
||||
moduleLen += eachEle["width"]
|
||||
pathList[inst] = modulePaths
|
||||
chainLength += moduleLen
|
||||
return (chainLength, pathList)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
CC = CreateCCFFChainPaths(None)
|
||||
pprint(CC["grid_clb_1__2_"][:5])
|
||||
pprint(len(CC["grid_clb_1__2_"]))
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# = = = = = = = = = = = = = = Variables Sections = = = = = = = = = = = = = = =
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
export PROJ_NAME=FPGA1212_SOFA_CHD # Project Name
|
||||
export FPGA_SIZE_X=12 # Grid X Size
|
||||
export FPGA_SIZE_Y=12 # Grid Y Size
|
||||
# Design Style [hier/flat], mostly hier
|
||||
export DESIGN_STYLE=hier
|
||||
export TECHNOLOGY="skywater"
|
||||
|
||||
# Complete Chip (fpga_top) or eFPGA (fpga_core)
|
||||
export DESIGN_NAME=fpga_core
|
||||
|
||||
# Pin Information Source Automatic or Sheet
|
||||
export PIN_MAP=Automatic
|
||||
export PIN_MAP_CSV_SPREADSHEET_LINK="" # Required only if PIN_MAP==Sheet
|
||||
|
||||
# Core Dimension, requires if DESIGN_NAME=fpga_core
|
||||
# if DESIGN_NAME=fpga_top its Optional if defined it overrides the
|
||||
# Calculated DIE_DIMENSION
|
||||
export DIE_DIMENSION=3200
|
||||
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Derived Or Fixed Variables
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
export OPENFPGA_ENGINE_PATH=/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip
|
||||
export TASK_DIR_NAME=${PROJ_NAME}_task
|
||||
export VERILOG_PROJ_DIR=${PROJ_NAME}_Verilog
|
||||
export SPY_HACK_FILE=${TASK_DIR_NAME}/spy_hack.txt
|
||||
export POST_OPENFPGA_SCRIPT=./PostOpenFPGAScript.sh
|
||||
export RESTRUCT_NETLIST=../utils/RestructureNetlistSkywater.py
|
||||
export POST_GENERATION_SCRIPT=./generate_scandef_and_case_analysis.sh
|
||||
export MODULE_ADJUST=./adjust_module.sh
|
||||
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Restructure Netlist Varaibles
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# export RESTRUCTURE_skipClockRestructure=""
|
||||
# export RESTRUCTURE_Skeleton=""
|
||||
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# PNR RELATED FLOW
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
export INIT_DESIGN_INPUT="ASCII"
|
||||
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Extra variables availble during flow (suuffix FLOWVAR_)
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
export FLOWVAR_STANDARD_CELLS="sc_hd"
|
||||
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Reference in New Issue