mirror of https://github.com/lnis-uofu/SOFA.git
[Cleanup] Removed unused SDCs
This commit is contained in:
Ganesh Gore
parent
d9b945ab6f
commit
0672f01e3a
|
|
@ -8,3 +8,5 @@
|
|||
**/*_Verilog/SRCBackup
|
||||
**/DOC/build
|
||||
**/SRC**/*_tb.v
|
||||
**/SDC/**/*.sdc
|
||||
!**/SDC/**/disable_configure_ports.sdc
|
||||
|
|
|
|||
|
|
@ -1,144 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
|
|
@ -1,208 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -1,198 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[13] -to fpga_top/cby_0__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[13] -to fpga_top/cby_0__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[14] -to fpga_top/cby_0__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[14] -to fpga_top/cby_0__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[15] -to fpga_top/cby_0__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[15] -to fpga_top/cby_0__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[17] -to fpga_top/cby_0__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[17] -to fpga_top/cby_0__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[19] -to fpga_top/cby_0__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[19] -to fpga_top/cby_0__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
|
|
@ -1,208 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -1,198 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -1,127 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable configurable memory outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_bottom_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_logic_out_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_fabric_out_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_ff_*_D_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_left_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
|
|
@ -1,122 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable routing multiplexer outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/out
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable Switch Block outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Clock contraints for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}]
|
||||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 1.110371906e-09 -waveform {0 5.551859528e-10} [get_ports {clk[0]}]
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_reg_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_reg_in[0] 1.599999994e-10
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_sc_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_sc_in[0] 1.599999994e-10
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_reg_in[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 4.500000025e-11
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_io__0_/io_inpad[0] 4.243000049e-11
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_io__0_/io_outpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[13] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[14] -to fpga_top/sb_0__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[15] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[16] -to fpga_top/sb_0__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[17] -to fpga_top/sb_0__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[18] -to fpga_top/sb_0__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[19] -to fpga_top/sb_0__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[19] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[13] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[14] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[15] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[16] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[17] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[18] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[18] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[17] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[16] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[15] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[14] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[13] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[12] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[11] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[10] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[9] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[8] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[7] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[6] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[5] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[4] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[3] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[2] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[1] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[19] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[18] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[17] -to fpga_top/sb_0__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[16] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[15] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[14] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[13] -to fpga_top/sb_0__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[12] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[11] -to fpga_top/sb_0__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[10] -to fpga_top/sb_0__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[9] -to fpga_top/sb_0__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[8] -to fpga_top/sb_0__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[7] -to fpga_top/sb_0__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[6] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[5] -to fpga_top/sb_0__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[4] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[3] -to fpga_top/sb_0__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[2] -to fpga_top/sb_0__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[1] -to fpga_top/sb_0__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[0] -to fpga_top/sb_0__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[19] -to fpga_top/sb_0__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
|
|
@ -1,158 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
|
|
@ -1,120 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[19] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[18] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[17] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[16] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[15] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[14] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[13] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[12] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[11] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[10] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[9] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[8] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[7] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[6] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[5] -to fpga_top/sb_12__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[4] -to fpga_top/sb_12__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[3] -to fpga_top/sb_12__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[2] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[1] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[19] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[18] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[17] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[16] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[15] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[14] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[13] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[12] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[11] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[10] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[9] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[8] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[7] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[6] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[5] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[4] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[3] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[2] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[1] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
|
|
@ -1,120 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[1] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[2] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[3] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[4] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[5] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[6] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[7] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[8] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[9] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[10] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[11] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[12] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[13] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[14] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[15] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[16] -to fpga_top/sb_12__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[17] -to fpga_top/sb_12__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[18] -to fpga_top/sb_12__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[19] -to fpga_top/sb_12__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[0] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[19] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[1] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[2] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[3] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[4] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[5] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[6] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[7] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[8] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[9] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[10] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[11] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[12] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[13] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[14] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[15] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[16] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[17] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[18] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
|
|
@ -1,206 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[1] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[1] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11
|
||||
|
|
@ -1,200 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
|
|
@ -1,200 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
|
|
@ -1,322 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
|
|
@ -1,182 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[21] -to fpga_top/cbx_1__0_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[21] -to fpga_top/cbx_1__0_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[22] -to fpga_top/cbx_1__0_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[22] -to fpga_top/cbx_1__0_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[23] -to fpga_top/cbx_1__0_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[23] -to fpga_top/cbx_1__0_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[27] -to fpga_top/cbx_1__0_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[27] -to fpga_top/cbx_1__0_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[28] -to fpga_top/cbx_1__0_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[28] -to fpga_top/cbx_1__0_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[29] -to fpga_top/cbx_1__0_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[29] -to fpga_top/cbx_1__0_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[21] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[21] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[27] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[27] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[22] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[22] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[28] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[28] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[23] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[23] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[29] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[29] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[20] -to fpga_top/cbx_1__12_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[20] -to fpga_top/cbx_1__12_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[22] -to fpga_top/cbx_1__12_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[22] -to fpga_top/cbx_1__12_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[24] -to fpga_top/cbx_1__12_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[24] -to fpga_top/cbx_1__12_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[26] -to fpga_top/cbx_1__12_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[26] -to fpga_top/cbx_1__12_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[28] -to fpga_top/cbx_1__12_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[28] -to fpga_top/cbx_1__12_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[24] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[24] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[26] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[26] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[28] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[28] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[20] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[20] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[22] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[22] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -1,250 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[21] -to fpga_top/cbx_1__1_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[21] -to fpga_top/cbx_1__1_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[23] -to fpga_top/cbx_1__1_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[23] -to fpga_top/cbx_1__1_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[25] -to fpga_top/cbx_1__1_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[25] -to fpga_top/cbx_1__1_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[27] -to fpga_top/cbx_1__1_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[27] -to fpga_top/cbx_1__1_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[29] -to fpga_top/cbx_1__1_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[29] -to fpga_top/cbx_1__1_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[25] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[25] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[27] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[27] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[29] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[29] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[21] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[21] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -1,86 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[13] -to fpga_top/cby_0__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[13] -to fpga_top/cby_0__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[14] -to fpga_top/cby_0__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[14] -to fpga_top/cby_0__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[15] -to fpga_top/cby_0__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[15] -to fpga_top/cby_0__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[17] -to fpga_top/cby_0__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[17] -to fpga_top/cby_0__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[19] -to fpga_top/cby_0__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[19] -to fpga_top/cby_0__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[20] -to fpga_top/cby_0__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[20] -to fpga_top/cby_0__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[21] -to fpga_top/cby_0__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[21] -to fpga_top/cby_0__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[22] -to fpga_top/cby_0__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[22] -to fpga_top/cby_0__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[23] -to fpga_top/cby_0__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[23] -to fpga_top/cby_0__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[24] -to fpga_top/cby_0__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[24] -to fpga_top/cby_0__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[25] -to fpga_top/cby_0__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[25] -to fpga_top/cby_0__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[26] -to fpga_top/cby_0__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[26] -to fpga_top/cby_0__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[27] -to fpga_top/cby_0__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[27] -to fpga_top/cby_0__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[28] -to fpga_top/cby_0__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[28] -to fpga_top/cby_0__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[29] -to fpga_top/cby_0__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[29] -to fpga_top/cby_0__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[24] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[24] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[20] -to fpga_top/cby_12__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[20] -to fpga_top/cby_12__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[22] -to fpga_top/cby_12__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[22] -to fpga_top/cby_12__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[24] -to fpga_top/cby_12__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[24] -to fpga_top/cby_12__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[26] -to fpga_top/cby_12__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[26] -to fpga_top/cby_12__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[28] -to fpga_top/cby_12__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[28] -to fpga_top/cby_12__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[24] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[24] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[26] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[26] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[28] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[28] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[20] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[20] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[22] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[22] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -1,250 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[21] -to fpga_top/cby_1__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[21] -to fpga_top/cby_1__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[23] -to fpga_top/cby_1__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[23] -to fpga_top/cby_1__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[25] -to fpga_top/cby_1__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[25] -to fpga_top/cby_1__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[27] -to fpga_top/cby_1__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[27] -to fpga_top/cby_1__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[29] -to fpga_top/cby_1__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[29] -to fpga_top/cby_1__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[25] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[25] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[27] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[27] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[29] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[29] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[21] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[21] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable configurable memory outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_bottom_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_logic_out_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_lut*_*_in_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_fabric_out_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_ff_*_D_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_left_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
|
|
@ -1,127 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable routing multiplexer outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_lut*_*_in_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/out
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable Switch Block outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Clock contraints for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}]
|
||||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 8.319719358e-10 -waveform {0 4.159859679e-10} [get_ports {clk[0]}]
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_reg_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_reg_in[0] 1.599999994e-10
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_sc_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_sc_in[0] 1.599999994e-10
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_cin[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_cin[0] 1.599999994e-10
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_reg_in[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 4.500000025e-11
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_io__0_/io_inpad[0] 4.243000049e-11
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_io__0_/io_outpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11
|
||||
|
|
@ -1,124 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[13] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[14] -to fpga_top/sb_0__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[15] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[16] -to fpga_top/sb_0__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[17] -to fpga_top/sb_0__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[18] -to fpga_top/sb_0__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[19] -to fpga_top/sb_0__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[20] -to fpga_top/sb_0__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[21] -to fpga_top/sb_0__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[22] -to fpga_top/sb_0__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[23] -to fpga_top/sb_0__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[24] -to fpga_top/sb_0__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[25] -to fpga_top/sb_0__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[26] -to fpga_top/sb_0__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[27] -to fpga_top/sb_0__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[28] -to fpga_top/sb_0__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[29] -to fpga_top/sb_0__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[29] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[13] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[14] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[15] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[16] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[17] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[18] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[19] -to fpga_top/sb_0__0_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[20] -to fpga_top/sb_0__0_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[21] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[22] -to fpga_top/sb_0__0_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[23] -to fpga_top/sb_0__0_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[24] -to fpga_top/sb_0__0_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[25] -to fpga_top/sb_0__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[26] -to fpga_top/sb_0__0_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[27] -to fpga_top/sb_0__0_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[28] -to fpga_top/sb_0__0_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[29] 6.020400151e-11
|
||||
|
|
@ -1,123 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[28] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[27] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[26] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[25] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[24] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[23] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[22] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[21] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[20] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[19] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[18] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[17] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[16] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[15] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[14] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[13] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[12] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[11] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[10] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[9] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[8] -to fpga_top/sb_0__12_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[7] -to fpga_top/sb_0__12_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[6] -to fpga_top/sb_0__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[5] -to fpga_top/sb_0__12_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[4] -to fpga_top/sb_0__12_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[3] -to fpga_top/sb_0__12_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[2] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[1] -to fpga_top/sb_0__12_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[0] -to fpga_top/sb_0__12_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[29] -to fpga_top/sb_0__12_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[28] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[27] -to fpga_top/sb_0__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[26] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[25] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[24] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[23] -to fpga_top/sb_0__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[22] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[21] -to fpga_top/sb_0__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[20] -to fpga_top/sb_0__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[19] -to fpga_top/sb_0__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[18] -to fpga_top/sb_0__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[17] -to fpga_top/sb_0__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[16] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[15] -to fpga_top/sb_0__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[14] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[13] -to fpga_top/sb_0__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[12] -to fpga_top/sb_0__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[11] -to fpga_top/sb_0__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[10] -to fpga_top/sb_0__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[9] -to fpga_top/sb_0__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[8] -to fpga_top/sb_0__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[7] -to fpga_top/sb_0__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[6] -to fpga_top/sb_0__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[5] -to fpga_top/sb_0__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[4] -to fpga_top/sb_0__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[3] -to fpga_top/sb_0__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[2] -to fpga_top/sb_0__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[1] -to fpga_top/sb_0__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[0] -to fpga_top/sb_0__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[29] -to fpga_top/sb_0__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
|
|
@ -1,217 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[23] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[24] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[20] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[25] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[22] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[26] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[23] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[27] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[24] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[28] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[26] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[29] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[27] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[28] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[20] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[21] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[22] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[21] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[25] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[29] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[20] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[20] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[22] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[22] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[23] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[23] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[24] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[24] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[26] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[26] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[27] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[27] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[28] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[28] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[29] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[25] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[21] -to fpga_top/sb_0__1_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[20] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[20] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[22] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[29] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[23] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[28] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[24] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[27] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[26] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[26] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[27] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[25] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[28] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[24] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[23] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[22] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[21] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[29] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[28] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[27] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[26] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[25] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[24] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[23] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[22] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[21] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[20] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[19] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[18] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[17] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[16] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[15] -to fpga_top/sb_12__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[14] -to fpga_top/sb_12__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[13] -to fpga_top/sb_12__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[12] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[11] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[10] -to fpga_top/sb_12__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[9] -to fpga_top/sb_12__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[8] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[7] -to fpga_top/sb_12__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[6] -to fpga_top/sb_12__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[5] -to fpga_top/sb_12__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[4] -to fpga_top/sb_12__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[3] -to fpga_top/sb_12__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[2] -to fpga_top/sb_12__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[1] -to fpga_top/sb_12__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[29] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[28] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[27] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[26] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[25] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[24] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[23] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[22] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[21] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[20] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[19] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[18] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[17] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[16] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[15] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[14] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[13] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[12] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[11] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[10] -to fpga_top/sb_12__0_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[9] -to fpga_top/sb_12__0_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[8] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[7] -to fpga_top/sb_12__0_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[6] -to fpga_top/sb_12__0_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[5] -to fpga_top/sb_12__0_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[4] -to fpga_top/sb_12__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[3] -to fpga_top/sb_12__0_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[2] -to fpga_top/sb_12__0_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[1] -to fpga_top/sb_12__0_/chanx_left_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -1,155 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[1] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[2] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[3] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[4] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[5] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[6] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[7] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[8] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[9] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[10] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[11] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[12] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[13] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[14] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[15] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[16] -to fpga_top/sb_12__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[17] -to fpga_top/sb_12__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[18] -to fpga_top/sb_12__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[19] -to fpga_top/sb_12__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[20] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[21] -to fpga_top/sb_12__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[22] -to fpga_top/sb_12__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[23] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[24] -to fpga_top/sb_12__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[25] -to fpga_top/sb_12__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[26] -to fpga_top/sb_12__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[27] -to fpga_top/sb_12__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[28] -to fpga_top/sb_12__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[29] -to fpga_top/sb_12__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[0] -to fpga_top/sb_12__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[29] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[1] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[2] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[3] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[4] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[5] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[6] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[7] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[8] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[9] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[10] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[11] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[12] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[13] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[14] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[15] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[16] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[17] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[18] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[19] -to fpga_top/sb_12__12_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[20] -to fpga_top/sb_12__12_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[21] -to fpga_top/sb_12__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[22] -to fpga_top/sb_12__12_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[23] -to fpga_top/sb_12__12_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[24] -to fpga_top/sb_12__12_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[25] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[26] -to fpga_top/sb_12__12_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[27] -to fpga_top/sb_12__12_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[28] -to fpga_top/sb_12__12_/chanx_left_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -1,265 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[22] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[20] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[21] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[22] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[20] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[23] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[24] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[29] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[26] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[28] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[27] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[27] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[28] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[26] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[25] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[24] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[23] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[23] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[20] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[24] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[22] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[25] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[23] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[26] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[24] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[27] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[26] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[28] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[27] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[29] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[28] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[20] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[21] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[22] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[1] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[21] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[25] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[29] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[20] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[20] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[22] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[22] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[23] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[23] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[24] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[24] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[26] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[26] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[27] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[27] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[28] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[28] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[29] -to fpga_top/sb_12__1_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[25] -to fpga_top/sb_12__1_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[21] -to fpga_top/sb_12__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[1] -to fpga_top/sb_12__1_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -1,258 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[21] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[25] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[29] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[20] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[20] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[22] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[22] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[23] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[23] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[24] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[24] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[26] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[26] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[27] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[27] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[28] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[28] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[29] -to fpga_top/sb_1__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[25] -to fpga_top/sb_1__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[21] -to fpga_top/sb_1__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[21] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[22] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[20] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[23] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[22] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[24] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[23] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[25] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[24] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[26] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[26] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[27] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[27] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[28] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[28] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[29] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[20] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[22] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[21] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[20] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[20] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[22] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[23] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[29] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[24] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[28] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[26] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[27] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[27] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[26] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[28] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[25] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[24] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[23] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
|
|
@ -1,258 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[20] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[20] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[29] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[22] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[28] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[23] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[27] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[24] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[26] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[26] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[25] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[27] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[24] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[28] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[23] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[22] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[21] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[21] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[25] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[29] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[20] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[20] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[22] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[22] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[23] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[23] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[24] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[24] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[26] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[26] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[27] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[27] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[28] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[29] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[28] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[25] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[21] -to fpga_top/sb_1__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[21] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[20] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[22] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[22] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[23] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[23] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[24] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[24] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[25] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[26] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[26] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[27] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[27] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[28] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[28] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[29] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[20] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
|
|
@ -1,426 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 1 18:12:04 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[29] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[25] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[21] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[21] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[25] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[29] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[29] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[25] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[21] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[21] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[25] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[29] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[25] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[21] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[21] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[25] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[29] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[29] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[29] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[29] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[25] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[21] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[21] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[25] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
|
|
@ -1,182 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[21] -to fpga_top/cbx_1__0_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[21] -to fpga_top/cbx_1__0_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[22] -to fpga_top/cbx_1__0_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[22] -to fpga_top/cbx_1__0_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[23] -to fpga_top/cbx_1__0_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[23] -to fpga_top/cbx_1__0_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[27] -to fpga_top/cbx_1__0_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[27] -to fpga_top/cbx_1__0_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[28] -to fpga_top/cbx_1__0_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[28] -to fpga_top/cbx_1__0_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[29] -to fpga_top/cbx_1__0_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[29] -to fpga_top/cbx_1__0_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[21] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[21] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[27] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[27] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[22] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[22] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[28] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[28] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[23] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[23] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[29] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[29] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[24] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[25] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[20] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[26] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[20] -to fpga_top/cbx_1__12_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[20] -to fpga_top/cbx_1__12_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[22] -to fpga_top/cbx_1__12_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[22] -to fpga_top/cbx_1__12_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[24] -to fpga_top/cbx_1__12_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[24] -to fpga_top/cbx_1__12_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[26] -to fpga_top/cbx_1__12_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[26] -to fpga_top/cbx_1__12_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[28] -to fpga_top/cbx_1__12_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[28] -to fpga_top/cbx_1__12_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[24] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[24] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[26] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[26] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[28] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[28] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[23] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[25] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[20] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[20] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[29] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[21] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[27] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[22] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[22] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -1,250 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/chanx_left_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/chanx_right_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[21] -to fpga_top/cbx_1__1_/chanx_left_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[21] -to fpga_top/cbx_1__1_/chanx_right_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/chanx_left_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/chanx_right_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[23] -to fpga_top/cbx_1__1_/chanx_left_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[23] -to fpga_top/cbx_1__1_/chanx_right_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/chanx_left_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/chanx_right_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[25] -to fpga_top/cbx_1__1_/chanx_left_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[25] -to fpga_top/cbx_1__1_/chanx_right_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/chanx_left_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/chanx_right_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[27] -to fpga_top/cbx_1__1_/chanx_left_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[27] -to fpga_top/cbx_1__1_/chanx_right_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/chanx_left_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/chanx_right_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[29] -to fpga_top/cbx_1__1_/chanx_left_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[29] -to fpga_top/cbx_1__1_/chanx_right_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[25] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[25] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[27] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[27] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[29] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[29] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[22] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[24] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[28] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[20] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[26] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[21] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[21] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -1,86 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[13] -to fpga_top/cby_0__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[13] -to fpga_top/cby_0__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[14] -to fpga_top/cby_0__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[14] -to fpga_top/cby_0__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[15] -to fpga_top/cby_0__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[15] -to fpga_top/cby_0__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[17] -to fpga_top/cby_0__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[17] -to fpga_top/cby_0__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[19] -to fpga_top/cby_0__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[19] -to fpga_top/cby_0__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[20] -to fpga_top/cby_0__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[20] -to fpga_top/cby_0__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[21] -to fpga_top/cby_0__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[21] -to fpga_top/cby_0__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[22] -to fpga_top/cby_0__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[22] -to fpga_top/cby_0__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[23] -to fpga_top/cby_0__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[23] -to fpga_top/cby_0__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[24] -to fpga_top/cby_0__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[24] -to fpga_top/cby_0__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[25] -to fpga_top/cby_0__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[25] -to fpga_top/cby_0__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[26] -to fpga_top/cby_0__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[26] -to fpga_top/cby_0__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[27] -to fpga_top/cby_0__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[27] -to fpga_top/cby_0__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[28] -to fpga_top/cby_0__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[28] -to fpga_top/cby_0__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[29] -to fpga_top/cby_0__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[29] -to fpga_top/cby_0__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[24] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[24] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[20] -to fpga_top/cby_12__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[20] -to fpga_top/cby_12__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[22] -to fpga_top/cby_12__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[22] -to fpga_top/cby_12__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[24] -to fpga_top/cby_12__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[24] -to fpga_top/cby_12__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[26] -to fpga_top/cby_12__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[26] -to fpga_top/cby_12__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[28] -to fpga_top/cby_12__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[28] -to fpga_top/cby_12__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[24] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[24] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[26] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[26] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[28] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[28] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[23] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[23] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[25] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[25] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[20] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[20] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[29] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[29] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[21] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[21] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[27] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[27] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[22] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[22] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -1,250 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/chany_bottom_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/chany_top_out[20] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[21] -to fpga_top/cby_1__1_/chany_bottom_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[21] -to fpga_top/cby_1__1_/chany_top_out[21] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/chany_bottom_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/chany_top_out[22] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[23] -to fpga_top/cby_1__1_/chany_bottom_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[23] -to fpga_top/cby_1__1_/chany_top_out[23] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/chany_bottom_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/chany_top_out[24] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[25] -to fpga_top/cby_1__1_/chany_bottom_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[25] -to fpga_top/cby_1__1_/chany_top_out[25] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/chany_bottom_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/chany_top_out[26] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[27] -to fpga_top/cby_1__1_/chany_bottom_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[27] -to fpga_top/cby_1__1_/chany_top_out[27] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/chany_bottom_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/chany_top_out[28] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[29] -to fpga_top/cby_1__1_/chany_bottom_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[29] -to fpga_top/cby_1__1_/chany_top_out[29] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[25] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[25] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[27] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[27] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[29] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[29] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[22] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[22] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[24] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[24] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[28] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[28] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[20] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[20] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[26] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[26] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[21] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[21] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable configurable memory outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_bottom_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_logic_out_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_lut*_*_in_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_fabric_out_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_ff_*_D_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_left_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfrtp_*_mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfrtp_*_*_/Q
|
||||
|
|
@ -4,7 +4,7 @@
|
|||
# Description: Disable configuration outputs of all the programmable cells for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
# Date: Sun Dec 13 16:23:06 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram
|
||||
|
|
|
|||
|
|
@ -1,127 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable routing multiplexer outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_lut*_*_in_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/out
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable Switch Block outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Clock contraints for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}]
|
||||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 8.319719358e-10 -waveform {0 4.159859679e-10} [get_ports {clk[0]}]
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_reg_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_reg_in[0] 1.599999994e-10
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_sc_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_sc_in[0] 1.599999994e-10
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_cin[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_cin[0] 1.599999994e-10
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_reg_in[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 4.500000025e-11
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_io__0_/io_inpad[0] 4.243000049e-11
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_io__0_/io_outpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11
|
||||
|
|
@ -1,124 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[13] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[14] -to fpga_top/sb_0__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[15] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[16] -to fpga_top/sb_0__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[17] -to fpga_top/sb_0__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[18] -to fpga_top/sb_0__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[19] -to fpga_top/sb_0__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[20] -to fpga_top/sb_0__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[21] -to fpga_top/sb_0__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[22] -to fpga_top/sb_0__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[23] -to fpga_top/sb_0__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[24] -to fpga_top/sb_0__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[25] -to fpga_top/sb_0__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[26] -to fpga_top/sb_0__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[27] -to fpga_top/sb_0__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[28] -to fpga_top/sb_0__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[29] -to fpga_top/sb_0__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[29] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[13] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[14] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[15] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[16] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[17] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[18] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[19] -to fpga_top/sb_0__0_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[20] -to fpga_top/sb_0__0_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[21] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[22] -to fpga_top/sb_0__0_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[23] -to fpga_top/sb_0__0_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[24] -to fpga_top/sb_0__0_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[25] -to fpga_top/sb_0__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[26] -to fpga_top/sb_0__0_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[27] -to fpga_top/sb_0__0_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[28] -to fpga_top/sb_0__0_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[29] 6.020400151e-11
|
||||
|
|
@ -1,123 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[28] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[27] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[26] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[25] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[24] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[23] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[22] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[21] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[20] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[19] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[18] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[17] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[16] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[15] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[14] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[13] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[12] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[11] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[10] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[9] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[8] -to fpga_top/sb_0__12_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[7] -to fpga_top/sb_0__12_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[6] -to fpga_top/sb_0__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[5] -to fpga_top/sb_0__12_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[4] -to fpga_top/sb_0__12_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[3] -to fpga_top/sb_0__12_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[2] -to fpga_top/sb_0__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[1] -to fpga_top/sb_0__12_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[0] -to fpga_top/sb_0__12_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__12_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[29] -to fpga_top/sb_0__12_/chanx_right_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[28] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[27] -to fpga_top/sb_0__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[26] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[25] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[24] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[23] -to fpga_top/sb_0__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[22] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[21] -to fpga_top/sb_0__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[20] -to fpga_top/sb_0__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[19] -to fpga_top/sb_0__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[18] -to fpga_top/sb_0__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[17] -to fpga_top/sb_0__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[16] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[15] -to fpga_top/sb_0__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[14] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[13] -to fpga_top/sb_0__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[12] -to fpga_top/sb_0__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[11] -to fpga_top/sb_0__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[10] -to fpga_top/sb_0__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[9] -to fpga_top/sb_0__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[8] -to fpga_top/sb_0__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[7] -to fpga_top/sb_0__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[6] -to fpga_top/sb_0__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[5] -to fpga_top/sb_0__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[4] -to fpga_top/sb_0__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[3] -to fpga_top/sb_0__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[2] -to fpga_top/sb_0__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[1] -to fpga_top/sb_0__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[0] -to fpga_top/sb_0__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[29] -to fpga_top/sb_0__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
|
|
@ -1,217 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[23] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[24] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[20] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[25] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[22] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[26] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[23] -to fpga_top/sb_0__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[27] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[24] -to fpga_top/sb_0__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[28] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[26] -to fpga_top/sb_0__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[29] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[27] -to fpga_top/sb_0__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[28] -to fpga_top/sb_0__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[20] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[21] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[22] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[21] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[25] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[29] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[20] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[20] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[22] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[22] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[23] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[23] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[24] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[24] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[26] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[26] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[27] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[27] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[28] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[28] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[29] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[25] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[21] -to fpga_top/sb_0__1_/chanx_right_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chanx_right_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_0__1_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[20] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[20] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[22] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[29] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[23] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[28] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[24] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[27] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[26] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[26] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[27] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[25] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[28] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[24] -to fpga_top/sb_0__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[23] -to fpga_top/sb_0__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[22] -to fpga_top/sb_0__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[21] -to fpga_top/sb_0__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[29] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[28] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[27] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[26] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[25] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[24] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[23] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[22] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[21] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[20] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[19] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[18] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[17] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[16] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[15] -to fpga_top/sb_12__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[14] -to fpga_top/sb_12__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[13] -to fpga_top/sb_12__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[12] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[11] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[10] -to fpga_top/sb_12__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[9] -to fpga_top/sb_12__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[8] -to fpga_top/sb_12__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[7] -to fpga_top/sb_12__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[6] -to fpga_top/sb_12__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[5] -to fpga_top/sb_12__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[4] -to fpga_top/sb_12__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[3] -to fpga_top/sb_12__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[2] -to fpga_top/sb_12__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[1] -to fpga_top/sb_12__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[29] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[28] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[27] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[26] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[25] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[24] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[23] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[22] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[21] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[20] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[19] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[18] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[17] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[16] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[15] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[14] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[13] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[12] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[11] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[10] -to fpga_top/sb_12__0_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[9] -to fpga_top/sb_12__0_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[8] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[7] -to fpga_top/sb_12__0_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[6] -to fpga_top/sb_12__0_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[5] -to fpga_top/sb_12__0_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[4] -to fpga_top/sb_12__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[3] -to fpga_top/sb_12__0_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[2] -to fpga_top/sb_12__0_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[1] -to fpga_top/sb_12__0_/chanx_left_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -1,155 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[1] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[2] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[3] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[4] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[5] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[6] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[7] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[8] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[9] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[10] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[11] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[12] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[13] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[14] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[15] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[16] -to fpga_top/sb_12__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[17] -to fpga_top/sb_12__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[18] -to fpga_top/sb_12__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[19] -to fpga_top/sb_12__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[20] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[21] -to fpga_top/sb_12__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[22] -to fpga_top/sb_12__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[23] -to fpga_top/sb_12__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[24] -to fpga_top/sb_12__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[25] -to fpga_top/sb_12__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[26] -to fpga_top/sb_12__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[27] -to fpga_top/sb_12__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[28] -to fpga_top/sb_12__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[29] -to fpga_top/sb_12__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[0] -to fpga_top/sb_12__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[29] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[1] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[2] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[3] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[4] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[5] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[6] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[7] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[8] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[9] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[10] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[11] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[12] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[13] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[14] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[15] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[16] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[17] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[18] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[19] -to fpga_top/sb_12__12_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[20] -to fpga_top/sb_12__12_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[21] -to fpga_top/sb_12__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[22] -to fpga_top/sb_12__12_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[23] -to fpga_top/sb_12__12_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[24] -to fpga_top/sb_12__12_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[25] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[26] -to fpga_top/sb_12__12_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[27] -to fpga_top/sb_12__12_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[28] -to fpga_top/sb_12__12_/chanx_left_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__12_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -1,265 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[22] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[20] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[21] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[22] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[20] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[23] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[24] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[29] -to fpga_top/sb_12__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[26] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[28] -to fpga_top/sb_12__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[27] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[27] -to fpga_top/sb_12__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[28] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[26] -to fpga_top/sb_12__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[25] -to fpga_top/sb_12__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[24] -to fpga_top/sb_12__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[23] -to fpga_top/sb_12__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[23] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[20] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[24] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[22] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[25] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[23] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[26] -to fpga_top/sb_12__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[24] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[27] -to fpga_top/sb_12__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[26] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[28] -to fpga_top/sb_12__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[27] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[29] -to fpga_top/sb_12__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[28] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[20] -to fpga_top/sb_12__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[21] -to fpga_top/sb_12__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[22] -to fpga_top/sb_12__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[1] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[21] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[25] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[29] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[20] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[20] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[22] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[22] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[23] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[23] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[24] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[24] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[26] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[26] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[27] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[27] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[28] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[28] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[29] -to fpga_top/sb_12__1_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[25] -to fpga_top/sb_12__1_/chanx_left_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[21] -to fpga_top/sb_12__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_12__1_/chanx_left_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_12__1_/chanx_left_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[1] -to fpga_top/sb_12__1_/chanx_left_out[29] 6.020400151e-11
|
||||
|
|
@ -1,258 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[21] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[25] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[29] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[20] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[20] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[22] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[22] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[23] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[23] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[24] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[24] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[26] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[26] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[27] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[27] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[28] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[28] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[29] -to fpga_top/sb_1__0_/chany_top_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[25] -to fpga_top/sb_1__0_/chany_top_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[21] -to fpga_top/sb_1__0_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chany_top_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chany_top_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[21] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[22] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[20] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[23] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[22] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[24] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[23] -to fpga_top/sb_1__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[25] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[24] -to fpga_top/sb_1__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[26] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[26] -to fpga_top/sb_1__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[27] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[27] -to fpga_top/sb_1__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[28] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[28] -to fpga_top/sb_1__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[29] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[20] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[22] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[21] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[20] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[20] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[22] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[23] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[29] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[24] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[28] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[26] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[27] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[27] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[26] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[28] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[25] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[24] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[23] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[26] 6.020400151e-11
|
||||
|
|
@ -1,258 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[20] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[20] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[29] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[22] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[28] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[23] -to fpga_top/sb_1__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[27] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[24] -to fpga_top/sb_1__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[26] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[26] -to fpga_top/sb_1__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[25] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[27] -to fpga_top/sb_1__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[24] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[28] -to fpga_top/sb_1__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[23] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[22] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[21] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[21] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[25] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[29] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[20] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[20] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[22] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[22] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[23] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[23] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[24] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[24] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[26] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[26] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[27] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[27] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[28] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[29] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[28] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[25] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[21] -to fpga_top/sb_1__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[20] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[21] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[23] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__12_/chany_bottom_out[24] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__12_/chany_bottom_out[25] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[27] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[28] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[29] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[21] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[20] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[22] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[22] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[23] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[23] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[24] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[24] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[25] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[26] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[26] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[27] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[27] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[28] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[28] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[29] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[20] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[26] 6.020400151e-11
|
||||
|
|
@ -1,426 +0,0 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Tue Dec 8 15:34:14 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[29] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[25] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[21] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[21] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[25] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[29] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_top_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_top_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[29] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[25] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[21] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[21] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chanx_right_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[25] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[29] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chanx_right_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[25] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[21] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[20] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[22] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[23] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[24] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_50_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[26] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_51_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[27] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[21] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[28] -to fpga_top/sb_1__1_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[25] -to fpga_top/sb_1__1_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[29] -to fpga_top/sb_1__1_/chany_bottom_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[29] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[29] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[29] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[20] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[25] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[22] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[21] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[23] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[24] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[26] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_42_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[27] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_43_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[28] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[21] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[22] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[25] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[26] 6.020400151e-11
|
||||
Loading…
Reference in New Issue