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[Doc] Add MUX design information to documentation

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tangxifan 2020-12-09 17:51:15 -07:00
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DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst
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@ -8,5 +8,14 @@ Circuit Designs
I/O Circuit
^^^^^^^^^^^
SOFA CHD FPGA share the same I/O circuit design as SOFA HD FPGA.
QLSOFA HD FPGA share the same I/O circuit design as SOFA HD FPGA.
See details at :ref:`sofa_hd_circuit_design_io`.
.. _sofa_hd_circuit_design_mux:
Multiplexer
^^^^^^^^^^^
QLSOFA HD FPGA share the same multiplexer design as SOFA HD FPGA.
See details at :ref:`sofa_hd_circuit_design_mux`.

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DOC/source/datasheet/sofa_chd/figures/custom_mux_cells.svg Normal file
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@ -0,0 +1,433 @@
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@ -10,3 +10,33 @@ I/O Circuit
SOFA CHD FPGA share the same I/O circuit design as SOFA HD FPGA.
See details at :ref:`sofa_hd_circuit_design_io`.
.. _sofa_hd_circuit_design_mux:
Multiplexer
^^^^^^^^^^^
Routing multiplexer are designed by using a few custom cells based on the Skywater *High-Density* (HD) PDK, as shown in :numref:`fig_sofa_chd_mux_circuit`.
The multiplexer design follows a two-level structure, which is applied to all the routing multiplexers in logic elements, connection blocks and switch blocks across the FPGA fabric.
.. _fig_sofa_chd_mux_circuit:
.. figure:: ./figures/sofa_chd_mux_circuit.svg
:scale: 30%
:alt: Schematic of multiplexer design in SOFA CHD FPGA
Schematic of multiplexer design in SOFA CHD FPGA
Each primitive in the two-level structure could be a 2/3/4-input custom cell, depending on the input size of the routing multiplexer.
Each custom cell is built with input inverters and transmission-gates.
For instance, :numref:`fig_sofa_chd_custom_mux_cells` shows the transistor-level design of a 3-input custom cell.
.. _fig_sofa_chd_custom_mux_cells:
.. figure:: ./figures/custom_mux_cells.svg
:scale: 40%
:alt: Detailed schematic of a 3-input custom cell in SOFA CHD FPGA
Detailed schematic of a 3-input custom cell in SOFA CHD FPGA
.. note:: Each routing multiplexer has a dedicated input which is connected to ground (GND) signal. When it is not used, the output will be driven by the ground, working as a constant generator.

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@ -34,3 +34,21 @@ The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC,
:alt: Schematic of embedded I/O cell used in FPGA
Schematic of embedded I/O cell used in FPGA
.. _sofa_hd_circuit_design_mux:
Multiplexer
^^^^^^^^^^^
Routing multiplexer are designed by using the skywater *High-Density* (HD) 2-input MUX cell, as shown in :numref:`fig_sofa_hd_mux_circuit`.
The tree-like multiplexer design is applied to all the routing multiplexers in logic elements, connection blocks and switch blocks across the FPGA fabric.
.. _fig_sofa_hd_mux_circuit:
.. figure:: ./figures/sofa_hd_mux_circuit.svg
:scale: 30%
:alt: Schematic of multiplexer design in SOFA HD FPGA
Schematic of multiplexer design in SOFA HD FPGA
.. note:: Each routing multiplexer has a dedicated input which is connected to ground (GND) signal. When it is not used, the output will be driven by the ground, working as a constant generator.