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[HDL] Update caravel integration netlist with mpw-b tagged version

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tangxifan 2020-12-16 16:41:18 -07:00
parent efe404e62b
commit c0e521ed85
1 changed files with 2 additions and 0 deletions
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HDL/common/caravel_qlsofa_hd_rtl_include_netlists.v
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@ -45,6 +45,8 @@
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/housekeeping_spi.v"
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/clock_div.v"
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/storage_bridge_wb.v"
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/mprj_logic_high.v"
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/mprj2_logic_high.v"
// Use Post-PnR netlists of QLSOFA HD FPGA
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/user_project_wrapper.v"