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[SOFA_HD] Updated netlist and task

This commit is contained in:
Ganesh Gore 2020-12-14 01:14:14 -07:00
parent fa87753d62
commit 967905e046
82 changed files with 722204 additions and 0 deletions
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73
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/OpenFPGAEngine.info Normal file
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commit 3a80af3408bcc76d5d5a5fe4def15b3da7682ac3
Merge: c05de439 3f91b843
Author: Laboratory for Nano Integrated Systems (LNIS) <40280375+LNIS-Projects@users.noreply.github.com>
Date: Fri Nov 13 16:44:58 2020 -0700
Merge pull request #126 from LNIS-Projects/dev
Multiple Bug Fixes
commit 3f91b8433e9b46e04bf4f62a599106417f78422c
Author: tangxifan <tangxifan@gmail.com>
Date: Fri Nov 13 15:00:25 2020 -0700
[Tool] Change the i/o numbering to the clockwise sequence
commit 088198c8610b676f91e370a0c59ddae2c4bc2f7a
Author: tangxifan <tangxifan@gmail.com>
Date: Fri Nov 13 10:56:00 2020 -0700
[Tool] enhance error checking in fabric key parser
commit c05de43927390f1c29cabb83986bcbbca58b47ae
Merge: 32da241e cb025e98
Author: Laboratory for Nano Integrated Systems (LNIS) <40280375+LNIS-Projects@users.noreply.github.com>
Date: Thu Nov 12 21:12:05 2020 -0700
Merge pull request #124 from LNIS-Projects/dev
Add readthedoc Setting File
commit cb025e982f0523dc78caec2df7c9bc3596d58120
Author: tangxifan <tangxifan@gmail.com>
Date: Thu Nov 12 19:43:43 2020 -0700
[Doc] Add readthedoc setting file
On branch master
Your branch is up to date with 'origin/master'.
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modified: openfpga_flow/scripts/run_fpga_flow.py
modified: openfpga_flow/scripts/run_fpga_task.py
Untracked files:
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openfpga/openfpga
openfpga_flow/tasks/FPGA1212_FC_HD_SKY_task
openfpga_flow/tasks/FPGA1212_FLAT_HD_SKY_task
openfpga_flow/tasks/FPGA1212_HIER_SKY_SC_MS_task
openfpga_flow/tasks/FPGA1212_RESET_HD_SKY_task
openfpga_flow/tasks/FPGA128128_FLAT_task
openfpga_flow/tasks/FPGA1616_FLAT_task
openfpga_flow/tasks/FPGA22_FLAT_SKY_task
openfpga_flow/tasks/FPGA22_FLAT_task
openfpga_flow/tasks/FPGA22_FRAME_task
openfpga_flow/tasks/FPGA22_HIER_SKY_SC_MS_task
openfpga_flow/tasks/FPGA22_HIER_SKY_task
openfpga_flow/tasks/FPGA22_HIER_task
openfpga_flow/tasks/FPGA22_MB_task
openfpga_flow/tasks/FPGA22_MODULAR_task
openfpga_flow/tasks/FPGA22_SPY_task
openfpga_flow/tasks/FPGA3232_FLAT_task
openfpga_flow/tasks/FPGA44_FLAT_task
openfpga_flow/tasks/FPGA6464_FLAT_task
openfpga_flow/tasks/FPGA66_FLAT_task
openfpga_flow/tasks/FPGA88_FLAT_HD_SKY_task
openfpga_flow/tasks/FPGA88_FLAT_task
openfpga_flow/tasks/routing_test/
openfpga_flow/tasks/skywater_openfpga_task
vpr/vpr
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243
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SDC/disable_configure_ports.sdc Normal file
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#############################################
# Synopsys Design Constraints (SDC)
# For FPGA fabric
# Description: Disable configuration outputs of all the programmable cells for PnR
# Author: Xifan TANG
# Organization: University of Utah
# Date: Sun Nov 29 02:09:07 2020
#############################################
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram_inv
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/mode
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/mode_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/sram
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/sram
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/sram_inv
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/sram_inv
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/sram
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/sram
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/sram
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/sram_inv
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/sram_inv
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/sram_inv
set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR
set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR
set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR
set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR

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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
`define INITIAL_SIMULATION 1
`define AUTOCHECKED_SIMULATION 1
`define ENABLE_FORMAL_VERIFICATION 1
`define FORMAL_SIMULATION 1

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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
`include "./SRC/fpga_defines.v"
//
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v"
//
`include "./SRC/sub_module/inv_buf_passgate.v"
`include "./SRC/sub_module/arch_encoder.v"
`include "./SRC/sub_module/local_encoder.v"
`include "./SRC/sub_module/muxes.v"
`include "./SRC/sub_module/luts.v"
`include "./SRC/sub_module/wires.v"
`include "./SRC/sub_module/memories.v"
//
`include "./SRC/lb/logical_tile_io_mode_physical__iopad.v"
`include "./SRC/lb/logical_tile_io_mode_io_.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v"
`include "./SRC/lb/logical_tile_clb_mode_default__fle.v"
`include "./SRC/lb/logical_tile_clb_mode_clb_.v"
`include "./SRC/lb/grid_io_top_top.v"
`include "./SRC/lb/grid_io_right_right.v"
`include "./SRC/lb/grid_io_bottom_bottom.v"
`include "./SRC/lb/grid_io_left_left.v"
`include "./SRC/lb/grid_clb.v"
//
`include "./SRC/routing/sb_0__0_.v"
`include "./SRC/routing/sb_0__1_.v"
`include "./SRC/routing/sb_0__12_.v"
`include "./SRC/routing/sb_1__0_.v"
`include "./SRC/routing/sb_1__1_.v"
`include "./SRC/routing/sb_1__12_.v"
`include "./SRC/routing/sb_12__0_.v"
`include "./SRC/routing/sb_12__1_.v"
`include "./SRC/routing/sb_12__12_.v"
`include "./SRC/routing/cbx_1__0_.v"
`include "./SRC/routing/cbx_1__1_.v"
`include "./SRC/routing/cbx_1__12_.v"
`include "./SRC/routing/cby_0__1_.v"
`include "./SRC/routing/cby_1__1_.v"
`include "./SRC/routing/cby_12__1_.v"
//
`include "./SRC/fpga_top.v"

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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
`define ENABLE_TIMING 1
`define ENABLE_SIGNAL_INITIALIZATION 1
`define ICARUS_SIMULATOR 1

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module grid_clb
( top_width_0_height_0__pin_0_, top_width_0_height_0__pin_1_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_3_, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_5_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_7_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_9_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_11_, top_width_0_height_0__pin_12_, top_width_0_height_0__pin_13_, top_width_0_height_0__pin_14_, top_width_0_height_0__pin_15_, top_width_0_height_0__pin_32_, top_width_0_height_0__pin_33_, right_width_0_height_0__pin_16_, right_width_0_height_0__pin_17_, right_width_0_height_0__pin_18_, right_width_0_height_0__pin_19_, right_width_0_height_0__pin_20_, right_width_0_height_0__pin_21_, right_width_0_height_0__pin_22_, right_width_0_height_0__pin_23_, right_width_0_height_0__pin_24_, right_width_0_height_0__pin_25_, right_width_0_height_0__pin_26_, right_width_0_height_0__pin_27_, right_width_0_height_0__pin_28_, right_width_0_height_0__pin_29_, right_width_0_height_0__pin_30_, right_width_0_height_0__pin_31_, ccff_head, top_width_0_height_0__pin_34_upper, top_width_0_height_0__pin_34_lower, top_width_0_height_0__pin_35_upper, top_width_0_height_0__pin_35_lower, top_width_0_height_0__pin_36_upper, top_width_0_height_0__pin_36_lower, top_width_0_height_0__pin_37_upper, top_width_0_height_0__pin_37_lower, top_width_0_height_0__pin_38_upper, top_width_0_height_0__pin_38_lower, top_width_0_height_0__pin_39_upper, top_width_0_height_0__pin_39_lower, top_width_0_height_0__pin_40_upper, top_width_0_height_0__pin_40_lower, top_width_0_height_0__pin_41_upper, top_width_0_height_0__pin_41_lower, right_width_0_height_0__pin_42_upper, right_width_0_height_0__pin_42_lower, right_width_0_height_0__pin_43_upper, right_width_0_height_0__pin_43_lower, right_width_0_height_0__pin_44_upper, right_width_0_height_0__pin_44_lower, right_width_0_height_0__pin_45_upper, right_width_0_height_0__pin_45_lower, right_width_0_height_0__pin_46_upper, right_width_0_height_0__pin_46_lower, right_width_0_height_0__pin_47_upper, right_width_0_height_0__pin_47_lower, right_width_0_height_0__pin_48_upper, right_width_0_height_0__pin_48_lower, right_width_0_height_0__pin_49_upper, right_width_0_height_0__pin_49_lower, bottom_width_0_height_0__pin_50_, bottom_width_0_height_0__pin_51_, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT, Test_en_E_in, Test_en_W_in, Test_en_W_out, Test_en_E_out, prog_clk_0_N_in, prog_clk_0_S_in, prog_clk_0_S_out, prog_clk_0_E_out, prog_clk_0_W_out, prog_clk_0_N_out, clk_0_N_in, clk_0_S_in );
input [0:0] top_width_0_height_0__pin_0_;
input [0:0] top_width_0_height_0__pin_1_;
input [0:0] top_width_0_height_0__pin_2_;
input [0:0] top_width_0_height_0__pin_3_;
input [0:0] top_width_0_height_0__pin_4_;
input [0:0] top_width_0_height_0__pin_5_;
input [0:0] top_width_0_height_0__pin_6_;
input [0:0] top_width_0_height_0__pin_7_;
input [0:0] top_width_0_height_0__pin_8_;
input [0:0] top_width_0_height_0__pin_9_;
input [0:0] top_width_0_height_0__pin_10_;
input [0:0] top_width_0_height_0__pin_11_;
input [0:0] top_width_0_height_0__pin_12_;
input [0:0] top_width_0_height_0__pin_13_;
input [0:0] top_width_0_height_0__pin_14_;
input [0:0] top_width_0_height_0__pin_15_;
input [0:0] top_width_0_height_0__pin_32_;
input [0:0] top_width_0_height_0__pin_33_;
input [0:0] right_width_0_height_0__pin_16_;
input [0:0] right_width_0_height_0__pin_17_;
input [0:0] right_width_0_height_0__pin_18_;
input [0:0] right_width_0_height_0__pin_19_;
input [0:0] right_width_0_height_0__pin_20_;
input [0:0] right_width_0_height_0__pin_21_;
input [0:0] right_width_0_height_0__pin_22_;
input [0:0] right_width_0_height_0__pin_23_;
input [0:0] right_width_0_height_0__pin_24_;
input [0:0] right_width_0_height_0__pin_25_;
input [0:0] right_width_0_height_0__pin_26_;
input [0:0] right_width_0_height_0__pin_27_;
input [0:0] right_width_0_height_0__pin_28_;
input [0:0] right_width_0_height_0__pin_29_;
input [0:0] right_width_0_height_0__pin_30_;
input [0:0] right_width_0_height_0__pin_31_;
input [0:0] ccff_head;
output [0:0] top_width_0_height_0__pin_34_upper;
output [0:0] top_width_0_height_0__pin_34_lower;
output [0:0] top_width_0_height_0__pin_35_upper;
output [0:0] top_width_0_height_0__pin_35_lower;
output [0:0] top_width_0_height_0__pin_36_upper;
output [0:0] top_width_0_height_0__pin_36_lower;
output [0:0] top_width_0_height_0__pin_37_upper;
output [0:0] top_width_0_height_0__pin_37_lower;
output [0:0] top_width_0_height_0__pin_38_upper;
output [0:0] top_width_0_height_0__pin_38_lower;
output [0:0] top_width_0_height_0__pin_39_upper;
output [0:0] top_width_0_height_0__pin_39_lower;
output [0:0] top_width_0_height_0__pin_40_upper;
output [0:0] top_width_0_height_0__pin_40_lower;
output [0:0] top_width_0_height_0__pin_41_upper;
output [0:0] top_width_0_height_0__pin_41_lower;
output [0:0] right_width_0_height_0__pin_42_upper;
output [0:0] right_width_0_height_0__pin_42_lower;
output [0:0] right_width_0_height_0__pin_43_upper;
output [0:0] right_width_0_height_0__pin_43_lower;
output [0:0] right_width_0_height_0__pin_44_upper;
output [0:0] right_width_0_height_0__pin_44_lower;
output [0:0] right_width_0_height_0__pin_45_upper;
output [0:0] right_width_0_height_0__pin_45_lower;
output [0:0] right_width_0_height_0__pin_46_upper;
output [0:0] right_width_0_height_0__pin_46_lower;
output [0:0] right_width_0_height_0__pin_47_upper;
output [0:0] right_width_0_height_0__pin_47_lower;
output [0:0] right_width_0_height_0__pin_48_upper;
output [0:0] right_width_0_height_0__pin_48_lower;
output [0:0] right_width_0_height_0__pin_49_upper;
output [0:0] right_width_0_height_0__pin_49_lower;
output [0:0] bottom_width_0_height_0__pin_50_;
output [0:0] bottom_width_0_height_0__pin_51_;
output [0:0] ccff_tail;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
input Test_en_E_in;
input Test_en_W_in;
output Test_en_W_out;
output Test_en_E_out;
input prog_clk_0_N_in;
input prog_clk_0_S_in;
output prog_clk_0_S_out;
output prog_clk_0_E_out;
output prog_clk_0_W_out;
output prog_clk_0_N_out;
input clk_0_N_in;
input clk_0_S_in;
wire prog_clk_0;
wire clk_0;
wire [0:0] Test_en;
wire [0:0] clk;
wire [0:0] prog_clk;
assign top_width_0_height_0__pin_34_lower[0] = top_width_0_height_0__pin_34_upper[0];
assign top_width_0_height_0__pin_35_lower[0] = top_width_0_height_0__pin_35_upper[0];
assign top_width_0_height_0__pin_36_lower[0] = top_width_0_height_0__pin_36_upper[0];
assign top_width_0_height_0__pin_37_lower[0] = top_width_0_height_0__pin_37_upper[0];
assign top_width_0_height_0__pin_38_lower[0] = top_width_0_height_0__pin_38_upper[0];
assign top_width_0_height_0__pin_39_lower[0] = top_width_0_height_0__pin_39_upper[0];
assign top_width_0_height_0__pin_40_lower[0] = top_width_0_height_0__pin_40_upper[0];
assign top_width_0_height_0__pin_41_lower[0] = top_width_0_height_0__pin_41_upper[0];
assign right_width_0_height_0__pin_42_lower[0] = right_width_0_height_0__pin_42_upper[0];
assign right_width_0_height_0__pin_43_lower[0] = right_width_0_height_0__pin_43_upper[0];
assign right_width_0_height_0__pin_44_lower[0] = right_width_0_height_0__pin_44_upper[0];
assign right_width_0_height_0__pin_45_lower[0] = right_width_0_height_0__pin_45_upper[0];
assign right_width_0_height_0__pin_46_lower[0] = right_width_0_height_0__pin_46_upper[0];
assign right_width_0_height_0__pin_47_lower[0] = right_width_0_height_0__pin_47_upper[0];
assign right_width_0_height_0__pin_48_lower[0] = right_width_0_height_0__pin_48_upper[0];
assign right_width_0_height_0__pin_49_lower[0] = right_width_0_height_0__pin_49_upper[0];
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;
assign Test_en_E_in = Test_en_W_in;
assign prog_clk_0 = prog_clk;
assign prog_clk_0_N_in = prog_clk_0_S_in;
assign clk = clk_0;
assign clk_0_N_in = clk_0_S_in;
logical_tile_clb_mode_clb_
logical_tile_clb_mode_clb__0
(
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clb_I0({ top_width_0_height_0__pin_0_[0], top_width_0_height_0__pin_1_[0], top_width_0_height_0__pin_2_[0] }),
.clb_I0i(top_width_0_height_0__pin_3_[0]),
.clb_I1({ top_width_0_height_0__pin_4_[0], top_width_0_height_0__pin_5_[0], top_width_0_height_0__pin_6_[0] }),
.clb_I1i(top_width_0_height_0__pin_7_[0]),
.clb_I2({ top_width_0_height_0__pin_8_[0], top_width_0_height_0__pin_9_[0], top_width_0_height_0__pin_10_[0] }),
.clb_I2i(top_width_0_height_0__pin_11_[0]),
.clb_I3({ top_width_0_height_0__pin_12_[0], top_width_0_height_0__pin_13_[0], top_width_0_height_0__pin_14_[0] }),
.clb_I3i(top_width_0_height_0__pin_15_[0]),
.clb_I4({ right_width_0_height_0__pin_16_[0], right_width_0_height_0__pin_17_[0], right_width_0_height_0__pin_18_[0] }),
.clb_I4i(right_width_0_height_0__pin_19_[0]),
.clb_I5({ right_width_0_height_0__pin_20_[0], right_width_0_height_0__pin_21_[0], right_width_0_height_0__pin_22_[0] }),
.clb_I5i(right_width_0_height_0__pin_23_[0]),
.clb_I6({ right_width_0_height_0__pin_24_[0], right_width_0_height_0__pin_25_[0], right_width_0_height_0__pin_26_[0] }),
.clb_I6i(right_width_0_height_0__pin_27_[0]),
.clb_I7({ right_width_0_height_0__pin_28_[0], right_width_0_height_0__pin_29_[0], right_width_0_height_0__pin_30_[0] }),
.clb_I7i(right_width_0_height_0__pin_31_[0]),
.clb_reg_in(top_width_0_height_0__pin_32_[0]),
.clb_sc_in(SC_IN_TOP),
.clb_clk(clk[0]),
.ccff_head(ccff_head[0]),
.clb_O({ top_width_0_height_0__pin_34_upper[0], top_width_0_height_0__pin_35_upper[0], top_width_0_height_0__pin_36_upper[0], top_width_0_height_0__pin_37_upper[0], top_width_0_height_0__pin_38_upper[0], top_width_0_height_0__pin_39_upper[0], top_width_0_height_0__pin_40_upper[0], top_width_0_height_0__pin_41_upper[0], right_width_0_height_0__pin_42_upper[0], right_width_0_height_0__pin_43_upper[0], right_width_0_height_0__pin_44_upper[0], right_width_0_height_0__pin_45_upper[0], right_width_0_height_0__pin_46_upper[0], right_width_0_height_0__pin_47_upper[0], right_width_0_height_0__pin_48_upper[0], right_width_0_height_0__pin_49_upper[0] }),
.clb_reg_out(bottom_width_0_height_0__pin_50_[0]),
.clb_sc_out(SC_OUT_BOT),
.ccff_tail(ccff_tail[0])
);
sky130_fd_sc_hd__buf_8
Test_en_FTB00
(
.A(Test_en_E_in),
.X(Test_en)
);
sky130_fd_sc_hd__buf_4
Test_en_W_FTB01
(
.A(Test_en_E_in),
.X(Test_en_W_out)
);
sky130_fd_sc_hd__buf_4
Test_en_E_FTB01
(
.A(Test_en_E_in),
.X(Test_en_E_out)
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_N_in),
.X(prog_clk_0)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_S_FTB01
(
.A(prog_clk_0_N_in),
.X(prog_clk_0_S_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_E_FTB01
(
.A(prog_clk_0_N_in),
.X(prog_clk_0_E_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_W_FTB01
(
.A(prog_clk_0_N_in),
.X(prog_clk_0_W_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_N_FTB01
(
.A(prog_clk_0_N_in),
.X(prog_clk_0_N_out)
);
sky130_fd_sc_hd__buf_8
clk_0_FTB00
(
.A(clk_0_N_in),
.X(clk_0)
);
endmodule

619
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v Normal file
View File

@ -0,0 +1,619 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module logical_tile_clb_mode_clb_(prog_clk,
Test_en,
clb_I0,
clb_I0i,
clb_I1,
clb_I1i,
clb_I2,
clb_I2i,
clb_I3,
clb_I3i,
clb_I4,
clb_I4i,
clb_I5,
clb_I5i,
clb_I6,
clb_I6i,
clb_I7,
clb_I7i,
clb_reg_in,
clb_sc_in,
clb_clk,
ccff_head,
clb_O,
clb_reg_out,
clb_sc_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] Test_en;
//
input [0:2] clb_I0;
//
input [0:0] clb_I0i;
//
input [0:2] clb_I1;
//
input [0:0] clb_I1i;
//
input [0:2] clb_I2;
//
input [0:0] clb_I2i;
//
input [0:2] clb_I3;
//
input [0:0] clb_I3i;
//
input [0:2] clb_I4;
//
input [0:0] clb_I4i;
//
input [0:2] clb_I5;
//
input [0:0] clb_I5i;
//
input [0:2] clb_I6;
//
input [0:0] clb_I6i;
//
input [0:2] clb_I7;
//
input [0:0] clb_I7i;
//
input [0:0] clb_reg_in;
//
input [0:0] clb_sc_in;
//
input [0:0] clb_clk;
//
input [0:0] ccff_head;
//
output [0:15] clb_O;
//
output [0:0] clb_reg_out;
//
output [0:0] clb_sc_out;
//
output [0:0] ccff_tail;
//
wire [0:2] clb_I0;
wire [0:0] clb_I0i;
wire [0:2] clb_I1;
wire [0:0] clb_I1i;
wire [0:2] clb_I2;
wire [0:0] clb_I2i;
wire [0:2] clb_I3;
wire [0:0] clb_I3i;
wire [0:2] clb_I4;
wire [0:0] clb_I4i;
wire [0:2] clb_I5;
wire [0:0] clb_I5i;
wire [0:2] clb_I6;
wire [0:0] clb_I6i;
wire [0:2] clb_I7;
wire [0:0] clb_I7i;
wire [0:0] clb_reg_in;
wire [0:0] clb_sc_in;
wire [0:0] clb_clk;
wire [0:15] clb_O;
wire [0:0] clb_reg_out;
wire [0:0] clb_sc_out;
//
//
//
wire [0:0] direct_interc_18_out;
wire [0:0] direct_interc_19_out;
wire [0:0] direct_interc_20_out;
wire [0:0] direct_interc_21_out;
wire [0:0] direct_interc_22_out;
wire [0:0] direct_interc_23_out;
wire [0:0] direct_interc_24_out;
wire [0:0] direct_interc_25_out;
wire [0:0] direct_interc_26_out;
wire [0:0] direct_interc_27_out;
wire [0:0] direct_interc_28_out;
wire [0:0] direct_interc_29_out;
wire [0:0] direct_interc_30_out;
wire [0:0] direct_interc_31_out;
wire [0:0] direct_interc_32_out;
wire [0:0] direct_interc_33_out;
wire [0:0] direct_interc_34_out;
wire [0:0] direct_interc_35_out;
wire [0:0] direct_interc_36_out;
wire [0:0] direct_interc_37_out;
wire [0:0] direct_interc_38_out;
wire [0:0] direct_interc_39_out;
wire [0:0] direct_interc_40_out;
wire [0:0] direct_interc_41_out;
wire [0:0] direct_interc_42_out;
wire [0:0] direct_interc_43_out;
wire [0:0] direct_interc_44_out;
wire [0:0] direct_interc_45_out;
wire [0:0] direct_interc_46_out;
wire [0:0] direct_interc_47_out;
wire [0:0] direct_interc_48_out;
wire [0:0] direct_interc_49_out;
wire [0:0] direct_interc_50_out;
wire [0:0] direct_interc_51_out;
wire [0:0] direct_interc_52_out;
wire [0:0] direct_interc_53_out;
wire [0:0] direct_interc_54_out;
wire [0:0] direct_interc_55_out;
wire [0:0] direct_interc_56_out;
wire [0:0] direct_interc_57_out;
wire [0:0] direct_interc_58_out;
wire [0:0] direct_interc_59_out;
wire [0:0] direct_interc_60_out;
wire [0:0] direct_interc_61_out;
wire [0:0] direct_interc_62_out;
wire [0:0] direct_interc_63_out;
wire [0:0] direct_interc_64_out;
wire [0:0] direct_interc_65_out;
wire [0:0] direct_interc_66_out;
wire [0:0] direct_interc_67_out;
wire [0:0] direct_interc_68_out;
wire [0:0] direct_interc_69_out;
wire [0:0] direct_interc_70_out;
wire [0:0] direct_interc_71_out;
wire [0:0] direct_interc_72_out;
wire [0:0] direct_interc_73_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_0_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_1_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_2_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_4_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_5_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out;
wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_6_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out;
wire [0:1] logical_tile_clb_mode_default__fle_7_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_7_fle_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out;
//
//
//
//
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_18_out[0], direct_interc_19_out[0], direct_interc_20_out[0], direct_interc_21_out[0]}),
.fle_reg_in(direct_interc_22_out[0]),
.fle_sc_in(direct_interc_23_out[0]),
.fle_clk(direct_interc_24_out[0]),
.ccff_head(ccff_head[0]),
.fle_out(logical_tile_clb_mode_default__fle_0_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_0_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_25_out[0], direct_interc_26_out[0], direct_interc_27_out[0], direct_interc_28_out[0]}),
.fle_reg_in(direct_interc_29_out[0]),
.fle_sc_in(direct_interc_30_out[0]),
.fle_clk(direct_interc_31_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_1_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_1_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_32_out[0], direct_interc_33_out[0], direct_interc_34_out[0], direct_interc_35_out[0]}),
.fle_reg_in(direct_interc_36_out[0]),
.fle_sc_in(direct_interc_37_out[0]),
.fle_clk(direct_interc_38_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_2_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_2_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_39_out[0], direct_interc_40_out[0], direct_interc_41_out[0], direct_interc_42_out[0]}),
.fle_reg_in(direct_interc_43_out[0]),
.fle_sc_in(direct_interc_44_out[0]),
.fle_clk(direct_interc_45_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_3_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_3_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_46_out[0], direct_interc_47_out[0], direct_interc_48_out[0], direct_interc_49_out[0]}),
.fle_reg_in(direct_interc_50_out[0]),
.fle_sc_in(direct_interc_51_out[0]),
.fle_clk(direct_interc_52_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_4_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_4_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_53_out[0], direct_interc_54_out[0], direct_interc_55_out[0], direct_interc_56_out[0]}),
.fle_reg_in(direct_interc_57_out[0]),
.fle_sc_in(direct_interc_58_out[0]),
.fle_clk(direct_interc_59_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_5_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_5_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_60_out[0], direct_interc_61_out[0], direct_interc_62_out[0], direct_interc_63_out[0]}),
.fle_reg_in(direct_interc_64_out[0]),
.fle_sc_in(direct_interc_65_out[0]),
.fle_clk(direct_interc_66_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_6_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_6_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail[0]));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fle_in({direct_interc_67_out[0], direct_interc_68_out[0], direct_interc_69_out[0], direct_interc_70_out[0]}),
.fle_reg_in(direct_interc_71_out[0]),
.fle_sc_in(direct_interc_72_out[0]),
.fle_clk(direct_interc_73_out[0]),
.ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail[0]),
.fle_out(logical_tile_clb_mode_default__fle_7_fle_out[0:1]),
.fle_reg_out(logical_tile_clb_mode_default__fle_7_fle_reg_out[0]),
.fle_sc_out(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]),
.ccff_tail(ccff_tail[0]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_0_fle_out[1]),
.out(clb_O[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_0_fle_out[0]),
.out(clb_O[1]));
direct_interc direct_interc_2_ (
.in(logical_tile_clb_mode_default__fle_1_fle_out[1]),
.out(clb_O[2]));
direct_interc direct_interc_3_ (
.in(logical_tile_clb_mode_default__fle_1_fle_out[0]),
.out(clb_O[3]));
direct_interc direct_interc_4_ (
.in(logical_tile_clb_mode_default__fle_2_fle_out[1]),
.out(clb_O[4]));
direct_interc direct_interc_5_ (
.in(logical_tile_clb_mode_default__fle_2_fle_out[0]),
.out(clb_O[5]));
direct_interc direct_interc_6_ (
.in(logical_tile_clb_mode_default__fle_3_fle_out[1]),
.out(clb_O[6]));
direct_interc direct_interc_7_ (
.in(logical_tile_clb_mode_default__fle_3_fle_out[0]),
.out(clb_O[7]));
direct_interc direct_interc_8_ (
.in(logical_tile_clb_mode_default__fle_4_fle_out[1]),
.out(clb_O[8]));
direct_interc direct_interc_9_ (
.in(logical_tile_clb_mode_default__fle_4_fle_out[0]),
.out(clb_O[9]));
direct_interc direct_interc_10_ (
.in(logical_tile_clb_mode_default__fle_5_fle_out[1]),
.out(clb_O[10]));
direct_interc direct_interc_11_ (
.in(logical_tile_clb_mode_default__fle_5_fle_out[0]),
.out(clb_O[11]));
direct_interc direct_interc_12_ (
.in(logical_tile_clb_mode_default__fle_6_fle_out[1]),
.out(clb_O[12]));
direct_interc direct_interc_13_ (
.in(logical_tile_clb_mode_default__fle_6_fle_out[0]),
.out(clb_O[13]));
direct_interc direct_interc_14_ (
.in(logical_tile_clb_mode_default__fle_7_fle_out[1]),
.out(clb_O[14]));
direct_interc direct_interc_15_ (
.in(logical_tile_clb_mode_default__fle_7_fle_out[0]),
.out(clb_O[15]));
direct_interc direct_interc_16_ (
.in(logical_tile_clb_mode_default__fle_7_fle_reg_out[0]),
.out(clb_reg_out[0]));
direct_interc direct_interc_17_ (
.in(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]),
.out(clb_sc_out[0]));
direct_interc direct_interc_18_ (
.in(clb_I0[0]),
.out(direct_interc_18_out[0]));
direct_interc direct_interc_19_ (
.in(clb_I0[1]),
.out(direct_interc_19_out[0]));
direct_interc direct_interc_20_ (
.in(clb_I0[2]),
.out(direct_interc_20_out[0]));
direct_interc direct_interc_21_ (
.in(clb_I0i[0]),
.out(direct_interc_21_out[0]));
direct_interc direct_interc_22_ (
.in(clb_reg_in[0]),
.out(direct_interc_22_out[0]));
direct_interc direct_interc_23_ (
.in(clb_sc_in[0]),
.out(direct_interc_23_out[0]));
direct_interc direct_interc_24_ (
.in(clb_clk[0]),
.out(direct_interc_24_out[0]));
direct_interc direct_interc_25_ (
.in(clb_I1[0]),
.out(direct_interc_25_out[0]));
direct_interc direct_interc_26_ (
.in(clb_I1[1]),
.out(direct_interc_26_out[0]));
direct_interc direct_interc_27_ (
.in(clb_I1[2]),
.out(direct_interc_27_out[0]));
direct_interc direct_interc_28_ (
.in(clb_I1i[0]),
.out(direct_interc_28_out[0]));
direct_interc direct_interc_29_ (
.in(logical_tile_clb_mode_default__fle_0_fle_reg_out[0]),
.out(direct_interc_29_out[0]));
direct_interc direct_interc_30_ (
.in(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]),
.out(direct_interc_30_out[0]));
direct_interc direct_interc_31_ (
.in(clb_clk[0]),
.out(direct_interc_31_out[0]));
direct_interc direct_interc_32_ (
.in(clb_I2[0]),
.out(direct_interc_32_out[0]));
direct_interc direct_interc_33_ (
.in(clb_I2[1]),
.out(direct_interc_33_out[0]));
direct_interc direct_interc_34_ (
.in(clb_I2[2]),
.out(direct_interc_34_out[0]));
direct_interc direct_interc_35_ (
.in(clb_I2i[0]),
.out(direct_interc_35_out[0]));
direct_interc direct_interc_36_ (
.in(logical_tile_clb_mode_default__fle_1_fle_reg_out[0]),
.out(direct_interc_36_out[0]));
direct_interc direct_interc_37_ (
.in(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]),
.out(direct_interc_37_out[0]));
direct_interc direct_interc_38_ (
.in(clb_clk[0]),
.out(direct_interc_38_out[0]));
direct_interc direct_interc_39_ (
.in(clb_I3[0]),
.out(direct_interc_39_out[0]));
direct_interc direct_interc_40_ (
.in(clb_I3[1]),
.out(direct_interc_40_out[0]));
direct_interc direct_interc_41_ (
.in(clb_I3[2]),
.out(direct_interc_41_out[0]));
direct_interc direct_interc_42_ (
.in(clb_I3i[0]),
.out(direct_interc_42_out[0]));
direct_interc direct_interc_43_ (
.in(logical_tile_clb_mode_default__fle_2_fle_reg_out[0]),
.out(direct_interc_43_out[0]));
direct_interc direct_interc_44_ (
.in(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]),
.out(direct_interc_44_out[0]));
direct_interc direct_interc_45_ (
.in(clb_clk[0]),
.out(direct_interc_45_out[0]));
direct_interc direct_interc_46_ (
.in(clb_I4[0]),
.out(direct_interc_46_out[0]));
direct_interc direct_interc_47_ (
.in(clb_I4[1]),
.out(direct_interc_47_out[0]));
direct_interc direct_interc_48_ (
.in(clb_I4[2]),
.out(direct_interc_48_out[0]));
direct_interc direct_interc_49_ (
.in(clb_I4i[0]),
.out(direct_interc_49_out[0]));
direct_interc direct_interc_50_ (
.in(logical_tile_clb_mode_default__fle_3_fle_reg_out[0]),
.out(direct_interc_50_out[0]));
direct_interc direct_interc_51_ (
.in(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]),
.out(direct_interc_51_out[0]));
direct_interc direct_interc_52_ (
.in(clb_clk[0]),
.out(direct_interc_52_out[0]));
direct_interc direct_interc_53_ (
.in(clb_I5[0]),
.out(direct_interc_53_out[0]));
direct_interc direct_interc_54_ (
.in(clb_I5[1]),
.out(direct_interc_54_out[0]));
direct_interc direct_interc_55_ (
.in(clb_I5[2]),
.out(direct_interc_55_out[0]));
direct_interc direct_interc_56_ (
.in(clb_I5i[0]),
.out(direct_interc_56_out[0]));
direct_interc direct_interc_57_ (
.in(logical_tile_clb_mode_default__fle_4_fle_reg_out[0]),
.out(direct_interc_57_out[0]));
direct_interc direct_interc_58_ (
.in(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]),
.out(direct_interc_58_out[0]));
direct_interc direct_interc_59_ (
.in(clb_clk[0]),
.out(direct_interc_59_out[0]));
direct_interc direct_interc_60_ (
.in(clb_I6[0]),
.out(direct_interc_60_out[0]));
direct_interc direct_interc_61_ (
.in(clb_I6[1]),
.out(direct_interc_61_out[0]));
direct_interc direct_interc_62_ (
.in(clb_I6[2]),
.out(direct_interc_62_out[0]));
direct_interc direct_interc_63_ (
.in(clb_I6i[0]),
.out(direct_interc_63_out[0]));
direct_interc direct_interc_64_ (
.in(logical_tile_clb_mode_default__fle_5_fle_reg_out[0]),
.out(direct_interc_64_out[0]));
direct_interc direct_interc_65_ (
.in(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]),
.out(direct_interc_65_out[0]));
direct_interc direct_interc_66_ (
.in(clb_clk[0]),
.out(direct_interc_66_out[0]));
direct_interc direct_interc_67_ (
.in(clb_I7[0]),
.out(direct_interc_67_out[0]));
direct_interc direct_interc_68_ (
.in(clb_I7[1]),
.out(direct_interc_68_out[0]));
direct_interc direct_interc_69_ (
.in(clb_I7[2]),
.out(direct_interc_69_out[0]));
direct_interc direct_interc_70_ (
.in(clb_I7i[0]),
.out(direct_interc_70_out[0]));
direct_interc direct_interc_71_ (
.in(logical_tile_clb_mode_default__fle_6_fle_reg_out[0]),
.out(direct_interc_71_out[0]));
direct_interc direct_interc_72_ (
.in(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]),
.out(direct_interc_72_out[0]));
direct_interc direct_interc_73_ (
.in(clb_clk[0]),
.out(direct_interc_73_out[0]));
endmodule
//
//

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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module logical_tile_clb_mode_default__fle(prog_clk,
Test_en,
fle_in,
fle_reg_in,
fle_sc_in,
fle_clk,
ccff_head,
fle_out,
fle_reg_out,
fle_sc_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] Test_en;
//
input [0:3] fle_in;
//
input [0:0] fle_reg_in;
//
input [0:0] fle_sc_in;
//
input [0:0] fle_clk;
//
input [0:0] ccff_head;
//
output [0:1] fle_out;
//
output [0:0] fle_reg_out;
//
output [0:0] fle_sc_out;
//
output [0:0] ccff_tail;
//
wire [0:3] fle_in;
wire [0:0] fle_reg_in;
wire [0:0] fle_sc_in;
wire [0:0] fle_clk;
wire [0:1] fle_out;
wire [0:0] fle_reg_out;
wire [0:0] fle_sc_out;
//
//
//
wire [0:0] direct_interc_10_out;
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] direct_interc_8_out;
wire [0:0] direct_interc_9_out;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out;
//
//
//
//
logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.fabric_in({direct_interc_4_out[0], direct_interc_5_out[0], direct_interc_6_out[0], direct_interc_7_out[0]}),
.fabric_reg_in(direct_interc_8_out[0]),
.fabric_sc_in(direct_interc_9_out[0]),
.fabric_clk(direct_interc_10_out[0]),
.ccff_head(ccff_head[0]),
.fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0:1]),
.fabric_reg_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out[0]),
.fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]),
.ccff_tail(ccff_tail[0]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]),
.out(fle_out[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]),
.out(fle_out[1]));
direct_interc direct_interc_2_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_reg_out[0]),
.out(fle_reg_out[0]));
direct_interc direct_interc_3_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]),
.out(fle_sc_out[0]));
direct_interc direct_interc_4_ (
.in(fle_in[0]),
.out(direct_interc_4_out[0]));
direct_interc direct_interc_5_ (
.in(fle_in[1]),
.out(direct_interc_5_out[0]));
direct_interc direct_interc_6_ (
.in(fle_in[2]),
.out(direct_interc_6_out[0]));
direct_interc direct_interc_7_ (
.in(fle_in[3]),
.out(direct_interc_7_out[0]));
direct_interc direct_interc_8_ (
.in(fle_reg_in[0]),
.out(direct_interc_8_out[0]));
direct_interc direct_interc_9_ (
.in(fle_sc_in[0]),
.out(direct_interc_9_out[0]));
direct_interc direct_interc_10_ (
.in(fle_clk[0]),
.out(direct_interc_10_out[0]));
endmodule
//
//

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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module logical_tile_clb_mode_default__fle_mode_physical__fabric(prog_clk,
Test_en,
fabric_in,
fabric_reg_in,
fabric_sc_in,
fabric_clk,
ccff_head,
fabric_out,
fabric_reg_out,
fabric_sc_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] Test_en;
//
input [0:3] fabric_in;
//
input [0:0] fabric_reg_in;
//
input [0:0] fabric_sc_in;
//
input [0:0] fabric_clk;
//
input [0:0] ccff_head;
//
output [0:1] fabric_out;
//
output [0:0] fabric_reg_out;
//
output [0:0] fabric_sc_out;
//
output [0:0] ccff_tail;
//
wire [0:3] fabric_in;
wire [0:0] fabric_reg_in;
wire [0:0] fabric_sc_in;
wire [0:0] fabric_clk;
wire [0:1] fabric_out;
wire [0:0] fabric_reg_out;
wire [0:0] fabric_sc_out;
//
//
//
wire [0:0] direct_interc_2_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] direct_interc_8_out;
wire [0:0] direct_interc_9_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out;
wire [0:1] mux_fabric_out_0_undriven_sram_inv;
wire [0:1] mux_fabric_out_1_undriven_sram_inv;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv;
wire [0:1] mux_ff_1_D_0_undriven_sram_inv;
wire [0:1] mux_tree_size2_0_sram;
wire [0:1] mux_tree_size2_1_sram;
wire [0:0] mux_tree_size2_2_out;
wire [0:1] mux_tree_size2_2_sram;
wire [0:0] mux_tree_size2_3_out;
wire [0:1] mux_tree_size2_3_sram;
wire [0:0] mux_tree_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_size2_mem_2_ccff_tail;
//
//
//
//
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
.prog_clk(prog_clk[0]),
.frac_logic_in({direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0], direct_interc_5_out[0]}),
.ccff_head(ccff_head[0]),
.frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0:1]),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
.Test_en(Test_en[0]),
.ff_D(mux_tree_size2_2_out[0]),
.ff_DI(direct_interc_6_out[0]),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
.ff_clk(direct_interc_7_out[0]));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
.Test_en(Test_en[0]),
.ff_D(mux_tree_size2_3_out[0]),
.ff_DI(direct_interc_8_out[0]),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
.ff_clk(direct_interc_9_out[0]));
mux_tree_size2 mux_fabric_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}),
.sram(mux_tree_size2_0_sram[0:1]),
.sram_inv(mux_fabric_out_0_undriven_sram_inv[0:1]),
.out(fabric_out[0]));
mux_tree_size2 mux_fabric_out_1 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}),
.sram(mux_tree_size2_1_sram[0:1]),
.sram_inv(mux_fabric_out_1_undriven_sram_inv[0:1]),
.out(fabric_out[1]));
mux_tree_size2 mux_ff_0_D_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_reg_in[0]}),
.sram(mux_tree_size2_2_sram[0:1]),
.sram_inv(mux_ff_0_D_0_undriven_sram_inv[0:1]),
.out(mux_tree_size2_2_out[0]));
mux_tree_size2 mux_ff_1_D_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]}),
.sram(mux_tree_size2_3_sram[0:1]),
.sram_inv(mux_ff_1_D_0_undriven_sram_inv[0:1]),
.out(mux_tree_size2_3_out[0]));
mux_tree_size2_mem mem_fabric_out_0 (
.prog_clk(prog_clk[0]),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]),
.ccff_tail(mux_tree_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_size2_0_sram[0:1]));
mux_tree_size2_mem mem_fabric_out_1 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_size2_1_sram[0:1]));
mux_tree_size2_mem mem_ff_0_D_0 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_size2_2_sram[0:1]));
mux_tree_size2_mem mem_ff_1_D_0 (
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_size2_mem_2_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_size2_3_sram[0:1]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
.out(fabric_reg_out[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
.out(fabric_sc_out[0]));
direct_interc direct_interc_2_ (
.in(fabric_in[0]),
.out(direct_interc_2_out[0]));
direct_interc direct_interc_3_ (
.in(fabric_in[1]),
.out(direct_interc_3_out[0]));
direct_interc direct_interc_4_ (
.in(fabric_in[2]),
.out(direct_interc_4_out[0]));
direct_interc direct_interc_5_ (
.in(fabric_in[3]),
.out(direct_interc_5_out[0]));
direct_interc direct_interc_6_ (
.in(fabric_sc_in[0]),
.out(direct_interc_6_out[0]));
direct_interc direct_interc_7_ (
.in(fabric_clk[0]),
.out(direct_interc_7_out[0]));
direct_interc direct_interc_8_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
.out(direct_interc_8_out[0]));
direct_interc direct_interc_9_ (
.in(fabric_clk[0]),
.out(direct_interc_9_out[0]));
endmodule
//
//

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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff(Test_en,
ff_D,
ff_DI,
ff_Q,
ff_clk);
//
input [0:0] Test_en;
//
input [0:0] ff_D;
//
input [0:0] ff_DI;
//
output [0:0] ff_Q;
//
input [0:0] ff_clk;
//
wire [0:0] ff_D;
wire [0:0] ff_DI;
wire [0:0] ff_Q;
wire [0:0] ff_clk;
//
//
//
//
//
//
//
sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ (
.SCE(Test_en[0]),
.D(ff_D[0]),
.SCD(ff_DI[0]),
.CLK(ff_clk[0]),
.Q(ff_Q[0]));
endmodule
//

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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic(prog_clk,
frac_logic_in,
ccff_head,
frac_logic_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:3] frac_logic_in;
//
input [0:0] ccff_head;
//
output [0:1] frac_logic_out;
//
output [0:0] ccff_tail;
//
wire [0:3] frac_logic_in;
wire [0:1] frac_logic_out;
//
//
//
wire [0:0] direct_interc_1_out;
wire [0:0] direct_interc_2_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out;
wire [0:1] mux_frac_logic_out_0_undriven_sram_inv;
wire [0:1] mux_tree_size2_0_sram;
//
//
//
//
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
.prog_clk(prog_clk[0]),
.frac_lut4_in({direct_interc_1_out[0], direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0]}),
.ccff_head(ccff_head[0]),
.frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0:1]),
.frac_lut4_lut4_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail[0]));
mux_tree_size2 mux_frac_logic_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}),
.sram(mux_tree_size2_0_sram[0:1]),
.sram_inv(mux_frac_logic_out_0_undriven_sram_inv[0:1]),
.out(frac_logic_out[0]));
mux_tree_size2_mem mem_frac_logic_out_0 (
.prog_clk(prog_clk[0]),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_size2_0_sram[0:1]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]),
.out(frac_logic_out[1]));
direct_interc direct_interc_1_ (
.in(frac_logic_in[0]),
.out(direct_interc_1_out[0]));
direct_interc direct_interc_2_ (
.in(frac_logic_in[1]),
.out(direct_interc_2_out[0]));
direct_interc direct_interc_3_ (
.in(frac_logic_in[2]),
.out(direct_interc_3_out[0]));
direct_interc direct_interc_4_ (
.in(frac_logic_in[3]),
.out(direct_interc_4_out[0]));
endmodule
//
//

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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4(prog_clk,
frac_lut4_in,
ccff_head,
frac_lut4_lut3_out,
frac_lut4_lut4_out,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:3] frac_lut4_in;
//
input [0:0] ccff_head;
//
output [0:1] frac_lut4_lut3_out;
//
output [0:0] frac_lut4_lut4_out;
//
output [0:0] ccff_tail;
//
wire [0:3] frac_lut4_in;
wire [0:1] frac_lut4_lut3_out;
wire [0:0] frac_lut4_lut4_out;
//
//
//
wire [0:0] frac_lut4_0__undriven_mode_inv;
wire [0:15] frac_lut4_0__undriven_sram_inv;
wire [0:0] frac_lut4_0_mode;
wire [0:15] frac_lut4_0_sram;
//
//
//
//
frac_lut4 frac_lut4_0_ (
.in(frac_lut4_in[0:3]),
.sram(frac_lut4_0_sram[0:15]),
.sram_inv(frac_lut4_0__undriven_sram_inv[0:15]),
.mode(frac_lut4_0_mode[0]),
.mode_inv(frac_lut4_0__undriven_mode_inv[0]),
.lut3_out(frac_lut4_lut3_out[0:1]),
.lut4_out(frac_lut4_lut4_out[0]));
frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem (
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]),
.mem_out({frac_lut4_0_sram[0:15], frac_lut4_0_mode[0]}));
endmodule
//

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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module logical_tile_io_mode_io_(IO_ISOL_N,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
io_outpad,
ccff_head,
io_inpad,
ccff_tail);
//
input [0:0] IO_ISOL_N;
//
input [0:0] prog_clk;
//
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
//
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
//
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
//
input [0:0] io_outpad;
//
input [0:0] ccff_head;
//
output [0:0] io_inpad;
//
output [0:0] ccff_tail;
//
wire [0:0] io_outpad;
wire [0:0] io_inpad;
//
//
//
wire [0:0] direct_interc_1_out;
wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad;
//
//
//
//
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.iopad_outpad(direct_interc_1_out[0]),
.ccff_head(ccff_head[0]),
.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]),
.ccff_tail(ccff_tail[0]));
direct_interc direct_interc_0_ (
.in(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]),
.out(io_inpad[0]));
direct_interc direct_interc_1_ (
.in(io_outpad[0]),
.out(direct_interc_1_out[0]));
endmodule
//
//

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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module logical_tile_io_mode_physical__iopad(IO_ISOL_N,
prog_clk,
gfpga_pad_EMBEDDED_IO_HD_SOC_IN,
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT,
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR,
iopad_outpad,
ccff_head,
iopad_inpad,
ccff_tail);
//
input [0:0] IO_ISOL_N;
//
input [0:0] prog_clk;
//
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
//
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
//
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
//
input [0:0] iopad_outpad;
//
input [0:0] ccff_head;
//
output [0:0] iopad_inpad;
//
output [0:0] ccff_tail;
//
wire [0:0] iopad_outpad;
wire [0:0] iopad_inpad;
//
//
//
wire [0:0] EMBEDDED_IO_HD_0_en;
//
//
//
//
EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
.IO_ISOL_N(IO_ISOL_N[0]),
.SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.FPGA_OUT(iopad_outpad[0]),
.FPGA_DIR(EMBEDDED_IO_HD_0_en[0]),
.FPGA_IN(iopad_inpad[0]));
EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem (
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(EMBEDDED_IO_HD_0_en[0]));
endmodule
//

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module cbx_1__0_
( chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_2_, bottom_grid_pin_4_, bottom_grid_pin_6_, bottom_grid_pin_8_, bottom_grid_pin_10_, bottom_grid_pin_12_, bottom_grid_pin_14_, bottom_grid_pin_16_, ccff_tail, IO_ISOL_N, gfpga_pad_EMBEDDED_IO_HD_SOC_IN, gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_12_, top_width_0_height_0__pin_14_, top_width_0_height_0__pin_16_, top_width_0_height_0__pin_1_upper, top_width_0_height_0__pin_1_lower, top_width_0_height_0__pin_3_upper, top_width_0_height_0__pin_3_lower, top_width_0_height_0__pin_5_upper, top_width_0_height_0__pin_5_lower, top_width_0_height_0__pin_7_upper, top_width_0_height_0__pin_7_lower, top_width_0_height_0__pin_9_upper, top_width_0_height_0__pin_9_lower, top_width_0_height_0__pin_11_upper, top_width_0_height_0__pin_11_lower, top_width_0_height_0__pin_13_upper, top_width_0_height_0__pin_13_lower, top_width_0_height_0__pin_15_upper, top_width_0_height_0__pin_15_lower, top_width_0_height_0__pin_17_upper, top_width_0_height_0__pin_17_lower, SC_IN_TOP, SC_OUT_BOT, SC_IN_BOT, SC_OUT_TOP, prog_clk_0_N_in, prog_clk_0_W_out );
input [0:19] chanx_left_in;
input [0:19] chanx_right_in;
input [0:0] ccff_head;
output [0:19] chanx_left_out;
output [0:19] chanx_right_out;
output [0:0] bottom_grid_pin_0_;
output [0:0] bottom_grid_pin_2_;
output [0:0] bottom_grid_pin_4_;
output [0:0] bottom_grid_pin_6_;
output [0:0] bottom_grid_pin_8_;
output [0:0] bottom_grid_pin_10_;
output [0:0] bottom_grid_pin_12_;
output [0:0] bottom_grid_pin_14_;
output [0:0] bottom_grid_pin_16_;
output [0:0] ccff_tail;
input [0:0] IO_ISOL_N;
input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
input [0:0] top_width_0_height_0__pin_0_;
input [0:0] top_width_0_height_0__pin_2_;
input [0:0] top_width_0_height_0__pin_4_;
input [0:0] top_width_0_height_0__pin_6_;
input [0:0] top_width_0_height_0__pin_8_;
input [0:0] top_width_0_height_0__pin_10_;
input [0:0] top_width_0_height_0__pin_12_;
input [0:0] top_width_0_height_0__pin_14_;
input [0:0] top_width_0_height_0__pin_16_;
output [0:0] top_width_0_height_0__pin_1_upper;
output [0:0] top_width_0_height_0__pin_1_lower;
output [0:0] top_width_0_height_0__pin_3_upper;
output [0:0] top_width_0_height_0__pin_3_lower;
output [0:0] top_width_0_height_0__pin_5_upper;
output [0:0] top_width_0_height_0__pin_5_lower;
output [0:0] top_width_0_height_0__pin_7_upper;
output [0:0] top_width_0_height_0__pin_7_lower;
output [0:0] top_width_0_height_0__pin_9_upper;
output [0:0] top_width_0_height_0__pin_9_lower;
output [0:0] top_width_0_height_0__pin_11_upper;
output [0:0] top_width_0_height_0__pin_11_lower;
output [0:0] top_width_0_height_0__pin_13_upper;
output [0:0] top_width_0_height_0__pin_13_lower;
output [0:0] top_width_0_height_0__pin_15_upper;
output [0:0] top_width_0_height_0__pin_15_lower;
output [0:0] top_width_0_height_0__pin_17_upper;
output [0:0] top_width_0_height_0__pin_17_lower;
input SC_IN_TOP;
output SC_OUT_BOT;
input SC_IN_BOT;
output SC_OUT_TOP;
input prog_clk_0_N_in;
output prog_clk_0_W_out;
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
wire [0:3] mux_top_ipin_7_undriven_sram_inv;
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire ccff_tail_mid;
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
wire [0:0] logical_tile_io_mode_io__7_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chanx_right_out[0] = chanx_left_in[0];
assign chanx_right_out[1] = chanx_left_in[1];
assign chanx_right_out[2] = chanx_left_in[2];
assign chanx_right_out[3] = chanx_left_in[3];
assign chanx_right_out[4] = chanx_left_in[4];
assign chanx_right_out[5] = chanx_left_in[5];
assign chanx_right_out[6] = chanx_left_in[6];
assign chanx_right_out[7] = chanx_left_in[7];
assign chanx_right_out[8] = chanx_left_in[8];
assign chanx_right_out[9] = chanx_left_in[9];
assign chanx_right_out[10] = chanx_left_in[10];
assign chanx_right_out[11] = chanx_left_in[11];
assign chanx_right_out[12] = chanx_left_in[12];
assign chanx_right_out[13] = chanx_left_in[13];
assign chanx_right_out[14] = chanx_left_in[14];
assign chanx_right_out[15] = chanx_left_in[15];
assign chanx_right_out[16] = chanx_left_in[16];
assign chanx_right_out[17] = chanx_left_in[17];
assign chanx_right_out[18] = chanx_left_in[18];
assign chanx_right_out[19] = chanx_left_in[19];
assign chanx_left_out[0] = chanx_right_in[0];
assign chanx_left_out[1] = chanx_right_in[1];
assign chanx_left_out[2] = chanx_right_in[2];
assign chanx_left_out[3] = chanx_right_in[3];
assign chanx_left_out[4] = chanx_right_in[4];
assign chanx_left_out[5] = chanx_right_in[5];
assign chanx_left_out[6] = chanx_right_in[6];
assign chanx_left_out[7] = chanx_right_in[7];
assign chanx_left_out[8] = chanx_right_in[8];
assign chanx_left_out[9] = chanx_right_in[9];
assign chanx_left_out[10] = chanx_right_in[10];
assign chanx_left_out[11] = chanx_right_in[11];
assign chanx_left_out[12] = chanx_right_in[12];
assign chanx_left_out[13] = chanx_right_in[13];
assign chanx_left_out[14] = chanx_right_in[14];
assign chanx_left_out[15] = chanx_right_in[15];
assign chanx_left_out[16] = chanx_right_in[16];
assign chanx_left_out[17] = chanx_right_in[17];
assign chanx_left_out[18] = chanx_right_in[18];
assign chanx_left_out[19] = chanx_right_in[19];
assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0];
assign top_width_0_height_0__pin_3_lower[0] = top_width_0_height_0__pin_3_upper[0];
assign top_width_0_height_0__pin_5_lower[0] = top_width_0_height_0__pin_5_upper[0];
assign top_width_0_height_0__pin_7_lower[0] = top_width_0_height_0__pin_7_upper[0];
assign top_width_0_height_0__pin_9_lower[0] = top_width_0_height_0__pin_9_upper[0];
assign top_width_0_height_0__pin_11_lower[0] = top_width_0_height_0__pin_11_upper[0];
assign top_width_0_height_0__pin_13_lower[0] = top_width_0_height_0__pin_13_upper[0];
assign top_width_0_height_0__pin_15_lower[0] = top_width_0_height_0__pin_15_upper[0];
assign top_width_0_height_0__pin_17_lower[0] = top_width_0_height_0__pin_17_upper[0];
assign SC_OUT_BOT = SC_IN_TOP;
assign SC_OUT_TOP = SC_IN_BOT;
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size10
mux_top_ipin_0
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_1
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_2_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_2
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_4_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_3
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_6_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_4
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_8_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_5
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_10_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_6
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_12_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_7
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_14_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_8
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_16_[0])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.io_outpad(top_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(top_width_0_height_0__pin_1_upper[0]),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail[0])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__1
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1]),
.io_outpad(top_width_0_height_0__pin_2_[0]),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_3_upper[0]),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__2
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2]),
.io_outpad(top_width_0_height_0__pin_4_[0]),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_5_upper[0]),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__3
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3]),
.io_outpad(top_width_0_height_0__pin_6_[0]),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_7_upper[0]),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__4
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4]),
.io_outpad(top_width_0_height_0__pin_8_[0]),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_9_upper[0]),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__5
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5]),
.io_outpad(top_width_0_height_0__pin_10_[0]),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_11_upper[0]),
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail[0])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__6
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6]),
.io_outpad(top_width_0_height_0__pin_12_[0]),
.ccff_head(logical_tile_io_mode_io__5_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_13_upper[0]),
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail[0])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__7
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7]),
.io_outpad(top_width_0_height_0__pin_14_[0]),
.ccff_head(logical_tile_io_mode_io__6_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_15_upper[0]),
.ccff_tail(logical_tile_io_mode_io__7_ccff_tail[0])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__8
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8]),
.io_outpad(top_width_0_height_0__pin_16_[0]),
.ccff_head(logical_tile_io_mode_io__7_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_17_upper[0]),
.ccff_tail(ccff_tail[0])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_N_in),
.X(prog_clk_0)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_W_FTB01
(
.A(prog_clk_0_N_in),
.X(prog_clk_0_W_out)
);
endmodule

593
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/routing/cbx_1__1_.v Normal file
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@ -0,0 +1,593 @@
module cbx_1__1_
( chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, SC_IN_TOP, SC_OUT_BOT, SC_IN_BOT, SC_OUT_TOP, REGIN_FEEDTHROUGH, REGOUT_FEEDTHROUGH, prog_clk_0_N_in, prog_clk_0_W_out, prog_clk_1_W_in, prog_clk_1_E_in, prog_clk_1_N_out, prog_clk_1_S_out, prog_clk_2_E_in, prog_clk_2_W_in, prog_clk_2_W_out, prog_clk_2_E_out, prog_clk_3_W_in, prog_clk_3_E_in, prog_clk_3_E_out, prog_clk_3_W_out, clk_1_W_in, clk_1_E_in, clk_1_N_out, clk_1_S_out, clk_2_E_in, clk_2_W_in, clk_2_W_out, clk_2_E_out, clk_3_W_in, clk_3_E_in, clk_3_E_out, clk_3_W_out );
input [0:19] chanx_left_in;
input [0:19] chanx_right_in;
input [0:0] ccff_head;
output [0:19] chanx_left_out;
output [0:19] chanx_right_out;
output [0:0] bottom_grid_pin_0_;
output [0:0] bottom_grid_pin_1_;
output [0:0] bottom_grid_pin_2_;
output [0:0] bottom_grid_pin_3_;
output [0:0] bottom_grid_pin_4_;
output [0:0] bottom_grid_pin_5_;
output [0:0] bottom_grid_pin_6_;
output [0:0] bottom_grid_pin_7_;
output [0:0] bottom_grid_pin_8_;
output [0:0] bottom_grid_pin_9_;
output [0:0] bottom_grid_pin_10_;
output [0:0] bottom_grid_pin_11_;
output [0:0] bottom_grid_pin_12_;
output [0:0] bottom_grid_pin_13_;
output [0:0] bottom_grid_pin_14_;
output [0:0] bottom_grid_pin_15_;
output [0:0] ccff_tail;
input SC_IN_TOP;
output SC_OUT_BOT;
input SC_IN_BOT;
output SC_OUT_TOP;
input REGIN_FEEDTHROUGH;
output REGOUT_FEEDTHROUGH;
input prog_clk_0_N_in;
output prog_clk_0_W_out;
input prog_clk_1_W_in;
input prog_clk_1_E_in;
output prog_clk_1_N_out;
output prog_clk_1_S_out;
input prog_clk_2_E_in;
input prog_clk_2_W_in;
output prog_clk_2_W_out;
output prog_clk_2_E_out;
input prog_clk_3_W_in;
input prog_clk_3_E_in;
output prog_clk_3_E_out;
output prog_clk_3_W_out;
input clk_1_W_in;
input clk_1_E_in;
output clk_1_N_out;
output clk_1_S_out;
input clk_2_E_in;
input clk_2_W_in;
output clk_2_W_out;
output clk_2_E_out;
input clk_3_W_in;
input clk_3_E_in;
output clk_3_E_out;
output clk_3_W_out;
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_10_undriven_sram_inv;
wire [0:3] mux_top_ipin_11_undriven_sram_inv;
wire [0:3] mux_top_ipin_12_undriven_sram_inv;
wire [0:3] mux_top_ipin_13_undriven_sram_inv;
wire [0:3] mux_top_ipin_14_undriven_sram_inv;
wire [0:3] mux_top_ipin_15_undriven_sram_inv;
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
wire [0:3] mux_top_ipin_7_undriven_sram_inv;
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
wire [0:3] mux_top_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chanx_right_out[0] = chanx_left_in[0];
assign chanx_right_out[1] = chanx_left_in[1];
assign chanx_right_out[2] = chanx_left_in[2];
assign chanx_right_out[3] = chanx_left_in[3];
assign chanx_right_out[4] = chanx_left_in[4];
assign chanx_right_out[5] = chanx_left_in[5];
assign chanx_right_out[6] = chanx_left_in[6];
assign chanx_right_out[7] = chanx_left_in[7];
assign chanx_right_out[8] = chanx_left_in[8];
assign chanx_right_out[9] = chanx_left_in[9];
assign chanx_right_out[10] = chanx_left_in[10];
assign chanx_right_out[11] = chanx_left_in[11];
assign chanx_right_out[12] = chanx_left_in[12];
assign chanx_right_out[13] = chanx_left_in[13];
assign chanx_right_out[14] = chanx_left_in[14];
assign chanx_right_out[15] = chanx_left_in[15];
assign chanx_right_out[16] = chanx_left_in[16];
assign chanx_right_out[17] = chanx_left_in[17];
assign chanx_right_out[18] = chanx_left_in[18];
assign chanx_right_out[19] = chanx_left_in[19];
assign chanx_left_out[0] = chanx_right_in[0];
assign chanx_left_out[1] = chanx_right_in[1];
assign chanx_left_out[2] = chanx_right_in[2];
assign chanx_left_out[3] = chanx_right_in[3];
assign chanx_left_out[4] = chanx_right_in[4];
assign chanx_left_out[5] = chanx_right_in[5];
assign chanx_left_out[6] = chanx_right_in[6];
assign chanx_left_out[7] = chanx_right_in[7];
assign chanx_left_out[8] = chanx_right_in[8];
assign chanx_left_out[9] = chanx_right_in[9];
assign chanx_left_out[10] = chanx_right_in[10];
assign chanx_left_out[11] = chanx_right_in[11];
assign chanx_left_out[12] = chanx_right_in[12];
assign chanx_left_out[13] = chanx_right_in[13];
assign chanx_left_out[14] = chanx_right_in[14];
assign chanx_left_out[15] = chanx_right_in[15];
assign chanx_left_out[16] = chanx_right_in[16];
assign chanx_left_out[17] = chanx_right_in[17];
assign chanx_left_out[18] = chanx_right_in[18];
assign chanx_left_out[19] = chanx_right_in[19];
assign SC_OUT_BOT = SC_IN_TOP;
assign SC_OUT_TOP = SC_IN_BOT;
assign REGOUT_FEEDTHROUGH = REGIN_FEEDTHROUGH;
assign prog_clk_0 = prog_clk;
assign prog_clk_1_W_in = prog_clk_1_E_in;
assign prog_clk_2_E_in = prog_clk_2_W_in;
assign prog_clk_3_W_in = prog_clk_3_E_in;
assign clk_1_W_in = clk_1_E_in;
assign clk_2_E_in = clk_2_W_in;
assign clk_3_W_in = clk_3_E_in;
mux_tree_tapbuf_size10
mux_top_ipin_0
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_3
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_3_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_4
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_4_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_7
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_7_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_8
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_8_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_11
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_11_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_12
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_12_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_15
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_15_[0])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size8
mux_top_ipin_1
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_1_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_2
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_2_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_5
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_5_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_6
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_6_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_9
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_9_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_10
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_10_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_13
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_13_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_14
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_14_[0])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_N_in),
.X(prog_clk_0)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_W_FTB01
(
.A(prog_clk_0_N_in),
.X(prog_clk_0_W_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_1_N_FTB01
(
.A(prog_clk_1_W_in),
.X(prog_clk_1_N_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_1_S_FTB01
(
.A(prog_clk_1_W_in),
.X(prog_clk_1_S_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_2_W_FTB01
(
.A(prog_clk_2_E_in),
.X(prog_clk_2_W_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_2_E_FTB01
(
.A(prog_clk_2_E_in),
.X(prog_clk_2_E_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_3_E_FTB01
(
.A(prog_clk_3_W_in),
.X(prog_clk_3_E_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_3_W_FTB01
(
.A(prog_clk_3_W_in),
.X(prog_clk_3_W_out)
);
sky130_fd_sc_hd__buf_4
clk_1_N_FTB01
(
.A(clk_1_W_in),
.X(clk_1_N_out)
);
sky130_fd_sc_hd__buf_4
clk_1_S_FTB01
(
.A(clk_1_W_in),
.X(clk_1_S_out)
);
sky130_fd_sc_hd__buf_4
clk_2_W_FTB01
(
.A(clk_2_E_in),
.X(clk_2_W_out)
);
sky130_fd_sc_hd__buf_4
clk_2_E_FTB01
(
.A(clk_2_E_in),
.X(clk_2_E_out)
);
sky130_fd_sc_hd__buf_4
clk_3_E_FTB01
(
.A(clk_3_W_in),
.X(clk_3_E_out)
);
sky130_fd_sc_hd__buf_4
clk_3_W_FTB01
(
.A(clk_3_W_in),
.X(clk_3_W_out)
);
endmodule

512
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/routing/cbx_1__2_.v Normal file
View File

@ -0,0 +1,512 @@
module cbx_1__2_
( chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, top_grid_pin_0_, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, IO_ISOL_N, gfpga_pad_EMBEDDED_IO_HD_SOC_IN, gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, bottom_width_0_height_0__pin_0_, bottom_width_0_height_0__pin_1_upper, bottom_width_0_height_0__pin_1_lower, SC_IN_TOP, SC_OUT_BOT, SC_IN_BOT, SC_OUT_TOP, prog_clk_0_S_in, prog_clk_0_W_out );
input [0:19] chanx_left_in;
input [0:19] chanx_right_in;
input [0:0] ccff_head;
output [0:19] chanx_left_out;
output [0:19] chanx_right_out;
output [0:0] top_grid_pin_0_;
output [0:0] bottom_grid_pin_0_;
output [0:0] bottom_grid_pin_1_;
output [0:0] bottom_grid_pin_2_;
output [0:0] bottom_grid_pin_3_;
output [0:0] bottom_grid_pin_4_;
output [0:0] bottom_grid_pin_5_;
output [0:0] bottom_grid_pin_6_;
output [0:0] bottom_grid_pin_7_;
output [0:0] bottom_grid_pin_8_;
output [0:0] bottom_grid_pin_9_;
output [0:0] bottom_grid_pin_10_;
output [0:0] bottom_grid_pin_11_;
output [0:0] bottom_grid_pin_12_;
output [0:0] bottom_grid_pin_13_;
output [0:0] bottom_grid_pin_14_;
output [0:0] bottom_grid_pin_15_;
output [0:0] ccff_tail;
input [0:0] IO_ISOL_N;
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
input [0:0] bottom_width_0_height_0__pin_0_;
output [0:0] bottom_width_0_height_0__pin_1_upper;
output [0:0] bottom_width_0_height_0__pin_1_lower;
input SC_IN_TOP;
output SC_OUT_BOT;
input SC_IN_BOT;
output SC_OUT_TOP;
input prog_clk_0_S_in;
output prog_clk_0_W_out;
wire [0:3] mux_bottom_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_0_undriven_sram_inv;
wire [0:3] mux_top_ipin_10_undriven_sram_inv;
wire [0:3] mux_top_ipin_11_undriven_sram_inv;
wire [0:3] mux_top_ipin_12_undriven_sram_inv;
wire [0:3] mux_top_ipin_13_undriven_sram_inv;
wire [0:3] mux_top_ipin_14_undriven_sram_inv;
wire [0:3] mux_top_ipin_15_undriven_sram_inv;
wire [0:3] mux_top_ipin_1_undriven_sram_inv;
wire [0:3] mux_top_ipin_2_undriven_sram_inv;
wire [0:3] mux_top_ipin_3_undriven_sram_inv;
wire [0:3] mux_top_ipin_4_undriven_sram_inv;
wire [0:3] mux_top_ipin_5_undriven_sram_inv;
wire [0:3] mux_top_ipin_6_undriven_sram_inv;
wire [0:3] mux_top_ipin_7_undriven_sram_inv;
wire [0:3] mux_top_ipin_8_undriven_sram_inv;
wire [0:3] mux_top_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
wire ccff_tail_mid;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chanx_right_out[0] = chanx_left_in[0];
assign chanx_right_out[1] = chanx_left_in[1];
assign chanx_right_out[2] = chanx_left_in[2];
assign chanx_right_out[3] = chanx_left_in[3];
assign chanx_right_out[4] = chanx_left_in[4];
assign chanx_right_out[5] = chanx_left_in[5];
assign chanx_right_out[6] = chanx_left_in[6];
assign chanx_right_out[7] = chanx_left_in[7];
assign chanx_right_out[8] = chanx_left_in[8];
assign chanx_right_out[9] = chanx_left_in[9];
assign chanx_right_out[10] = chanx_left_in[10];
assign chanx_right_out[11] = chanx_left_in[11];
assign chanx_right_out[12] = chanx_left_in[12];
assign chanx_right_out[13] = chanx_left_in[13];
assign chanx_right_out[14] = chanx_left_in[14];
assign chanx_right_out[15] = chanx_left_in[15];
assign chanx_right_out[16] = chanx_left_in[16];
assign chanx_right_out[17] = chanx_left_in[17];
assign chanx_right_out[18] = chanx_left_in[18];
assign chanx_right_out[19] = chanx_left_in[19];
assign chanx_left_out[0] = chanx_right_in[0];
assign chanx_left_out[1] = chanx_right_in[1];
assign chanx_left_out[2] = chanx_right_in[2];
assign chanx_left_out[3] = chanx_right_in[3];
assign chanx_left_out[4] = chanx_right_in[4];
assign chanx_left_out[5] = chanx_right_in[5];
assign chanx_left_out[6] = chanx_right_in[6];
assign chanx_left_out[7] = chanx_right_in[7];
assign chanx_left_out[8] = chanx_right_in[8];
assign chanx_left_out[9] = chanx_right_in[9];
assign chanx_left_out[10] = chanx_right_in[10];
assign chanx_left_out[11] = chanx_right_in[11];
assign chanx_left_out[12] = chanx_right_in[12];
assign chanx_left_out[13] = chanx_right_in[13];
assign chanx_left_out[14] = chanx_right_in[14];
assign chanx_left_out[15] = chanx_right_in[15];
assign chanx_left_out[16] = chanx_right_in[16];
assign chanx_left_out[17] = chanx_right_in[17];
assign chanx_left_out[18] = chanx_right_in[18];
assign chanx_left_out[19] = chanx_right_in[19];
assign bottom_width_0_height_0__pin_1_lower[0] = bottom_width_0_height_0__pin_1_upper[0];
assign SC_OUT_BOT = SC_IN_TOP;
assign SC_OUT_TOP = SC_IN_BOT;
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size10
mux_bottom_ipin_0
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_bottom_ipin_0_undriven_sram_inv[0:3]),
.out(top_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_0
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_3
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_3_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_4
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_4_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_7
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_7_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_8
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_8_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_11
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_11_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_12
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_12_[0])
);
mux_tree_tapbuf_size10
mux_top_ipin_15
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_15_[0])
);
mux_tree_tapbuf_size10_mem
mem_bottom_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_ipin_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3])
);
mux_tree_tapbuf_size8
mux_top_ipin_1
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_1_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_2
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_2_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_5
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_5_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_6
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_6_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_9
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_9_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_10
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_10_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_13
(
.in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_13_[0])
);
mux_tree_tapbuf_size8
mux_top_ipin_14
(
.in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]),
.out(bottom_grid_pin_14_[0])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.io_outpad(bottom_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(bottom_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_S_in),
.X(prog_clk_0)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_W_FTB01
(
.A(prog_clk_0_S_in),
.X(prog_clk_0_W_out)
);
endmodule

113
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/routing/cby_0__1_.v Normal file
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@ -0,0 +1,113 @@
module cby_0__1_
( chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_0_, ccff_tail, IO_ISOL_N, gfpga_pad_EMBEDDED_IO_HD_SOC_IN, gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, right_width_0_height_0__pin_0_, right_width_0_height_0__pin_1_upper, right_width_0_height_0__pin_1_lower, prog_clk_0_E_in );
input [0:19] chany_bottom_in;
input [0:19] chany_top_in;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chany_top_out;
output [0:0] left_grid_pin_0_;
output [0:0] ccff_tail;
input [0:0] IO_ISOL_N;
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
input [0:0] right_width_0_height_0__pin_0_;
output [0:0] right_width_0_height_0__pin_1_upper;
output [0:0] right_width_0_height_0__pin_1_lower;
input prog_clk_0_E_in;
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire ccff_tail_mid;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
assign chany_top_out[2] = chany_bottom_in[2];
assign chany_top_out[3] = chany_bottom_in[3];
assign chany_top_out[4] = chany_bottom_in[4];
assign chany_top_out[5] = chany_bottom_in[5];
assign chany_top_out[6] = chany_bottom_in[6];
assign chany_top_out[7] = chany_bottom_in[7];
assign chany_top_out[8] = chany_bottom_in[8];
assign chany_top_out[9] = chany_bottom_in[9];
assign chany_top_out[10] = chany_bottom_in[10];
assign chany_top_out[11] = chany_bottom_in[11];
assign chany_top_out[12] = chany_bottom_in[12];
assign chany_top_out[13] = chany_bottom_in[13];
assign chany_top_out[14] = chany_bottom_in[14];
assign chany_top_out[15] = chany_bottom_in[15];
assign chany_top_out[16] = chany_bottom_in[16];
assign chany_top_out[17] = chany_bottom_in[17];
assign chany_top_out[18] = chany_bottom_in[18];
assign chany_top_out[19] = chany_bottom_in[19];
assign chany_bottom_out[0] = chany_top_in[0];
assign chany_bottom_out[1] = chany_top_in[1];
assign chany_bottom_out[2] = chany_top_in[2];
assign chany_bottom_out[3] = chany_top_in[3];
assign chany_bottom_out[4] = chany_top_in[4];
assign chany_bottom_out[5] = chany_top_in[5];
assign chany_bottom_out[6] = chany_top_in[6];
assign chany_bottom_out[7] = chany_top_in[7];
assign chany_bottom_out[8] = chany_top_in[8];
assign chany_bottom_out[9] = chany_top_in[9];
assign chany_bottom_out[10] = chany_top_in[10];
assign chany_bottom_out[11] = chany_top_in[11];
assign chany_bottom_out[12] = chany_top_in[12];
assign chany_bottom_out[13] = chany_top_in[13];
assign chany_bottom_out[14] = chany_top_in[14];
assign chany_bottom_out[15] = chany_top_in[15];
assign chany_bottom_out[16] = chany_top_in[16];
assign chany_bottom_out[17] = chany_top_in[17];
assign chany_bottom_out[18] = chany_top_in[18];
assign chany_bottom_out[19] = chany_top_in[19];
assign right_width_0_height_0__pin_1_lower[0] = right_width_0_height_0__pin_1_upper[0];
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size10
mux_right_ipin_0
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_pin_0_[0])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.io_outpad(right_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(right_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_E_in),
.X(prog_clk_0)
);
endmodule

583
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/routing/cby_1__1_.v Normal file
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@ -0,0 +1,583 @@
module cby_1__1_
( chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail, Test_en_S_in, Test_en_E_in, Test_en_W_in, Test_en_N_out, Test_en_W_out, Test_en_E_out, prog_clk_0_W_in, prog_clk_0_S_out, prog_clk_0_N_out, prog_clk_2_N_in, prog_clk_2_S_in, prog_clk_2_S_out, prog_clk_2_N_out, prog_clk_3_S_in, prog_clk_3_N_in, prog_clk_3_N_out, prog_clk_3_S_out, clk_2_N_in, clk_2_S_in, clk_2_S_out, clk_2_N_out, clk_3_S_in, clk_3_N_in, clk_3_N_out, clk_3_S_out );
input [0:19] chany_bottom_in;
input [0:19] chany_top_in;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chany_top_out;
output [0:0] left_grid_pin_16_;
output [0:0] left_grid_pin_17_;
output [0:0] left_grid_pin_18_;
output [0:0] left_grid_pin_19_;
output [0:0] left_grid_pin_20_;
output [0:0] left_grid_pin_21_;
output [0:0] left_grid_pin_22_;
output [0:0] left_grid_pin_23_;
output [0:0] left_grid_pin_24_;
output [0:0] left_grid_pin_25_;
output [0:0] left_grid_pin_26_;
output [0:0] left_grid_pin_27_;
output [0:0] left_grid_pin_28_;
output [0:0] left_grid_pin_29_;
output [0:0] left_grid_pin_30_;
output [0:0] left_grid_pin_31_;
output [0:0] ccff_tail;
input Test_en_S_in;
input Test_en_E_in;
input Test_en_W_in;
output Test_en_N_out;
output Test_en_W_out;
output Test_en_E_out;
input prog_clk_0_W_in;
output prog_clk_0_S_out;
output prog_clk_0_N_out;
input prog_clk_2_N_in;
input prog_clk_2_S_in;
output prog_clk_2_S_out;
output prog_clk_2_N_out;
input prog_clk_3_S_in;
input prog_clk_3_N_in;
output prog_clk_3_N_out;
output prog_clk_3_S_out;
input clk_2_N_in;
input clk_2_S_in;
output clk_2_S_out;
output clk_2_N_out;
input clk_3_S_in;
input clk_3_N_in;
output clk_3_N_out;
output clk_3_S_out;
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_10_undriven_sram_inv;
wire [0:3] mux_right_ipin_11_undriven_sram_inv;
wire [0:3] mux_right_ipin_12_undriven_sram_inv;
wire [0:3] mux_right_ipin_13_undriven_sram_inv;
wire [0:3] mux_right_ipin_14_undriven_sram_inv;
wire [0:3] mux_right_ipin_15_undriven_sram_inv;
wire [0:3] mux_right_ipin_1_undriven_sram_inv;
wire [0:3] mux_right_ipin_2_undriven_sram_inv;
wire [0:3] mux_right_ipin_3_undriven_sram_inv;
wire [0:3] mux_right_ipin_4_undriven_sram_inv;
wire [0:3] mux_right_ipin_5_undriven_sram_inv;
wire [0:3] mux_right_ipin_6_undriven_sram_inv;
wire [0:3] mux_right_ipin_7_undriven_sram_inv;
wire [0:3] mux_right_ipin_8_undriven_sram_inv;
wire [0:3] mux_right_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
assign chany_top_out[2] = chany_bottom_in[2];
assign chany_top_out[3] = chany_bottom_in[3];
assign chany_top_out[4] = chany_bottom_in[4];
assign chany_top_out[5] = chany_bottom_in[5];
assign chany_top_out[6] = chany_bottom_in[6];
assign chany_top_out[7] = chany_bottom_in[7];
assign chany_top_out[8] = chany_bottom_in[8];
assign chany_top_out[9] = chany_bottom_in[9];
assign chany_top_out[10] = chany_bottom_in[10];
assign chany_top_out[11] = chany_bottom_in[11];
assign chany_top_out[12] = chany_bottom_in[12];
assign chany_top_out[13] = chany_bottom_in[13];
assign chany_top_out[14] = chany_bottom_in[14];
assign chany_top_out[15] = chany_bottom_in[15];
assign chany_top_out[16] = chany_bottom_in[16];
assign chany_top_out[17] = chany_bottom_in[17];
assign chany_top_out[18] = chany_bottom_in[18];
assign chany_top_out[19] = chany_bottom_in[19];
assign chany_bottom_out[0] = chany_top_in[0];
assign chany_bottom_out[1] = chany_top_in[1];
assign chany_bottom_out[2] = chany_top_in[2];
assign chany_bottom_out[3] = chany_top_in[3];
assign chany_bottom_out[4] = chany_top_in[4];
assign chany_bottom_out[5] = chany_top_in[5];
assign chany_bottom_out[6] = chany_top_in[6];
assign chany_bottom_out[7] = chany_top_in[7];
assign chany_bottom_out[8] = chany_top_in[8];
assign chany_bottom_out[9] = chany_top_in[9];
assign chany_bottom_out[10] = chany_top_in[10];
assign chany_bottom_out[11] = chany_top_in[11];
assign chany_bottom_out[12] = chany_top_in[12];
assign chany_bottom_out[13] = chany_top_in[13];
assign chany_bottom_out[14] = chany_top_in[14];
assign chany_bottom_out[15] = chany_top_in[15];
assign chany_bottom_out[16] = chany_top_in[16];
assign chany_bottom_out[17] = chany_top_in[17];
assign chany_bottom_out[18] = chany_top_in[18];
assign chany_bottom_out[19] = chany_top_in[19];
assign Test_en_S_in = Test_en_E_in;
assign Test_en_E_in = Test_en_W_in;
assign prog_clk_0 = prog_clk;
assign prog_clk_2_N_in = prog_clk_2_S_in;
assign prog_clk_3_S_in = prog_clk_3_N_in;
assign clk_2_N_in = clk_2_S_in;
assign clk_3_S_in = clk_3_N_in;
mux_tree_tapbuf_size10
mux_right_ipin_0
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_pin_16_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_3
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]),
.out(left_grid_pin_19_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_4
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]),
.out(left_grid_pin_20_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_7
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]),
.out(left_grid_pin_23_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_8
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]),
.out(left_grid_pin_24_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_11
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]),
.out(left_grid_pin_27_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_12
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]),
.out(left_grid_pin_28_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_15
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]),
.out(left_grid_pin_31_[0])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size8
mux_right_ipin_1
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]),
.out(left_grid_pin_17_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_2
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]),
.out(left_grid_pin_18_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_5
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]),
.out(left_grid_pin_21_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_6
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]),
.out(left_grid_pin_22_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_9
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]),
.out(left_grid_pin_25_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_10
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]),
.out(left_grid_pin_26_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_13
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]),
.out(left_grid_pin_29_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_14
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]),
.out(left_grid_pin_30_[0])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);
sky130_fd_sc_hd__buf_4
Test_en_N_FTB01
(
.A(Test_en_S_in),
.X(Test_en_N_out)
);
sky130_fd_sc_hd__buf_4
Test_en_W_FTB01
(
.A(Test_en_S_in),
.X(Test_en_W_out)
);
sky130_fd_sc_hd__buf_4
Test_en_E_FTB01
(
.A(Test_en_S_in),
.X(Test_en_E_out)
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_W_in),
.X(prog_clk_0)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_S_FTB01
(
.A(prog_clk_0_W_in),
.X(prog_clk_0_S_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_N_FTB01
(
.A(prog_clk_0_W_in),
.X(prog_clk_0_N_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_2_S_FTB01
(
.A(prog_clk_2_N_in),
.X(prog_clk_2_S_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_2_N_FTB01
(
.A(prog_clk_2_N_in),
.X(prog_clk_2_N_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_3_N_FTB01
(
.A(prog_clk_3_S_in),
.X(prog_clk_3_N_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_3_S_FTB01
(
.A(prog_clk_3_S_in),
.X(prog_clk_3_S_out)
);
sky130_fd_sc_hd__buf_4
clk_2_S_FTB01
(
.A(clk_2_N_in),
.X(clk_2_S_out)
);
sky130_fd_sc_hd__buf_4
clk_2_N_FTB01
(
.A(clk_2_N_in),
.X(clk_2_N_out)
);
sky130_fd_sc_hd__buf_4
clk_3_N_FTB01
(
.A(clk_3_S_in),
.X(clk_3_N_out)
);
sky130_fd_sc_hd__buf_4
clk_3_S_FTB01
(
.A(clk_3_S_in),
.X(clk_3_S_out)
);
endmodule

515
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/routing/cby_2__1_.v Normal file
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@ -0,0 +1,515 @@
module cby_2__1_
( chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, right_grid_pin_0_, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail, IO_ISOL_N, gfpga_pad_EMBEDDED_IO_HD_SOC_IN, gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, left_width_0_height_0__pin_0_, left_width_0_height_0__pin_1_upper, left_width_0_height_0__pin_1_lower, prog_clk_0_W_in, prog_clk_0_S_out, prog_clk_0_N_out );
input [0:19] chany_bottom_in;
input [0:19] chany_top_in;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chany_top_out;
output [0:0] right_grid_pin_0_;
output [0:0] left_grid_pin_16_;
output [0:0] left_grid_pin_17_;
output [0:0] left_grid_pin_18_;
output [0:0] left_grid_pin_19_;
output [0:0] left_grid_pin_20_;
output [0:0] left_grid_pin_21_;
output [0:0] left_grid_pin_22_;
output [0:0] left_grid_pin_23_;
output [0:0] left_grid_pin_24_;
output [0:0] left_grid_pin_25_;
output [0:0] left_grid_pin_26_;
output [0:0] left_grid_pin_27_;
output [0:0] left_grid_pin_28_;
output [0:0] left_grid_pin_29_;
output [0:0] left_grid_pin_30_;
output [0:0] left_grid_pin_31_;
output [0:0] ccff_tail;
input [0:0] IO_ISOL_N;
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
input [0:0] left_width_0_height_0__pin_0_;
output [0:0] left_width_0_height_0__pin_1_upper;
output [0:0] left_width_0_height_0__pin_1_lower;
input prog_clk_0_W_in;
output prog_clk_0_S_out;
output prog_clk_0_N_out;
wire [0:3] mux_left_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_0_undriven_sram_inv;
wire [0:3] mux_right_ipin_10_undriven_sram_inv;
wire [0:3] mux_right_ipin_11_undriven_sram_inv;
wire [0:3] mux_right_ipin_12_undriven_sram_inv;
wire [0:3] mux_right_ipin_13_undriven_sram_inv;
wire [0:3] mux_right_ipin_14_undriven_sram_inv;
wire [0:3] mux_right_ipin_15_undriven_sram_inv;
wire [0:3] mux_right_ipin_1_undriven_sram_inv;
wire [0:3] mux_right_ipin_2_undriven_sram_inv;
wire [0:3] mux_right_ipin_3_undriven_sram_inv;
wire [0:3] mux_right_ipin_4_undriven_sram_inv;
wire [0:3] mux_right_ipin_5_undriven_sram_inv;
wire [0:3] mux_right_ipin_6_undriven_sram_inv;
wire [0:3] mux_right_ipin_7_undriven_sram_inv;
wire [0:3] mux_right_ipin_8_undriven_sram_inv;
wire [0:3] mux_right_ipin_9_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:3] mux_tree_tapbuf_size8_4_sram;
wire [0:3] mux_tree_tapbuf_size8_5_sram;
wire [0:3] mux_tree_tapbuf_size8_6_sram;
wire [0:3] mux_tree_tapbuf_size8_7_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail;
wire ccff_tail_mid;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_top_out[0] = chany_bottom_in[0];
assign chany_top_out[1] = chany_bottom_in[1];
assign chany_top_out[2] = chany_bottom_in[2];
assign chany_top_out[3] = chany_bottom_in[3];
assign chany_top_out[4] = chany_bottom_in[4];
assign chany_top_out[5] = chany_bottom_in[5];
assign chany_top_out[6] = chany_bottom_in[6];
assign chany_top_out[7] = chany_bottom_in[7];
assign chany_top_out[8] = chany_bottom_in[8];
assign chany_top_out[9] = chany_bottom_in[9];
assign chany_top_out[10] = chany_bottom_in[10];
assign chany_top_out[11] = chany_bottom_in[11];
assign chany_top_out[12] = chany_bottom_in[12];
assign chany_top_out[13] = chany_bottom_in[13];
assign chany_top_out[14] = chany_bottom_in[14];
assign chany_top_out[15] = chany_bottom_in[15];
assign chany_top_out[16] = chany_bottom_in[16];
assign chany_top_out[17] = chany_bottom_in[17];
assign chany_top_out[18] = chany_bottom_in[18];
assign chany_top_out[19] = chany_bottom_in[19];
assign chany_bottom_out[0] = chany_top_in[0];
assign chany_bottom_out[1] = chany_top_in[1];
assign chany_bottom_out[2] = chany_top_in[2];
assign chany_bottom_out[3] = chany_top_in[3];
assign chany_bottom_out[4] = chany_top_in[4];
assign chany_bottom_out[5] = chany_top_in[5];
assign chany_bottom_out[6] = chany_top_in[6];
assign chany_bottom_out[7] = chany_top_in[7];
assign chany_bottom_out[8] = chany_top_in[8];
assign chany_bottom_out[9] = chany_top_in[9];
assign chany_bottom_out[10] = chany_top_in[10];
assign chany_bottom_out[11] = chany_top_in[11];
assign chany_bottom_out[12] = chany_top_in[12];
assign chany_bottom_out[13] = chany_top_in[13];
assign chany_bottom_out[14] = chany_top_in[14];
assign chany_bottom_out[15] = chany_top_in[15];
assign chany_bottom_out[16] = chany_top_in[16];
assign chany_bottom_out[17] = chany_top_in[17];
assign chany_bottom_out[18] = chany_top_in[18];
assign chany_bottom_out[19] = chany_top_in[19];
assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0];
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size10
mux_left_ipin_0
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_left_ipin_0_undriven_sram_inv[0:3]),
.out(right_grid_pin_0_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_0
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]),
.out(left_grid_pin_16_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_3
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]),
.out(left_grid_pin_19_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_4
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]),
.out(left_grid_pin_20_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_7
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]),
.out(left_grid_pin_23_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_8
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]),
.out(left_grid_pin_24_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_11
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]),
.out(left_grid_pin_27_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_12
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[17], chany_top_in[17] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]),
.out(left_grid_pin_28_[0])
);
mux_tree_tapbuf_size10
mux_right_ipin_15
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]),
.out(left_grid_pin_31_[0])
);
mux_tree_tapbuf_size10_mem
mem_left_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_ipin_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3])
);
mux_tree_tapbuf_size8
mux_right_ipin_1
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]),
.out(left_grid_pin_17_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_2
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]),
.out(left_grid_pin_18_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_5
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]),
.out(left_grid_pin_21_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_6
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]),
.out(left_grid_pin_22_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_9
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }),
.sram(mux_tree_tapbuf_size8_4_sram[0:3]),
.sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]),
.out(left_grid_pin_25_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_10
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }),
.sram(mux_tree_tapbuf_size8_5_sram[0:3]),
.sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]),
.out(left_grid_pin_26_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_13
(
.in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }),
.sram(mux_tree_tapbuf_size8_6_sram[0:3]),
.sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]),
.out(left_grid_pin_29_[0])
);
mux_tree_tapbuf_size8
mux_right_ipin_14
(
.in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }),
.sram(mux_tree_tapbuf_size8_7_sram[0:3]),
.sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]),
.out(left_grid_pin_30_[0])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_ipin_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3])
);
logical_tile_io_mode_io_
logical_tile_io_mode_io__0
(
.IO_ISOL_N(IO_ISOL_N[0]),
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]),
.io_outpad(left_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_tail_mid),
.io_inpad(left_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_W_in),
.X(prog_clk_0)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_S_FTB01
(
.A(prog_clk_0_W_in),
.X(prog_clk_0_S_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_0_N_FTB01
(
.A(prog_clk_0_W_in),
.X(prog_clk_0_N_out)
);
endmodule

603
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/routing/sb_0__0_.v Normal file
View File

@ -0,0 +1,603 @@
module sb_0__0_
( chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, right_bottom_grid_pin_13_, right_bottom_grid_pin_15_, right_bottom_grid_pin_17_, ccff_head, chany_top_out, chanx_right_out, ccff_tail, prog_clk_0_E_in );
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_1_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_1_;
input [0:0] right_bottom_grid_pin_3_;
input [0:0] right_bottom_grid_pin_5_;
input [0:0] right_bottom_grid_pin_7_;
input [0:0] right_bottom_grid_pin_9_;
input [0:0] right_bottom_grid_pin_11_;
input [0:0] right_bottom_grid_pin_13_;
input [0:0] right_bottom_grid_pin_15_;
input [0:0] right_bottom_grid_pin_17_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:0] ccff_tail;
input prog_clk_0_E_in;
wire [0:2] mux_right_track_0_undriven_sram_inv;
wire [0:1] mux_right_track_10_undriven_sram_inv;
wire [0:1] mux_right_track_12_undriven_sram_inv;
wire [0:1] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_20_undriven_sram_inv;
wire [0:1] mux_right_track_22_undriven_sram_inv;
wire [0:1] mux_right_track_24_undriven_sram_inv;
wire [0:1] mux_right_track_26_undriven_sram_inv;
wire [0:1] mux_right_track_28_undriven_sram_inv;
wire [0:2] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_30_undriven_sram_inv;
wire [0:1] mux_right_track_32_undriven_sram_inv;
wire [0:1] mux_right_track_34_undriven_sram_inv;
wire [0:1] mux_right_track_36_undriven_sram_inv;
wire [0:1] mux_right_track_38_undriven_sram_inv;
wire [0:2] mux_right_track_4_undriven_sram_inv;
wire [0:2] mux_right_track_6_undriven_sram_inv;
wire [0:1] mux_right_track_8_undriven_sram_inv;
wire [0:1] mux_top_track_0_undriven_sram_inv;
wire [0:1] mux_top_track_24_undriven_sram_inv;
wire [0:1] mux_top_track_4_undriven_sram_inv;
wire [0:1] mux_top_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_top_out[19] = chanx_right_in[0];
assign chany_top_out[1] = chanx_right_in[2];
assign chany_top_out[3] = chanx_right_in[4];
assign chany_top_out[5] = chanx_right_in[6];
assign chany_top_out[6] = chanx_right_in[7];
assign chany_top_out[7] = chanx_right_in[8];
assign chany_top_out[8] = chanx_right_in[9];
assign chany_top_out[9] = chanx_right_in[10];
assign chany_top_out[10] = chanx_right_in[11];
assign chany_top_out[11] = chanx_right_in[12];
assign chany_top_out[13] = chanx_right_in[14];
assign chany_top_out[14] = chanx_right_in[15];
assign chany_top_out[15] = chanx_right_in[16];
assign chany_top_out[16] = chanx_right_in[17];
assign chany_top_out[17] = chanx_right_in[18];
assign chany_top_out[18] = chanx_right_in[19];
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size2
mux_top_track_0
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[1] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:1]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size2
mux_top_track_4
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[3] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:1]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size2
mux_top_track_8
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[5] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:1]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size2
mux_top_track_24
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:1]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size2
mux_right_track_10
(
.in({ chany_top_in[4], right_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:1]),
.out(chanx_right_out[5])
);
mux_tree_tapbuf_size2
mux_right_track_12
(
.in({ chany_top_in[5], right_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:1]),
.out(chanx_right_out[6])
);
mux_tree_tapbuf_size2
mux_right_track_14
(
.in({ chany_top_in[6], right_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:1]),
.out(chanx_right_out[7])
);
mux_tree_tapbuf_size2
mux_right_track_16
(
.in({ chany_top_in[7], right_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size2
mux_right_track_18
(
.in({ chany_top_in[8], right_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9])
);
mux_tree_tapbuf_size2
mux_right_track_20
(
.in({ chany_top_in[9], right_bottom_grid_pin_13_[0] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_right_track_20_undriven_sram_inv[0:1]),
.out(chanx_right_out[10])
);
mux_tree_tapbuf_size2
mux_right_track_22
(
.in({ chany_top_in[10], right_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_right_track_22_undriven_sram_inv[0:1]),
.out(chanx_right_out[11])
);
mux_tree_tapbuf_size2
mux_right_track_26
(
.in({ chany_top_in[12], right_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_right_track_26_undriven_sram_inv[0:1]),
.out(chanx_right_out[13])
);
mux_tree_tapbuf_size2
mux_right_track_28
(
.in({ chany_top_in[13], right_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
.out(chanx_right_out[14])
);
mux_tree_tapbuf_size2
mux_right_track_30
(
.in({ chany_top_in[14], right_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
.out(chanx_right_out[15])
);
mux_tree_tapbuf_size2
mux_right_track_32
(
.in({ chany_top_in[15], right_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size2
mux_right_track_34
(
.in({ chany_top_in[16], right_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
.out(chanx_right_out[17])
);
mux_tree_tapbuf_size2
mux_right_track_36
(
.in({ chany_top_in[17], right_bottom_grid_pin_13_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_right_track_36_undriven_sram_inv[0:1]),
.out(chanx_right_out[18])
);
mux_tree_tapbuf_size2
mux_right_track_38
(
.in({ chany_top_in[18], right_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_right_track_38_undriven_sram_inv[0:1]),
.out(chanx_right_out[19])
);
mux_tree_tapbuf_size2_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_26
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_28
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_30
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_34
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_36
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_38
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1])
);
mux_tree_tapbuf_size6
mux_right_track_0
(
.in({ chany_top_in[19], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_13_[0], right_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:2]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size6
mux_right_track_4
(
.in({ chany_top_in[1], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_13_[0], right_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:2]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size6_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size5
mux_right_track_2
(
.in({ chany_top_in[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0], right_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:2]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size5
mux_right_track_6
(
.in({ chany_top_in[2], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0], right_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:2]),
.out(chanx_right_out[3])
);
mux_tree_tapbuf_size5_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_right_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
mux_tree_tapbuf_size3
mux_right_track_8
(
.in({ chany_top_in[3], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:1]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size3
mux_right_track_24
(
.in({ chany_top_in[11], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:1]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size3_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_E_in),
.X(prog_clk_0)
);
endmodule

823
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/routing/sb_0__1_.v Normal file
View File

@ -0,0 +1,823 @@
module sb_0__1_
( chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chany_top_out, chanx_right_out, chany_bottom_out, ccff_tail, prog_clk_0_E_in );
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_1_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_1_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:0] ccff_tail;
input prog_clk_0_E_in;
wire [0:2] mux_bottom_track_17_undriven_sram_inv;
wire [0:2] mux_bottom_track_1_undriven_sram_inv;
wire [0:2] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_33_undriven_sram_inv;
wire [0:2] mux_bottom_track_3_undriven_sram_inv;
wire [0:2] mux_bottom_track_5_undriven_sram_inv;
wire [0:2] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_right_track_0_undriven_sram_inv;
wire [0:2] mux_right_track_10_undriven_sram_inv;
wire [0:2] mux_right_track_12_undriven_sram_inv;
wire [0:2] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_20_undriven_sram_inv;
wire [0:1] mux_right_track_22_undriven_sram_inv;
wire [0:2] mux_right_track_24_undriven_sram_inv;
wire [0:1] mux_right_track_26_undriven_sram_inv;
wire [0:1] mux_right_track_28_undriven_sram_inv;
wire [0:2] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_30_undriven_sram_inv;
wire [0:1] mux_right_track_32_undriven_sram_inv;
wire [0:1] mux_right_track_34_undriven_sram_inv;
wire [0:1] mux_right_track_36_undriven_sram_inv;
wire [0:2] mux_right_track_4_undriven_sram_inv;
wire [0:2] mux_right_track_6_undriven_sram_inv;
wire [0:2] mux_right_track_8_undriven_sram_inv;
wire [0:2] mux_top_track_0_undriven_sram_inv;
wire [0:2] mux_top_track_16_undriven_sram_inv;
wire [0:2] mux_top_track_24_undriven_sram_inv;
wire [0:2] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_32_undriven_sram_inv;
wire [0:2] mux_top_track_4_undriven_sram_inv;
wire [0:2] mux_top_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_4_sram;
wire [0:2] mux_tree_tapbuf_size4_5_sram;
wire [0:2] mux_tree_tapbuf_size4_6_sram;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_2_sram;
wire [0:2] mux_tree_tapbuf_size5_3_sram;
wire [0:2] mux_tree_tapbuf_size5_4_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:2] mux_tree_tapbuf_size6_4_sram;
wire [0:2] mux_tree_tapbuf_size6_5_sram;
wire [0:2] mux_tree_tapbuf_size6_6_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_bottom_out[3] = chany_top_in[2];
assign chany_bottom_out[5] = chany_top_in[4];
assign chany_bottom_out[6] = chany_top_in[5];
assign chany_bottom_out[7] = chany_top_in[6];
assign chany_bottom_out[9] = chany_top_in[8];
assign chany_bottom_out[10] = chany_top_in[9];
assign chany_bottom_out[11] = chany_top_in[10];
assign chany_bottom_out[13] = chany_top_in[12];
assign chany_bottom_out[14] = chany_top_in[13];
assign chany_bottom_out[15] = chany_top_in[14];
assign chany_bottom_out[17] = chany_top_in[16];
assign chany_bottom_out[18] = chany_top_in[17];
assign chany_bottom_out[19] = chany_top_in[18];
assign chanx_right_out[19] = right_bottom_grid_pin_41_[0];
assign chany_top_out[3] = chany_bottom_in[2];
assign chany_top_out[5] = chany_bottom_in[4];
assign chany_top_out[6] = chany_bottom_in[5];
assign chany_top_out[7] = chany_bottom_in[6];
assign chany_top_out[9] = chany_bottom_in[8];
assign chany_top_out[10] = chany_bottom_in[9];
assign chany_top_out[11] = chany_bottom_in[10];
assign chany_top_out[13] = chany_bottom_in[12];
assign chany_top_out[14] = chany_bottom_in[13];
assign chany_top_out[15] = chany_bottom_in[14];
assign chany_top_out[17] = chany_bottom_in[16];
assign chany_top_out[18] = chany_bottom_in[17];
assign chany_top_out[19] = chany_bottom_in[18];
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size6
mux_top_track_0
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15], chany_bottom_in[2], chany_bottom_in[12] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:2]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size6
mux_top_track_4
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], chany_bottom_in[5], chany_bottom_in[14] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:2]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size6
mux_top_track_8
(
.in({ top_left_grid_pin_1_[0], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18], chany_bottom_in[6], chany_bottom_in[16] }),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:2]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size6
mux_right_track_0
(
.in({ chany_top_in[2], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2] }),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:2]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size6
mux_bottom_track_1
(
.in({ chany_top_in[2], chany_top_in[12], chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size6_4_sram[0:2]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size6
mux_bottom_track_5
(
.in({ chany_top_in[5], chany_top_in[14], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size6_5_sram[0:2]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size6
mux_bottom_track_9
(
.in({ chany_top_in[6], chany_top_in[16], chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size6_6_sram[0:2]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:2]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size6_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2])
);
mux_tree_tapbuf_size5
mux_top_track_2
(
.in({ chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], chany_bottom_in[4], chany_bottom_in[13] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:2]),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size5
mux_top_track_16
(
.in({ chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], chany_bottom_in[8], chany_bottom_in[17] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:2]),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size5
mux_bottom_track_3
(
.in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18] }),
.sram(mux_tree_tapbuf_size5_2_sram[0:2]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size5
mux_bottom_track_17
(
.in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15] }),
.sram(mux_tree_tapbuf_size5_3_sram[0:2]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:2]),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size5
mux_bottom_track_25
(
.in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[7], chanx_right_in[14] }),
.sram(mux_tree_tapbuf_size5_4_sram[0:2]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size5_mem
mem_top_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_top_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_2_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_3_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_4_sram[0:2])
);
mux_tree_tapbuf_size4
mux_top_track_24
(
.in({ chanx_right_in[6], chanx_right_in[13], chany_bottom_in[9], chany_bottom_in[18] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:2]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size4
mux_top_track_32
(
.in({ chanx_right_in[0], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[10] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_top_track_32_undriven_sram_inv[0:2]),
.out(chany_top_out[16])
);
mux_tree_tapbuf_size4
mux_right_track_8
(
.in({ chany_top_in[7:8], right_bottom_grid_pin_34_[0], chany_bottom_in[8] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:2]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size4
mux_right_track_10
(
.in({ chany_top_in[9], chany_top_in[11], right_bottom_grid_pin_35_[0], chany_bottom_in[9] }),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:2]),
.out(chanx_right_out[5])
);
mux_tree_tapbuf_size4
mux_right_track_12
(
.in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_36_[0], chany_bottom_in[10] }),
.sram(mux_tree_tapbuf_size4_4_sram[0:2]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:2]),
.out(chanx_right_out[6])
);
mux_tree_tapbuf_size4
mux_right_track_14
(
.in({ chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_37_[0], chany_bottom_in[12] }),
.sram(mux_tree_tapbuf_size4_5_sram[0:2]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:2]),
.out(chanx_right_out[7])
);
mux_tree_tapbuf_size4
mux_right_track_24
(
.in({ chany_top_in[18], right_bottom_grid_pin_34_[0], chany_bottom_in[18:19] }),
.sram(mux_tree_tapbuf_size4_6_sram[0:2]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:2]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size4_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_top_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_5_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_6_sram[0:2])
);
mux_tree_tapbuf_size7
mux_right_track_2
(
.in({ chany_top_in[0], chany_top_in[4], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:2]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size7
mux_right_track_4
(
.in({ chany_top_in[1], chany_top_in[5], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[5] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:2]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size7
mux_right_track_6
(
.in({ chany_top_in[3], chany_top_in[6], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:2]),
.out(chanx_right_out[3])
);
mux_tree_tapbuf_size7_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
mux_tree_tapbuf_size3
mux_right_track_16
(
.in({ chany_top_in[13], right_bottom_grid_pin_38_[0], chany_bottom_in[13] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size3
mux_right_track_18
(
.in({ chany_top_in[14], right_bottom_grid_pin_39_[0], chany_bottom_in[14] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9])
);
mux_tree_tapbuf_size3
mux_right_track_20
(
.in({ chany_top_in[16], right_bottom_grid_pin_40_[0], chany_bottom_in[16] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_right_track_20_undriven_sram_inv[0:1]),
.out(chanx_right_out[10])
);
mux_tree_tapbuf_size3
mux_right_track_22
(
.in({ chany_top_in[17], right_bottom_grid_pin_41_[0], chany_bottom_in[17] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_right_track_22_undriven_sram_inv[0:1]),
.out(chanx_right_out[11])
);
mux_tree_tapbuf_size3
mux_bottom_track_33
(
.in({ chany_top_in[10], chanx_right_in[6], chanx_right_in[13] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_bottom_track_33_undriven_sram_inv[0:1]),
.out(chany_bottom_out[16])
);
mux_tree_tapbuf_size3_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
mux_tree_tapbuf_size2
mux_right_track_26
(
.in({ right_bottom_grid_pin_35_[0], chany_bottom_in[15] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_right_track_26_undriven_sram_inv[0:1]),
.out(chanx_right_out[13])
);
mux_tree_tapbuf_size2
mux_right_track_28
(
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
.out(chanx_right_out[14])
);
mux_tree_tapbuf_size2
mux_right_track_30
(
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[7] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
.out(chanx_right_out[15])
);
mux_tree_tapbuf_size2
mux_right_track_32
(
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[3] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size2
mux_right_track_34
(
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[1] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
.out(chanx_right_out[17])
);
mux_tree_tapbuf_size2
mux_right_track_36
(
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[0] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_right_track_36_undriven_sram_inv[0:1]),
.out(chanx_right_out[18])
);
mux_tree_tapbuf_size2_mem
mem_right_track_26
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_28
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_30
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_34
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_36
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_E_in),
.X(prog_clk_0)
);
endmodule

606
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/routing/sb_0__2_.v Normal file
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@ -0,0 +1,606 @@
module sb_0__2_
( chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chanx_right_out, chany_bottom_out, ccff_tail, SC_IN_TOP, SC_OUT_BOT, prog_clk_0_E_in );
input [0:19] chanx_right_in;
input [0:0] right_top_grid_pin_1_;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_1_;
input [0:0] ccff_head;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:0] ccff_tail;
input SC_IN_TOP;
output SC_OUT_BOT;
input prog_clk_0_E_in;
wire [0:1] mux_bottom_track_1_undriven_sram_inv;
wire [0:1] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_5_undriven_sram_inv;
wire [0:1] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_right_track_0_undriven_sram_inv;
wire [0:1] mux_right_track_10_undriven_sram_inv;
wire [0:1] mux_right_track_12_undriven_sram_inv;
wire [0:1] mux_right_track_14_undriven_sram_inv;
wire [0:1] mux_right_track_16_undriven_sram_inv;
wire [0:1] mux_right_track_18_undriven_sram_inv;
wire [0:1] mux_right_track_20_undriven_sram_inv;
wire [0:1] mux_right_track_22_undriven_sram_inv;
wire [0:1] mux_right_track_24_undriven_sram_inv;
wire [0:1] mux_right_track_26_undriven_sram_inv;
wire [0:1] mux_right_track_28_undriven_sram_inv;
wire [0:2] mux_right_track_2_undriven_sram_inv;
wire [0:1] mux_right_track_30_undriven_sram_inv;
wire [0:1] mux_right_track_32_undriven_sram_inv;
wire [0:1] mux_right_track_34_undriven_sram_inv;
wire [0:1] mux_right_track_36_undriven_sram_inv;
wire [0:1] mux_right_track_38_undriven_sram_inv;
wire [0:2] mux_right_track_4_undriven_sram_inv;
wire [0:2] mux_right_track_6_undriven_sram_inv;
wire [0:1] mux_right_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_bottom_out[18] = chanx_right_in[0];
assign chany_bottom_out[17] = chanx_right_in[1];
assign chany_bottom_out[16] = chanx_right_in[2];
assign chany_bottom_out[15] = chanx_right_in[3];
assign chany_bottom_out[14] = chanx_right_in[4];
assign chany_bottom_out[13] = chanx_right_in[5];
assign chany_bottom_out[11] = chanx_right_in[7];
assign chany_bottom_out[10] = chanx_right_in[8];
assign chany_bottom_out[9] = chanx_right_in[9];
assign chany_bottom_out[8] = chanx_right_in[10];
assign chany_bottom_out[7] = chanx_right_in[11];
assign chany_bottom_out[6] = chanx_right_in[12];
assign chany_bottom_out[5] = chanx_right_in[13];
assign chany_bottom_out[3] = chanx_right_in[15];
assign chany_bottom_out[1] = chanx_right_in[17];
assign chany_bottom_out[19] = chanx_right_in[19];
assign SC_OUT_BOT = SC_IN_TOP;
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size6
mux_right_track_0
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[18] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:2]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size6
mux_right_track_4
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[16] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:2]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size6_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size5
mux_right_track_2
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[17] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:2]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size5
mux_right_track_6
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[15] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_right_track_6_undriven_sram_inv[0:2]),
.out(chanx_right_out[3])
);
mux_tree_tapbuf_size5_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_right_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
mux_tree_tapbuf_size3
mux_right_track_8
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[14] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:1]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size3
mux_right_track_24
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:1]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size3_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size2
mux_right_track_10
(
.in({ right_bottom_grid_pin_34_[0], chany_bottom_in[13] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_right_track_10_undriven_sram_inv[0:1]),
.out(chanx_right_out[5])
);
mux_tree_tapbuf_size2
mux_right_track_12
(
.in({ right_bottom_grid_pin_35_[0], chany_bottom_in[12] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_right_track_12_undriven_sram_inv[0:1]),
.out(chanx_right_out[6])
);
mux_tree_tapbuf_size2
mux_right_track_14
(
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_right_track_14_undriven_sram_inv[0:1]),
.out(chanx_right_out[7])
);
mux_tree_tapbuf_size2
mux_right_track_16
(
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[10] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:1]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size2
mux_right_track_18
(
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[9] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_right_track_18_undriven_sram_inv[0:1]),
.out(chanx_right_out[9])
);
mux_tree_tapbuf_size2
mux_right_track_20
(
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[8] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_right_track_20_undriven_sram_inv[0:1]),
.out(chanx_right_out[10])
);
mux_tree_tapbuf_size2
mux_right_track_22
(
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[7] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_right_track_22_undriven_sram_inv[0:1]),
.out(chanx_right_out[11])
);
mux_tree_tapbuf_size2
mux_right_track_26
(
.in({ right_bottom_grid_pin_34_[0], chany_bottom_in[5] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_right_track_26_undriven_sram_inv[0:1]),
.out(chanx_right_out[13])
);
mux_tree_tapbuf_size2
mux_right_track_28
(
.in({ right_bottom_grid_pin_35_[0], chany_bottom_in[4] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_right_track_28_undriven_sram_inv[0:1]),
.out(chanx_right_out[14])
);
mux_tree_tapbuf_size2
mux_right_track_30
(
.in({ right_bottom_grid_pin_36_[0], chany_bottom_in[3] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_right_track_30_undriven_sram_inv[0:1]),
.out(chanx_right_out[15])
);
mux_tree_tapbuf_size2
mux_right_track_32
(
.in({ right_bottom_grid_pin_37_[0], chany_bottom_in[2] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:1]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size2
mux_right_track_34
(
.in({ right_bottom_grid_pin_38_[0], chany_bottom_in[1] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_right_track_34_undriven_sram_inv[0:1]),
.out(chanx_right_out[17])
);
mux_tree_tapbuf_size2
mux_right_track_36
(
.in({ right_bottom_grid_pin_39_[0], chany_bottom_in[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_right_track_36_undriven_sram_inv[0:1]),
.out(chanx_right_out[18])
);
mux_tree_tapbuf_size2
mux_right_track_38
(
.in({ right_bottom_grid_pin_40_[0], chany_bottom_in[19] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_right_track_38_undriven_sram_inv[0:1]),
.out(chanx_right_out[19])
);
mux_tree_tapbuf_size2
mux_bottom_track_1
(
.in({ chanx_right_in[18], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:1]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size2
mux_bottom_track_5
(
.in({ chanx_right_in[16], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:1]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size2
mux_bottom_track_9
(
.in({ chanx_right_in[14], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size2
mux_bottom_track_25
(
.in({ chanx_right_in[6], bottom_left_grid_pin_1_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:1]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size2_mem
mem_right_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_26
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_28
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_30
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_34
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_36
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_right_track_38
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_E_in),
.X(prog_clk_0)
);
endmodule

762
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/routing/sb_1__0_.v Normal file
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@ -0,0 +1,762 @@
module sb_1__0_
( chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, right_bottom_grid_pin_13_, right_bottom_grid_pin_15_, right_bottom_grid_pin_17_, chanx_left_in, left_bottom_grid_pin_1_, left_bottom_grid_pin_3_, left_bottom_grid_pin_5_, left_bottom_grid_pin_7_, left_bottom_grid_pin_9_, left_bottom_grid_pin_11_, left_bottom_grid_pin_13_, left_bottom_grid_pin_15_, left_bottom_grid_pin_17_, ccff_head, chany_top_out, chanx_right_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_OUT_TOP, Test_en_S_in, Test_en_N_out, prog_clk_0_N_in, prog_clk_3_S_in, prog_clk_3_N_out, clk_3_S_in, clk_3_N_out );
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_1_;
input [0:0] right_bottom_grid_pin_3_;
input [0:0] right_bottom_grid_pin_5_;
input [0:0] right_bottom_grid_pin_7_;
input [0:0] right_bottom_grid_pin_9_;
input [0:0] right_bottom_grid_pin_11_;
input [0:0] right_bottom_grid_pin_13_;
input [0:0] right_bottom_grid_pin_15_;
input [0:0] right_bottom_grid_pin_17_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_1_;
input [0:0] left_bottom_grid_pin_3_;
input [0:0] left_bottom_grid_pin_5_;
input [0:0] left_bottom_grid_pin_7_;
input [0:0] left_bottom_grid_pin_9_;
input [0:0] left_bottom_grid_pin_11_;
input [0:0] left_bottom_grid_pin_13_;
input [0:0] left_bottom_grid_pin_15_;
input [0:0] left_bottom_grid_pin_17_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input SC_IN_TOP;
output SC_OUT_TOP;
input Test_en_S_in;
output Test_en_N_out;
input prog_clk_0_N_in;
input prog_clk_3_S_in;
output prog_clk_3_N_out;
input clk_3_S_in;
output clk_3_N_out;
wire [0:2] mux_left_track_17_undriven_sram_inv;
wire [0:3] mux_left_track_1_undriven_sram_inv;
wire [0:2] mux_left_track_25_undriven_sram_inv;
wire [0:2] mux_left_track_33_undriven_sram_inv;
wire [0:3] mux_left_track_3_undriven_sram_inv;
wire [0:3] mux_left_track_5_undriven_sram_inv;
wire [0:3] mux_left_track_9_undriven_sram_inv;
wire [0:3] mux_right_track_0_undriven_sram_inv;
wire [0:2] mux_right_track_16_undriven_sram_inv;
wire [0:2] mux_right_track_24_undriven_sram_inv;
wire [0:3] mux_right_track_2_undriven_sram_inv;
wire [0:2] mux_right_track_32_undriven_sram_inv;
wire [0:3] mux_right_track_4_undriven_sram_inv;
wire [0:3] mux_right_track_8_undriven_sram_inv;
wire [0:3] mux_top_track_0_undriven_sram_inv;
wire [0:2] mux_top_track_10_undriven_sram_inv;
wire [0:1] mux_top_track_12_undriven_sram_inv;
wire [0:1] mux_top_track_14_undriven_sram_inv;
wire [0:1] mux_top_track_16_undriven_sram_inv;
wire [0:1] mux_top_track_18_undriven_sram_inv;
wire [0:1] mux_top_track_20_undriven_sram_inv;
wire [0:1] mux_top_track_22_undriven_sram_inv;
wire [0:1] mux_top_track_24_undriven_sram_inv;
wire [0:2] mux_top_track_2_undriven_sram_inv;
wire [0:1] mux_top_track_38_undriven_sram_inv;
wire [0:2] mux_top_track_4_undriven_sram_inv;
wire [0:2] mux_top_track_6_undriven_sram_inv;
wire [0:2] mux_top_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:3] mux_tree_tapbuf_size14_0_sram;
wire [0:3] mux_tree_tapbuf_size14_1_sram;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:1] mux_tree_tapbuf_size3_6_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:2] mux_tree_tapbuf_size7_4_sram;
wire [0:2] mux_tree_tapbuf_size7_5_sram;
wire [0:2] mux_tree_tapbuf_size7_6_sram;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_3_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:3] mux_tree_tapbuf_size9_1_sram;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_top_out[13] = top_left_grid_pin_43_[0];
assign chanx_left_out[3] = chanx_right_in[2];
assign chanx_left_out[5] = chanx_right_in[4];
assign chanx_left_out[6] = chanx_right_in[5];
assign chanx_left_out[7] = chanx_right_in[6];
assign chanx_left_out[9] = chanx_right_in[8];
assign chanx_left_out[10] = chanx_right_in[9];
assign chanx_left_out[11] = chanx_right_in[10];
assign chanx_left_out[13] = chanx_right_in[12];
assign chanx_left_out[14] = chanx_right_in[13];
assign chanx_left_out[15] = chanx_right_in[14];
assign chanx_left_out[17] = chanx_right_in[16];
assign chanx_left_out[18] = chanx_right_in[17];
assign chanx_left_out[19] = chanx_right_in[18];
assign chanx_right_out[3] = chanx_left_in[2];
assign chany_top_out[18] = chanx_left_in[3];
assign chanx_right_out[5] = chanx_left_in[4];
assign chanx_right_out[6] = chanx_left_in[5];
assign chanx_right_out[7] = chanx_left_in[6];
assign chany_top_out[17] = chanx_left_in[7];
assign chanx_right_out[9] = chanx_left_in[8];
assign chanx_right_out[10] = chanx_left_in[9];
assign chanx_right_out[11] = chanx_left_in[10];
assign chany_top_out[16] = chanx_left_in[11];
assign chanx_right_out[13] = chanx_left_in[12];
assign chanx_right_out[14] = chanx_left_in[13];
assign chanx_right_out[15] = chanx_left_in[14];
assign chany_top_out[15] = chanx_left_in[15];
assign chanx_right_out[17] = chanx_left_in[16];
assign chanx_right_out[18] = chanx_left_in[17];
assign chanx_right_out[19] = chanx_left_in[18];
assign chany_top_out[14] = chanx_left_in[19];
assign SC_OUT_TOP = SC_IN_TOP;
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size8
mux_top_track_0
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_left_in[0], chanx_left_in[2] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:3]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size8
mux_right_track_8
(
.in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_17_[0], chanx_left_in[6], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:3]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size8
mux_left_track_3
(
.in({ chany_top_in[6], chany_top_in[13], chanx_right_in[4], chanx_right_in[13], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0], left_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:3]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size8
mux_left_track_9
(
.in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], chanx_right_in[6], chanx_right_in[16], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size8_3_sram[0:3]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:3]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size8_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3])
);
mux_tree_tapbuf_size7
mux_top_track_2
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_left_in[4] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:2]),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size7
mux_top_track_4
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[5], chanx_right_in[7], chanx_left_in[5] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:2]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size7
mux_top_track_6
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[6], chanx_right_in[11], chanx_left_in[6] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_top_track_6_undriven_sram_inv[0:2]),
.out(chany_top_out[3])
);
mux_tree_tapbuf_size7
mux_right_track_16
(
.in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_11_[0], chanx_left_in[8], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:2]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size7
mux_right_track_24
(
.in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_13_[0], chanx_left_in[9], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size7_4_sram[0:2]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:2]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size7
mux_left_track_17
(
.in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size7_5_sram[0:2]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:2]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size7
mux_left_track_25
(
.in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], chanx_right_in[9], chanx_right_in[18], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_13_[0] }),
.sram(mux_tree_tapbuf_size7_6_sram[0:2]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:2]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size7_mem
mem_top_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_top_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2])
);
mux_tree_tapbuf_size4
mux_top_track_8
(
.in({ top_left_grid_pin_42_[0], chanx_right_in[8], chanx_right_in[15], chanx_left_in[8] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:2]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size4
mux_top_track_10
(
.in({ top_left_grid_pin_43_[0], chanx_right_in[9], chanx_right_in[19], chanx_left_in[9] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_top_track_10_undriven_sram_inv[0:2]),
.out(chany_top_out[5])
);
mux_tree_tapbuf_size4_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_top_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
mux_tree_tapbuf_size3
mux_top_track_12
(
.in({ top_left_grid_pin_44_[0], chanx_right_in[10], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_top_track_12_undriven_sram_inv[0:1]),
.out(chany_top_out[6])
);
mux_tree_tapbuf_size3
mux_top_track_14
(
.in({ top_left_grid_pin_45_[0], chanx_right_in[12], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_top_track_14_undriven_sram_inv[0:1]),
.out(chany_top_out[7])
);
mux_tree_tapbuf_size3
mux_top_track_16
(
.in({ top_left_grid_pin_46_[0], chanx_right_in[13], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:1]),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size3
mux_top_track_18
(
.in({ top_left_grid_pin_47_[0], chanx_right_in[14], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_top_track_18_undriven_sram_inv[0:1]),
.out(chany_top_out[9])
);
mux_tree_tapbuf_size3
mux_top_track_20
(
.in({ top_left_grid_pin_48_[0], chanx_right_in[16], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_top_track_20_undriven_sram_inv[0:1]),
.out(chany_top_out[10])
);
mux_tree_tapbuf_size3
mux_top_track_22
(
.in({ top_left_grid_pin_49_[0], chanx_right_in[17], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_top_track_22_undriven_sram_inv[0:1]),
.out(chany_top_out[11])
);
mux_tree_tapbuf_size3
mux_top_track_24
(
.in({ top_left_grid_pin_42_[0], chanx_right_in[18], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size3_6_sram[0:1]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:1]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size3_mem
mem_top_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1])
);
mux_tree_tapbuf_size2
mux_top_track_38
(
.in({ chanx_right_in[0], chanx_left_in[1] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_top_track_38_undriven_sram_inv[0:1]),
.out(chany_top_out[19])
);
mux_tree_tapbuf_size2_mem
mem_top_track_38
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size9
mux_right_track_0
(
.in({ chany_top_in[6], chany_top_in[13], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_13_[0], right_bottom_grid_pin_17_[0], chanx_left_in[2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:3]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size9
mux_right_track_2
(
.in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0], right_bottom_grid_pin_15_[0], chanx_left_in[4], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size9_1_sram[0:3]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:3]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size9_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3])
);
mux_tree_tapbuf_size9_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_1_sram[0:3])
);
mux_tree_tapbuf_size14
mux_right_track_4
(
.in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_11_[0], right_bottom_grid_pin_13_[0], right_bottom_grid_pin_15_[0], right_bottom_grid_pin_17_[0], chanx_left_in[5], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size14_0_sram[0:3]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:3]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size14
mux_left_track_5
(
.in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], chanx_right_in[5], chanx_right_in[14], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_11_[0], left_bottom_grid_pin_13_[0], left_bottom_grid_pin_15_[0], left_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size14_1_sram[0:3]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:3]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size14_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_0_sram[0:3])
);
mux_tree_tapbuf_size14_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_1_sram[0:3])
);
mux_tree_tapbuf_size6
mux_right_track_32
(
.in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_15_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:2]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size6
mux_left_track_33
(
.in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], chanx_right_in[10], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:2]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size6_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size10
mux_left_track_1
(
.in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], chanx_right_in[2], chanx_right_in[12], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_13_[0], left_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:3]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size10_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
sky130_fd_sc_hd__buf_4
Test_en_N_FTB01
(
.A(Test_en_S_in),
.X(Test_en_N_out)
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_N_in),
.X(prog_clk_0)
);
sky130_fd_sc_hd__buf_4
prog_clk_3_N_FTB01
(
.A(prog_clk_3_S_in),
.X(prog_clk_3_N_out)
);
sky130_fd_sc_hd__buf_4
clk_3_N_FTB01
(
.A(clk_3_S_in),
.X(clk_3_N_out)
);
endmodule

981
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/routing/sb_1__1_.v Normal file
View File

@ -0,0 +1,981 @@
module sb_1__1_
( chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, chanx_right_in, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_top_out, chanx_right_out, chany_bottom_out, chanx_left_out, ccff_tail, Test_en_S_in, Test_en_N_out, prog_clk_0_N_in, prog_clk_1_N_in, prog_clk_1_S_in, prog_clk_1_E_out, prog_clk_1_W_out, prog_clk_2_N_in, prog_clk_2_E_in, prog_clk_2_S_in, prog_clk_2_W_in, prog_clk_2_W_out, prog_clk_2_S_out, prog_clk_2_N_out, prog_clk_2_E_out, prog_clk_3_W_in, prog_clk_3_E_in, prog_clk_3_S_in, prog_clk_3_N_in, prog_clk_3_E_out, prog_clk_3_W_out, prog_clk_3_N_out, prog_clk_3_S_out, clk_1_N_in, clk_1_S_in, clk_1_E_out, clk_1_W_out, clk_2_N_in, clk_2_E_in, clk_2_S_in, clk_2_W_in, clk_2_W_out, clk_2_S_out, clk_2_N_out, clk_2_E_out, clk_3_W_in, clk_3_E_in, clk_3_S_in, clk_3_N_in, clk_3_E_out, clk_3_W_out, clk_3_N_out, clk_3_S_out );
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input Test_en_S_in;
output Test_en_N_out;
input prog_clk_0_N_in;
input prog_clk_1_N_in;
input prog_clk_1_S_in;
output prog_clk_1_E_out;
output prog_clk_1_W_out;
input prog_clk_2_N_in;
input prog_clk_2_E_in;
input prog_clk_2_S_in;
input prog_clk_2_W_in;
output prog_clk_2_W_out;
output prog_clk_2_S_out;
output prog_clk_2_N_out;
output prog_clk_2_E_out;
input prog_clk_3_W_in;
input prog_clk_3_E_in;
input prog_clk_3_S_in;
input prog_clk_3_N_in;
output prog_clk_3_E_out;
output prog_clk_3_W_out;
output prog_clk_3_N_out;
output prog_clk_3_S_out;
input clk_1_N_in;
input clk_1_S_in;
output clk_1_E_out;
output clk_1_W_out;
input clk_2_N_in;
input clk_2_E_in;
input clk_2_S_in;
input clk_2_W_in;
output clk_2_W_out;
output clk_2_S_out;
output clk_2_N_out;
output clk_2_E_out;
input clk_3_W_in;
input clk_3_E_in;
input clk_3_S_in;
input clk_3_N_in;
output clk_3_E_out;
output clk_3_W_out;
output clk_3_N_out;
output clk_3_S_out;
wire [0:3] mux_bottom_track_17_undriven_sram_inv;
wire [0:3] mux_bottom_track_1_undriven_sram_inv;
wire [0:3] mux_bottom_track_25_undriven_sram_inv;
wire [0:2] mux_bottom_track_33_undriven_sram_inv;
wire [0:3] mux_bottom_track_3_undriven_sram_inv;
wire [0:4] mux_bottom_track_5_undriven_sram_inv;
wire [0:3] mux_bottom_track_9_undriven_sram_inv;
wire [0:3] mux_left_track_17_undriven_sram_inv;
wire [0:3] mux_left_track_1_undriven_sram_inv;
wire [0:3] mux_left_track_25_undriven_sram_inv;
wire [0:2] mux_left_track_33_undriven_sram_inv;
wire [0:3] mux_left_track_3_undriven_sram_inv;
wire [0:4] mux_left_track_5_undriven_sram_inv;
wire [0:3] mux_left_track_9_undriven_sram_inv;
wire [0:3] mux_right_track_0_undriven_sram_inv;
wire [0:3] mux_right_track_16_undriven_sram_inv;
wire [0:3] mux_right_track_24_undriven_sram_inv;
wire [0:3] mux_right_track_2_undriven_sram_inv;
wire [0:2] mux_right_track_32_undriven_sram_inv;
wire [0:4] mux_right_track_4_undriven_sram_inv;
wire [0:3] mux_right_track_8_undriven_sram_inv;
wire [0:3] mux_top_track_0_undriven_sram_inv;
wire [0:3] mux_top_track_16_undriven_sram_inv;
wire [0:3] mux_top_track_24_undriven_sram_inv;
wire [0:3] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_32_undriven_sram_inv;
wire [0:4] mux_top_track_4_undriven_sram_inv;
wire [0:3] mux_top_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_10_sram;
wire [0:3] mux_tree_tapbuf_size10_11_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_4_sram;
wire [0:3] mux_tree_tapbuf_size10_5_sram;
wire [0:3] mux_tree_tapbuf_size10_6_sram;
wire [0:3] mux_tree_tapbuf_size10_7_sram;
wire [0:3] mux_tree_tapbuf_size10_8_sram;
wire [0:3] mux_tree_tapbuf_size10_9_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail;
wire [0:3] mux_tree_tapbuf_size12_0_sram;
wire [0:3] mux_tree_tapbuf_size12_1_sram;
wire [0:3] mux_tree_tapbuf_size12_2_sram;
wire [0:3] mux_tree_tapbuf_size12_3_sram;
wire [0:3] mux_tree_tapbuf_size12_4_sram;
wire [0:3] mux_tree_tapbuf_size12_5_sram;
wire [0:3] mux_tree_tapbuf_size12_6_sram;
wire [0:3] mux_tree_tapbuf_size12_7_sram;
wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail;
wire [0:4] mux_tree_tapbuf_size16_0_sram;
wire [0:4] mux_tree_tapbuf_size16_1_sram;
wire [0:4] mux_tree_tapbuf_size16_2_sram;
wire [0:4] mux_tree_tapbuf_size16_3_sram;
wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_bottom_out[3] = chany_top_in[2];
assign chany_bottom_out[5] = chany_top_in[4];
assign chany_bottom_out[6] = chany_top_in[5];
assign chany_bottom_out[7] = chany_top_in[6];
assign chany_bottom_out[9] = chany_top_in[8];
assign chany_bottom_out[10] = chany_top_in[9];
assign chany_bottom_out[11] = chany_top_in[10];
assign chany_bottom_out[13] = chany_top_in[12];
assign chany_bottom_out[14] = chany_top_in[13];
assign chany_bottom_out[15] = chany_top_in[14];
assign chany_bottom_out[17] = chany_top_in[16];
assign chany_bottom_out[18] = chany_top_in[17];
assign chany_bottom_out[19] = chany_top_in[18];
assign chanx_left_out[3] = chanx_right_in[2];
assign chanx_left_out[5] = chanx_right_in[4];
assign chanx_left_out[6] = chanx_right_in[5];
assign chanx_left_out[7] = chanx_right_in[6];
assign chanx_left_out[9] = chanx_right_in[8];
assign chanx_left_out[10] = chanx_right_in[9];
assign chanx_left_out[11] = chanx_right_in[10];
assign chanx_left_out[13] = chanx_right_in[12];
assign chanx_left_out[14] = chanx_right_in[13];
assign chanx_left_out[15] = chanx_right_in[14];
assign chanx_left_out[17] = chanx_right_in[16];
assign chanx_left_out[18] = chanx_right_in[17];
assign chanx_left_out[19] = chanx_right_in[18];
assign chany_top_out[3] = chany_bottom_in[2];
assign chany_top_out[5] = chany_bottom_in[4];
assign chany_top_out[6] = chany_bottom_in[5];
assign chany_top_out[7] = chany_bottom_in[6];
assign chany_top_out[9] = chany_bottom_in[8];
assign chany_top_out[10] = chany_bottom_in[9];
assign chany_top_out[11] = chany_bottom_in[10];
assign chany_top_out[13] = chany_bottom_in[12];
assign chany_top_out[14] = chany_bottom_in[13];
assign chany_top_out[15] = chany_bottom_in[14];
assign chany_top_out[17] = chany_bottom_in[16];
assign chany_top_out[18] = chany_bottom_in[17];
assign chany_top_out[19] = chany_bottom_in[18];
assign chanx_right_out[3] = chanx_left_in[2];
assign chanx_right_out[5] = chanx_left_in[4];
assign chanx_right_out[6] = chanx_left_in[5];
assign chanx_right_out[7] = chanx_left_in[6];
assign chanx_right_out[9] = chanx_left_in[8];
assign chanx_right_out[10] = chanx_left_in[9];
assign chanx_right_out[11] = chanx_left_in[10];
assign chanx_right_out[13] = chanx_left_in[12];
assign chanx_right_out[14] = chanx_left_in[13];
assign chanx_right_out[15] = chanx_left_in[14];
assign chanx_right_out[17] = chanx_left_in[16];
assign chanx_right_out[18] = chanx_left_in[17];
assign chanx_right_out[19] = chanx_left_in[18];
assign prog_clk_0 = prog_clk;
assign prog_clk_1_N_in = prog_clk_1_S_in;
assign prog_clk_2_N_in = prog_clk_2_E_in;
assign prog_clk_2_E_in = prog_clk_2_S_in;
assign prog_clk_2_S_in = prog_clk_2_W_in;
assign prog_clk_3_W_in = prog_clk_3_E_in;
assign prog_clk_3_E_in = prog_clk_3_S_in;
assign prog_clk_3_S_in = prog_clk_3_N_in;
assign clk_1_N_in = clk_1_S_in;
assign clk_2_N_in = clk_2_E_in;
assign clk_2_E_in = clk_2_S_in;
assign clk_2_S_in = clk_2_W_in;
assign clk_3_W_in = clk_3_E_in;
assign clk_3_E_in = clk_3_S_in;
assign clk_3_S_in = clk_3_N_in;
mux_tree_tapbuf_size12
mux_top_track_0
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size12_0_sram[0:3]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:3]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size12
mux_top_track_2
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_right_in[13], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size12_1_sram[0:3]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:3]),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size12
mux_right_track_0
(
.in({ chany_top_in[2], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[15], chanx_left_in[2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size12_2_sram[0:3]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:3]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size12
mux_right_track_2
(
.in({ chany_top_in[0], chany_top_in[4], chany_top_in[13], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size12_3_sram[0:3]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:3]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size12
mux_bottom_track_1
(
.in({ chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chanx_right_in[15], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size12_4_sram[0:3]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:3]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size12
mux_bottom_track_3
(
.in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[13], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size12_5_sram[0:3]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:3]),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size12
mux_left_track_1
(
.in({ chany_top_in[0], chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size12_6_sram[0:3]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:3]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size12
mux_left_track_3
(
.in({ chany_top_in[4], chany_top_in[13], chany_top_in[19], chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[13], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size12_7_sram[0:3]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:3]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size12_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_0_sram[0:3])
);
mux_tree_tapbuf_size12_mem
mem_top_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_1_sram[0:3])
);
mux_tree_tapbuf_size12_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_2_sram[0:3])
);
mux_tree_tapbuf_size12_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_3_sram[0:3])
);
mux_tree_tapbuf_size12_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_4_sram[0:3])
);
mux_tree_tapbuf_size12_mem
mem_bottom_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_5_sram[0:3])
);
mux_tree_tapbuf_size12_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_6_sram[0:3])
);
mux_tree_tapbuf_size12_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size12_7_sram[0:3])
);
mux_tree_tapbuf_size16
mux_top_track_4
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14:15] }),
.sram(mux_tree_tapbuf_size16_0_sram[0:4]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:4]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size16
mux_right_track_4
(
.in({ chany_top_in[1], chany_top_in[5], chany_top_in[14], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size16_1_sram[0:4]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:4]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size16
mux_bottom_track_5
(
.in({ chany_top_in[5], chany_top_in[14], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[5], chanx_left_in[7], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size16_2_sram[0:4]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:4]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size16
mux_left_track_5
(
.in({ chany_top_in[5], chany_top_in[14:15], chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[5], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size16_3_sram[0:4]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:4]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size16_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size16_0_sram[0:4])
);
mux_tree_tapbuf_size16_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size16_1_sram[0:4])
);
mux_tree_tapbuf_size16_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size16_2_sram[0:4])
);
mux_tree_tapbuf_size16_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size16_3_sram[0:4])
);
mux_tree_tapbuf_size10
mux_top_track_8
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], chanx_right_in[6], chanx_right_in[11], chanx_right_in[16], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:3]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size10
mux_top_track_16
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chanx_right_in[8], chanx_right_in[15], chanx_right_in[17], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[7:8], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:3]),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size10
mux_top_track_24
(
.in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chanx_right_in[9], chanx_right_in[18:19], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[3], chanx_left_in[9], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:3]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size10
mux_right_track_8
(
.in({ chany_top_in[3], chany_top_in[6], chany_top_in[16], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:3]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size10
mux_right_track_16
(
.in({ chany_top_in[7:8], chany_top_in[17], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[8], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size10_4_sram[0:3]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:3]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size10
mux_right_track_24
(
.in({ chany_top_in[9], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[9], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size10_5_sram[0:3]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:3]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size10
mux_bottom_track_9
(
.in({ chany_top_in[6], chany_top_in[16], chanx_right_in[3], chanx_right_in[6], chanx_right_in[16], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size10_6_sram[0:3]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:3]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size10
mux_bottom_track_17
(
.in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[17], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[8], chanx_left_in[15], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size10_7_sram[0:3]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:3]),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size10
mux_bottom_track_25
(
.in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[9], chanx_right_in[18], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[9], chanx_left_in[18:19] }),
.sram(mux_tree_tapbuf_size10_8_sram[0:3]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:3]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size10
mux_left_track_9
(
.in({ chany_top_in[6], chany_top_in[11], chany_top_in[16], chanx_right_in[6], chanx_right_in[16], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size10_9_sram[0:3]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:3]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size10
mux_left_track_17
(
.in({ chany_top_in[7:8], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], chany_bottom_in[7:8], chany_bottom_in[17], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size10_10_sram[0:3]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:3]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size10
mux_left_track_25
(
.in({ chany_top_in[3], chany_top_in[9], chany_top_in[18], chanx_right_in[9], chanx_right_in[18], chany_bottom_in[9], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size10_11_sram[0:3]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:3]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size10_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_bottom_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_8_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_9_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_10_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_11_sram[0:3])
);
mux_tree_tapbuf_size7
mux_top_track_32
(
.in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chanx_right_in[0], chanx_right_in[10], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_top_track_32_undriven_sram_inv[0:2]),
.out(chany_top_out[16])
);
mux_tree_tapbuf_size7
mux_right_track_32
(
.in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[10], chany_bottom_in[19], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:2]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size7
mux_bottom_track_33
(
.in({ chany_top_in[10], chanx_right_in[10], chanx_right_in[19], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_bottom_track_33_undriven_sram_inv[0:2]),
.out(chany_bottom_out[16])
);
mux_tree_tapbuf_size7
mux_left_track_33
(
.in({ chany_top_in[1], chany_top_in[10], chanx_right_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:2]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size7_mem
mem_top_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);
sky130_fd_sc_hd__buf_4
Test_en_N_FTB01
(
.A(Test_en_S_in),
.X(Test_en_N_out)
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_N_in),
.X(prog_clk_0)
);
sky130_fd_sc_hd__buf_4
prog_clk_1_E_FTB01
(
.A(prog_clk_1_N_in),
.X(prog_clk_1_E_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_1_W_FTB01
(
.A(prog_clk_1_N_in),
.X(prog_clk_1_W_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_2_W_FTB01
(
.A(prog_clk_2_N_in),
.X(prog_clk_2_W_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_2_S_FTB01
(
.A(prog_clk_2_N_in),
.X(prog_clk_2_S_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_2_N_FTB01
(
.A(prog_clk_2_N_in),
.X(prog_clk_2_N_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_2_E_FTB01
(
.A(prog_clk_2_N_in),
.X(prog_clk_2_E_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_3_E_FTB01
(
.A(prog_clk_3_W_in),
.X(prog_clk_3_E_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_3_W_FTB01
(
.A(prog_clk_3_W_in),
.X(prog_clk_3_W_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_3_N_FTB01
(
.A(prog_clk_3_W_in),
.X(prog_clk_3_N_out)
);
sky130_fd_sc_hd__buf_4
prog_clk_3_S_FTB01
(
.A(prog_clk_3_W_in),
.X(prog_clk_3_S_out)
);
sky130_fd_sc_hd__buf_4
clk_1_E_FTB01
(
.A(clk_1_N_in),
.X(clk_1_E_out)
);
sky130_fd_sc_hd__buf_4
clk_1_W_FTB01
(
.A(clk_1_N_in),
.X(clk_1_W_out)
);
sky130_fd_sc_hd__buf_4
clk_2_W_FTB01
(
.A(clk_2_N_in),
.X(clk_2_W_out)
);
sky130_fd_sc_hd__buf_4
clk_2_S_FTB01
(
.A(clk_2_N_in),
.X(clk_2_S_out)
);
sky130_fd_sc_hd__buf_4
clk_2_N_FTB01
(
.A(clk_2_N_in),
.X(clk_2_N_out)
);
sky130_fd_sc_hd__buf_4
clk_2_E_FTB01
(
.A(clk_2_N_in),
.X(clk_2_E_out)
);
sky130_fd_sc_hd__buf_4
clk_3_E_FTB01
(
.A(clk_3_W_in),
.X(clk_3_E_out)
);
sky130_fd_sc_hd__buf_4
clk_3_W_FTB01
(
.A(clk_3_W_in),
.X(clk_3_W_out)
);
sky130_fd_sc_hd__buf_4
clk_3_N_FTB01
(
.A(clk_3_W_in),
.X(clk_3_N_out)
);
sky130_fd_sc_hd__buf_4
clk_3_S_FTB01
(
.A(clk_3_W_in),
.X(clk_3_S_out)
);
endmodule

732
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/routing/sb_1__2_.v Normal file
View File

@ -0,0 +1,732 @@
module sb_1__2_
( chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chanx_right_out, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_BOT, SC_OUT_BOT, prog_clk_0_S_in );
input [0:19] chanx_right_in;
input [0:0] right_top_grid_pin_1_;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_top_grid_pin_1_;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input SC_IN_BOT;
output SC_OUT_BOT;
input prog_clk_0_S_in;
wire [0:2] mux_bottom_track_11_undriven_sram_inv;
wire [0:1] mux_bottom_track_13_undriven_sram_inv;
wire [0:1] mux_bottom_track_15_undriven_sram_inv;
wire [0:1] mux_bottom_track_17_undriven_sram_inv;
wire [0:1] mux_bottom_track_19_undriven_sram_inv;
wire [0:2] mux_bottom_track_1_undriven_sram_inv;
wire [0:1] mux_bottom_track_21_undriven_sram_inv;
wire [0:1] mux_bottom_track_23_undriven_sram_inv;
wire [0:2] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_27_undriven_sram_inv;
wire [0:2] mux_bottom_track_3_undriven_sram_inv;
wire [0:2] mux_bottom_track_5_undriven_sram_inv;
wire [0:2] mux_bottom_track_7_undriven_sram_inv;
wire [0:2] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_left_track_17_undriven_sram_inv;
wire [0:3] mux_left_track_1_undriven_sram_inv;
wire [0:2] mux_left_track_25_undriven_sram_inv;
wire [0:2] mux_left_track_33_undriven_sram_inv;
wire [0:3] mux_left_track_3_undriven_sram_inv;
wire [0:3] mux_left_track_5_undriven_sram_inv;
wire [0:3] mux_left_track_9_undriven_sram_inv;
wire [0:3] mux_right_track_0_undriven_sram_inv;
wire [0:2] mux_right_track_16_undriven_sram_inv;
wire [0:2] mux_right_track_24_undriven_sram_inv;
wire [0:3] mux_right_track_2_undriven_sram_inv;
wire [0:2] mux_right_track_32_undriven_sram_inv;
wire [0:3] mux_right_track_4_undriven_sram_inv;
wire [0:3] mux_right_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:3] mux_tree_tapbuf_size14_0_sram;
wire [0:3] mux_tree_tapbuf_size14_1_sram;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:2] mux_tree_tapbuf_size7_4_sram;
wire [0:2] mux_tree_tapbuf_size7_5_sram;
wire [0:2] mux_tree_tapbuf_size7_6_sram;
wire [0:2] mux_tree_tapbuf_size7_7_sram;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:3] mux_tree_tapbuf_size9_1_sram;
wire [0:3] mux_tree_tapbuf_size9_2_sram;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_bottom_out[18] = chanx_right_in[0];
assign chany_bottom_out[17] = chanx_right_in[1];
assign chanx_left_out[3] = chanx_right_in[2];
assign chany_bottom_out[16] = chanx_right_in[3];
assign chanx_left_out[5] = chanx_right_in[4];
assign chanx_left_out[6] = chanx_right_in[5];
assign chanx_left_out[7] = chanx_right_in[6];
assign chany_bottom_out[15] = chanx_right_in[7];
assign chanx_left_out[9] = chanx_right_in[8];
assign chanx_left_out[10] = chanx_right_in[9];
assign chanx_left_out[11] = chanx_right_in[10];
assign chany_bottom_out[14] = chanx_right_in[11];
assign chanx_left_out[13] = chanx_right_in[12];
assign chanx_left_out[14] = chanx_right_in[13];
assign chanx_left_out[15] = chanx_right_in[14];
assign chanx_left_out[17] = chanx_right_in[16];
assign chanx_left_out[18] = chanx_right_in[17];
assign chanx_left_out[19] = chanx_right_in[18];
assign chany_bottom_out[19] = chanx_left_in[0];
assign chanx_right_out[3] = chanx_left_in[2];
assign chanx_right_out[5] = chanx_left_in[4];
assign chanx_right_out[6] = chanx_left_in[5];
assign chanx_right_out[7] = chanx_left_in[6];
assign chanx_right_out[9] = chanx_left_in[8];
assign chanx_right_out[10] = chanx_left_in[9];
assign chanx_right_out[11] = chanx_left_in[10];
assign chanx_right_out[13] = chanx_left_in[12];
assign chanx_right_out[14] = chanx_left_in[13];
assign chanx_right_out[15] = chanx_left_in[14];
assign chanx_right_out[17] = chanx_left_in[16];
assign chanx_right_out[18] = chanx_left_in[17];
assign chanx_right_out[19] = chanx_left_in[18];
assign SC_OUT_BOT = SC_IN_BOT;
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size10
mux_right_track_0
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], chanx_left_in[2], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_right_track_0_undriven_sram_inv[0:3]),
.out(chanx_right_out[0])
);
mux_tree_tapbuf_size10_mem
mem_right_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size9
mux_right_track_2
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], chanx_left_in[4], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_right_track_2_undriven_sram_inv[0:3]),
.out(chanx_right_out[1])
);
mux_tree_tapbuf_size9
mux_left_track_1
(
.in({ chanx_right_in[2], chanx_right_in[12], chany_bottom_in[6], chany_bottom_in[13], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size9_1_sram[0:3]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:3]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size9
mux_left_track_3
(
.in({ chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size9_2_sram[0:3]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:3]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size9_mem
mem_right_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3])
);
mux_tree_tapbuf_size9_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_1_sram[0:3])
);
mux_tree_tapbuf_size9_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_2_sram[0:3])
);
mux_tree_tapbuf_size14
mux_right_track_4
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], chanx_left_in[5], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size14_0_sram[0:3]),
.sram_inv(mux_right_track_4_undriven_sram_inv[0:3]),
.out(chanx_right_out[2])
);
mux_tree_tapbuf_size14
mux_left_track_5
(
.in({ chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], left_top_grid_pin_1_[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size14_1_sram[0:3]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:3]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size14_mem
mem_right_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_0_sram[0:3])
);
mux_tree_tapbuf_size14_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_1_sram[0:3])
);
mux_tree_tapbuf_size8
mux_right_track_8
(
.in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_right_track_8_undriven_sram_inv[0:3]),
.out(chanx_right_out[4])
);
mux_tree_tapbuf_size8
mux_left_track_9
(
.in({ chanx_right_in[6], chanx_right_in[16], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], left_top_grid_pin_1_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:3]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size8_mem
mem_right_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size7
mux_right_track_16
(
.in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], chanx_left_in[8], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_right_track_16_undriven_sram_inv[0:2]),
.out(chanx_right_out[8])
);
mux_tree_tapbuf_size7
mux_right_track_24
(
.in({ right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[9], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_right_track_24_undriven_sram_inv[0:2]),
.out(chanx_right_out[12])
);
mux_tree_tapbuf_size7
mux_bottom_track_1
(
.in({ chanx_right_in[2], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size7
mux_bottom_track_3
(
.in({ chanx_right_in[4], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size7
mux_bottom_track_5
(
.in({ chanx_right_in[5], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[5], chanx_left_in[7] }),
.sram(mux_tree_tapbuf_size7_4_sram[0:2]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size7
mux_bottom_track_7
(
.in({ chanx_right_in[6], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[6], chanx_left_in[11] }),
.sram(mux_tree_tapbuf_size7_5_sram[0:2]),
.sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]),
.out(chany_bottom_out[3])
);
mux_tree_tapbuf_size7
mux_left_track_17
(
.in({ chanx_right_in[8], chanx_right_in[17], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size7_6_sram[0:2]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:2]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size7
mux_left_track_25
(
.in({ chanx_right_in[9], chanx_right_in[18], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size7_7_sram[0:2]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:2]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size7_mem
mem_right_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_right_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_7_sram[0:2])
);
mux_tree_tapbuf_size5
mux_right_track_32
(
.in({ right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[6], chany_bottom_in[13], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_right_track_32_undriven_sram_inv[0:2]),
.out(chanx_right_out[16])
);
mux_tree_tapbuf_size5_mem
mem_right_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size4
mux_bottom_track_9
(
.in({ chanx_right_in[8], bottom_left_grid_pin_42_[0], chanx_left_in[8], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:2]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size4
mux_bottom_track_11
(
.in({ chanx_right_in[9], bottom_left_grid_pin_43_[0], chanx_left_in[9], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_bottom_track_11_undriven_sram_inv[0:2]),
.out(chany_bottom_out[5])
);
mux_tree_tapbuf_size4
mux_bottom_track_25
(
.in({ chanx_right_in[18:19], bottom_left_grid_pin_42_[0], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size4_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_bottom_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
mux_tree_tapbuf_size3
mux_bottom_track_13
(
.in({ chanx_right_in[10], bottom_left_grid_pin_44_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]),
.out(chany_bottom_out[6])
);
mux_tree_tapbuf_size3
mux_bottom_track_15
(
.in({ chanx_right_in[12], bottom_left_grid_pin_45_[0], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]),
.out(chany_bottom_out[7])
);
mux_tree_tapbuf_size3
mux_bottom_track_17
(
.in({ chanx_right_in[13], bottom_left_grid_pin_46_[0], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size3
mux_bottom_track_19
(
.in({ chanx_right_in[14], bottom_left_grid_pin_47_[0], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]),
.out(chany_bottom_out[9])
);
mux_tree_tapbuf_size3
mux_bottom_track_21
(
.in({ chanx_right_in[16], bottom_left_grid_pin_48_[0], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]),
.out(chany_bottom_out[10])
);
mux_tree_tapbuf_size3
mux_bottom_track_23
(
.in({ chanx_right_in[17], bottom_left_grid_pin_49_[0], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_bottom_track_23_undriven_sram_inv[0:1]),
.out(chany_bottom_out[11])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_21
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_23
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1])
);
mux_tree_tapbuf_size2
mux_bottom_track_27
(
.in({ chanx_right_in[15], bottom_left_grid_pin_43_[0] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_bottom_track_27_undriven_sram_inv[0:1]),
.out(chany_bottom_out[13])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_27
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size6
mux_left_track_33
(
.in({ chanx_right_in[10], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:2]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size6_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_S_in),
.X(prog_clk_0)
);
endmodule

831
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/routing/sb_2__0_.v Normal file
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@ -0,0 +1,831 @@
module sb_2__0_
( chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, top_right_grid_pin_1_, chanx_left_in, left_bottom_grid_pin_1_, left_bottom_grid_pin_3_, left_bottom_grid_pin_5_, left_bottom_grid_pin_7_, left_bottom_grid_pin_9_, left_bottom_grid_pin_11_, left_bottom_grid_pin_13_, left_bottom_grid_pin_15_, left_bottom_grid_pin_17_, ccff_head, chany_top_out, chanx_left_out, ccff_tail, prog_clk_0_N_in );
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:0] top_right_grid_pin_1_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_1_;
input [0:0] left_bottom_grid_pin_3_;
input [0:0] left_bottom_grid_pin_5_;
input [0:0] left_bottom_grid_pin_7_;
input [0:0] left_bottom_grid_pin_9_;
input [0:0] left_bottom_grid_pin_11_;
input [0:0] left_bottom_grid_pin_13_;
input [0:0] left_bottom_grid_pin_15_;
input [0:0] left_bottom_grid_pin_17_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input prog_clk_0_N_in;
wire [0:1] mux_left_track_11_undriven_sram_inv;
wire [0:1] mux_left_track_13_undriven_sram_inv;
wire [0:1] mux_left_track_15_undriven_sram_inv;
wire [0:1] mux_left_track_17_undriven_sram_inv;
wire [0:1] mux_left_track_19_undriven_sram_inv;
wire [0:2] mux_left_track_1_undriven_sram_inv;
wire [0:1] mux_left_track_21_undriven_sram_inv;
wire [0:1] mux_left_track_23_undriven_sram_inv;
wire [0:1] mux_left_track_25_undriven_sram_inv;
wire [0:1] mux_left_track_27_undriven_sram_inv;
wire [0:1] mux_left_track_29_undriven_sram_inv;
wire [0:1] mux_left_track_31_undriven_sram_inv;
wire [0:1] mux_left_track_33_undriven_sram_inv;
wire [0:1] mux_left_track_35_undriven_sram_inv;
wire [0:1] mux_left_track_37_undriven_sram_inv;
wire [0:1] mux_left_track_39_undriven_sram_inv;
wire [0:2] mux_left_track_3_undriven_sram_inv;
wire [0:2] mux_left_track_5_undriven_sram_inv;
wire [0:2] mux_left_track_7_undriven_sram_inv;
wire [0:1] mux_left_track_9_undriven_sram_inv;
wire [0:2] mux_top_track_0_undriven_sram_inv;
wire [0:1] mux_top_track_10_undriven_sram_inv;
wire [0:1] mux_top_track_12_undriven_sram_inv;
wire [0:1] mux_top_track_14_undriven_sram_inv;
wire [0:1] mux_top_track_16_undriven_sram_inv;
wire [0:1] mux_top_track_18_undriven_sram_inv;
wire [0:1] mux_top_track_20_undriven_sram_inv;
wire [0:1] mux_top_track_22_undriven_sram_inv;
wire [0:1] mux_top_track_24_undriven_sram_inv;
wire [0:1] mux_top_track_26_undriven_sram_inv;
wire [0:2] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_4_undriven_sram_inv;
wire [0:2] mux_top_track_6_undriven_sram_inv;
wire [0:1] mux_top_track_8_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_18_sram;
wire [0:1] mux_tree_tapbuf_size2_19_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_20_sram;
wire [0:1] mux_tree_tapbuf_size2_21_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_2_sram;
wire [0:2] mux_tree_tapbuf_size5_3_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_top_out[19] = chanx_left_in[1];
assign chany_top_out[18] = chanx_left_in[2];
assign chany_top_out[17] = chanx_left_in[3];
assign chany_top_out[16] = chanx_left_in[4];
assign chany_top_out[15] = chanx_left_in[5];
assign chany_top_out[14] = chanx_left_in[6];
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size6
mux_top_track_0
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[0] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:2]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size6
mux_top_track_4
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:2]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size6
mux_left_track_1
(
.in({ chany_top_in[0], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_13_[0], left_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:2]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size6
mux_left_track_5
(
.in({ chany_top_in[18], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_13_[0], left_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:2]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size6_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2])
);
mux_tree_tapbuf_size5
mux_top_track_2
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:2]),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size5
mux_top_track_6
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_top_track_6_undriven_sram_inv[0:2]),
.out(chany_top_out[3])
);
mux_tree_tapbuf_size5
mux_left_track_3
(
.in({ chany_top_in[19], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0], left_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size5_2_sram[0:2]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:2]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size5
mux_left_track_7
(
.in({ chany_top_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0], left_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size5_3_sram[0:2]),
.sram_inv(mux_left_track_7_undriven_sram_inv[0:2]),
.out(chanx_left_out[3])
);
mux_tree_tapbuf_size5_mem
mem_top_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_top_track_6
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_2_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_left_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_3_sram[0:2])
);
mux_tree_tapbuf_size3
mux_top_track_8
(
.in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:1]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size3
mux_top_track_24
(
.in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[8] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:1]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size3
mux_left_track_9
(
.in({ chany_top_in[16], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:1]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size3
mux_left_track_25
(
.in({ chany_top_in[8], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_17_[0] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:1]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size3_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
mux_tree_tapbuf_size2
mux_top_track_10
(
.in({ top_left_grid_pin_43_[0], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_top_track_10_undriven_sram_inv[0:1]),
.out(chany_top_out[5])
);
mux_tree_tapbuf_size2
mux_top_track_12
(
.in({ top_left_grid_pin_44_[0], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_top_track_12_undriven_sram_inv[0:1]),
.out(chany_top_out[6])
);
mux_tree_tapbuf_size2
mux_top_track_14
(
.in({ top_left_grid_pin_45_[0], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_top_track_14_undriven_sram_inv[0:1]),
.out(chany_top_out[7])
);
mux_tree_tapbuf_size2
mux_top_track_16
(
.in({ top_left_grid_pin_46_[0], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:1]),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size2
mux_top_track_18
(
.in({ top_left_grid_pin_47_[0], chanx_left_in[11] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_top_track_18_undriven_sram_inv[0:1]),
.out(chany_top_out[9])
);
mux_tree_tapbuf_size2
mux_top_track_20
(
.in({ top_left_grid_pin_48_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_top_track_20_undriven_sram_inv[0:1]),
.out(chany_top_out[10])
);
mux_tree_tapbuf_size2
mux_top_track_22
(
.in({ top_left_grid_pin_49_[0], chanx_left_in[9] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_top_track_22_undriven_sram_inv[0:1]),
.out(chany_top_out[11])
);
mux_tree_tapbuf_size2
mux_top_track_26
(
.in({ top_left_grid_pin_43_[0], chanx_left_in[7] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_top_track_26_undriven_sram_inv[0:1]),
.out(chany_top_out[13])
);
mux_tree_tapbuf_size2
mux_left_track_11
(
.in({ chany_top_in[15], left_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_left_track_11_undriven_sram_inv[0:1]),
.out(chanx_left_out[5])
);
mux_tree_tapbuf_size2
mux_left_track_13
(
.in({ chany_top_in[14], left_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_left_track_13_undriven_sram_inv[0:1]),
.out(chanx_left_out[6])
);
mux_tree_tapbuf_size2
mux_left_track_15
(
.in({ chany_top_in[13], left_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_left_track_15_undriven_sram_inv[0:1]),
.out(chanx_left_out[7])
);
mux_tree_tapbuf_size2
mux_left_track_17
(
.in({ chany_top_in[12], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:1]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size2
mux_left_track_19
(
.in({ chany_top_in[11], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_left_track_19_undriven_sram_inv[0:1]),
.out(chanx_left_out[9])
);
mux_tree_tapbuf_size2
mux_left_track_21
(
.in({ chany_top_in[10], left_bottom_grid_pin_13_[0] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_left_track_21_undriven_sram_inv[0:1]),
.out(chanx_left_out[10])
);
mux_tree_tapbuf_size2
mux_left_track_23
(
.in({ chany_top_in[9], left_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_left_track_23_undriven_sram_inv[0:1]),
.out(chanx_left_out[11])
);
mux_tree_tapbuf_size2
mux_left_track_27
(
.in({ chany_top_in[7], left_bottom_grid_pin_3_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_left_track_27_undriven_sram_inv[0:1]),
.out(chanx_left_out[13])
);
mux_tree_tapbuf_size2
mux_left_track_29
(
.in({ chany_top_in[6], left_bottom_grid_pin_5_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_left_track_29_undriven_sram_inv[0:1]),
.out(chanx_left_out[14])
);
mux_tree_tapbuf_size2
mux_left_track_31
(
.in({ chany_top_in[5], left_bottom_grid_pin_7_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_left_track_31_undriven_sram_inv[0:1]),
.out(chanx_left_out[15])
);
mux_tree_tapbuf_size2
mux_left_track_33
(
.in({ chany_top_in[4], left_bottom_grid_pin_9_[0] }),
.sram(mux_tree_tapbuf_size2_18_sram[0:1]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:1]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size2
mux_left_track_35
(
.in({ chany_top_in[3], left_bottom_grid_pin_11_[0] }),
.sram(mux_tree_tapbuf_size2_19_sram[0:1]),
.sram_inv(mux_left_track_35_undriven_sram_inv[0:1]),
.out(chanx_left_out[17])
);
mux_tree_tapbuf_size2
mux_left_track_37
(
.in({ chany_top_in[2], left_bottom_grid_pin_13_[0] }),
.sram(mux_tree_tapbuf_size2_20_sram[0:1]),
.sram_inv(mux_left_track_37_undriven_sram_inv[0:1]),
.out(chanx_left_out[18])
);
mux_tree_tapbuf_size2
mux_left_track_39
(
.in({ chany_top_in[1], left_bottom_grid_pin_15_[0] }),
.sram(mux_tree_tapbuf_size2_21_sram[0:1]),
.sram_inv(mux_left_track_39_undriven_sram_inv[0:1]),
.out(chanx_left_out[19])
);
mux_tree_tapbuf_size2_mem
mem_top_track_10
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_12
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_14
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_18
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_20
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_22
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_top_track_26
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_21
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_23
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_27
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_29
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_31
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_18_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_35
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_19_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_37
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_20_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_39
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_21_sram[0:1])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_N_in),
.X(prog_clk_0)
);
endmodule

839
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/routing/sb_2__1_.v Normal file
View File

@ -0,0 +1,839 @@
module sb_2__1_
( chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, top_right_grid_pin_1_, chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_top_out, chany_bottom_out, chanx_left_out, ccff_tail, prog_clk_0_N_in );
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:0] top_right_grid_pin_1_;
input [0:19] chany_bottom_in;
input [0:0] bottom_right_grid_pin_1_;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input prog_clk_0_N_in;
wire [0:2] mux_bottom_track_17_undriven_sram_inv;
wire [0:3] mux_bottom_track_1_undriven_sram_inv;
wire [0:2] mux_bottom_track_25_undriven_sram_inv;
wire [0:2] mux_bottom_track_33_undriven_sram_inv;
wire [0:3] mux_bottom_track_3_undriven_sram_inv;
wire [0:3] mux_bottom_track_5_undriven_sram_inv;
wire [0:3] mux_bottom_track_9_undriven_sram_inv;
wire [0:2] mux_left_track_11_undriven_sram_inv;
wire [0:2] mux_left_track_13_undriven_sram_inv;
wire [0:2] mux_left_track_15_undriven_sram_inv;
wire [0:1] mux_left_track_17_undriven_sram_inv;
wire [0:1] mux_left_track_19_undriven_sram_inv;
wire [0:2] mux_left_track_1_undriven_sram_inv;
wire [0:1] mux_left_track_21_undriven_sram_inv;
wire [0:1] mux_left_track_23_undriven_sram_inv;
wire [0:1] mux_left_track_25_undriven_sram_inv;
wire [0:1] mux_left_track_29_undriven_sram_inv;
wire [0:1] mux_left_track_31_undriven_sram_inv;
wire [0:1] mux_left_track_33_undriven_sram_inv;
wire [0:1] mux_left_track_35_undriven_sram_inv;
wire [0:1] mux_left_track_37_undriven_sram_inv;
wire [0:1] mux_left_track_39_undriven_sram_inv;
wire [0:2] mux_left_track_3_undriven_sram_inv;
wire [0:2] mux_left_track_5_undriven_sram_inv;
wire [0:2] mux_left_track_7_undriven_sram_inv;
wire [0:2] mux_left_track_9_undriven_sram_inv;
wire [0:3] mux_top_track_0_undriven_sram_inv;
wire [0:2] mux_top_track_16_undriven_sram_inv;
wire [0:2] mux_top_track_24_undriven_sram_inv;
wire [0:3] mux_top_track_2_undriven_sram_inv;
wire [0:2] mux_top_track_32_undriven_sram_inv;
wire [0:3] mux_top_track_4_undriven_sram_inv;
wire [0:3] mux_top_track_8_undriven_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:3] mux_tree_tapbuf_size14_0_sram;
wire [0:3] mux_tree_tapbuf_size14_1_sram;
wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:2] mux_tree_tapbuf_size7_0_sram;
wire [0:2] mux_tree_tapbuf_size7_1_sram;
wire [0:2] mux_tree_tapbuf_size7_2_sram;
wire [0:2] mux_tree_tapbuf_size7_3_sram;
wire [0:2] mux_tree_tapbuf_size7_4_sram;
wire [0:2] mux_tree_tapbuf_size7_5_sram;
wire [0:2] mux_tree_tapbuf_size7_6_sram;
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_bottom_out[3] = chany_top_in[2];
assign chany_bottom_out[5] = chany_top_in[4];
assign chany_bottom_out[6] = chany_top_in[5];
assign chany_bottom_out[7] = chany_top_in[6];
assign chany_bottom_out[9] = chany_top_in[8];
assign chany_bottom_out[10] = chany_top_in[9];
assign chany_bottom_out[11] = chany_top_in[10];
assign chany_bottom_out[13] = chany_top_in[12];
assign chany_bottom_out[14] = chany_top_in[13];
assign chany_bottom_out[15] = chany_top_in[14];
assign chany_bottom_out[17] = chany_top_in[16];
assign chany_bottom_out[18] = chany_top_in[17];
assign chany_bottom_out[19] = chany_top_in[18];
assign chany_top_out[3] = chany_bottom_in[2];
assign chany_top_out[5] = chany_bottom_in[4];
assign chany_top_out[6] = chany_bottom_in[5];
assign chany_top_out[7] = chany_bottom_in[6];
assign chany_top_out[9] = chany_bottom_in[8];
assign chany_top_out[10] = chany_bottom_in[9];
assign chany_top_out[11] = chany_bottom_in[10];
assign chany_top_out[13] = chany_bottom_in[12];
assign chany_top_out[14] = chany_bottom_in[13];
assign chany_top_out[15] = chany_bottom_in[14];
assign chany_top_out[17] = chany_bottom_in[16];
assign chany_top_out[18] = chany_bottom_in[17];
assign chany_top_out[19] = chany_bottom_in[18];
assign chanx_left_out[13] = left_bottom_grid_pin_35_[0];
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size10
mux_top_track_0
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_top_track_0_undriven_sram_inv[0:3]),
.out(chany_top_out[0])
);
mux_tree_tapbuf_size10
mux_bottom_track_1
(
.in({ chany_top_in[2], chany_top_in[12], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:3]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size10_mem
mem_top_track_0
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3])
);
mux_tree_tapbuf_size10_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3])
);
mux_tree_tapbuf_size8
mux_top_track_2
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[6], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_top_track_2_undriven_sram_inv[0:3]),
.out(chany_top_out[1])
);
mux_tree_tapbuf_size8
mux_top_track_8
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], top_right_grid_pin_1_[0], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_top_track_8_undriven_sram_inv[0:3]),
.out(chany_top_out[4])
);
mux_tree_tapbuf_size8
mux_bottom_track_9
(
.in({ chany_top_in[6], chany_top_in[16], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:3]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size8_mem
mem_top_track_2
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_top_track_8
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3])
);
mux_tree_tapbuf_size8_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3])
);
mux_tree_tapbuf_size14
mux_top_track_4
(
.in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], top_right_grid_pin_1_[0], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size14_0_sram[0:3]),
.sram_inv(mux_top_track_4_undriven_sram_inv[0:3]),
.out(chany_top_out[2])
);
mux_tree_tapbuf_size14
mux_bottom_track_5
(
.in({ chany_top_in[5], chany_top_in[14], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size14_1_sram[0:3]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:3]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size14_mem
mem_top_track_4
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_0_sram[0:3])
);
mux_tree_tapbuf_size14_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size14_1_sram[0:3])
);
mux_tree_tapbuf_size7
mux_top_track_16
(
.in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }),
.sram(mux_tree_tapbuf_size7_0_sram[0:2]),
.sram_inv(mux_top_track_16_undriven_sram_inv[0:2]),
.out(chany_top_out[8])
);
mux_tree_tapbuf_size7
mux_top_track_24
(
.in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size7_1_sram[0:2]),
.sram_inv(mux_top_track_24_undriven_sram_inv[0:2]),
.out(chany_top_out[12])
);
mux_tree_tapbuf_size7
mux_bottom_track_17
(
.in({ chany_top_in[8], chany_top_in[17], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }),
.sram(mux_tree_tapbuf_size7_2_sram[0:2]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:2]),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size7
mux_left_track_1
(
.in({ chany_top_in[0], chany_top_in[2], chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size7_3_sram[0:2]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:2]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size7
mux_left_track_3
(
.in({ chany_top_in[4], chany_bottom_in[0], chany_bottom_in[4], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size7_4_sram[0:2]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:2]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size7
mux_left_track_5
(
.in({ chany_top_in[5], chany_bottom_in[1], chany_bottom_in[5], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size7_5_sram[0:2]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:2]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size7
mux_left_track_7
(
.in({ chany_top_in[6], chany_bottom_in[3], chany_bottom_in[6], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size7_6_sram[0:2]),
.sram_inv(mux_left_track_7_undriven_sram_inv[0:2]),
.out(chanx_left_out[3])
);
mux_tree_tapbuf_size7_mem
mem_top_track_16
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_0_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_top_track_24
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_1_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_bottom_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_2_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_3_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_4_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_5_sram[0:2])
);
mux_tree_tapbuf_size7_mem
mem_left_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size7_6_sram[0:2])
);
mux_tree_tapbuf_size6
mux_top_track_32
(
.in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_top_track_32_undriven_sram_inv[0:2]),
.out(chany_top_out[16])
);
mux_tree_tapbuf_size6
mux_bottom_track_25
(
.in({ chany_top_in[9], chany_top_in[18], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[6], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size6
mux_bottom_track_33
(
.in({ chany_top_in[10], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_bottom_track_33_undriven_sram_inv[0:2]),
.out(chany_bottom_out[16])
);
mux_tree_tapbuf_size6_mem
mem_top_track_32
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2])
);
mux_tree_tapbuf_size9
mux_bottom_track_3
(
.in({ chany_top_in[4], chany_top_in[13], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:3]),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size9_mem
mem_bottom_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3])
);
mux_tree_tapbuf_size4
mux_left_track_9
(
.in({ chany_top_in[8], chany_bottom_in[7:8], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:2]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size4
mux_left_track_11
(
.in({ chany_top_in[9], chany_bottom_in[9], chany_bottom_in[11], left_bottom_grid_pin_35_[0] }),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_left_track_11_undriven_sram_inv[0:2]),
.out(chanx_left_out[5])
);
mux_tree_tapbuf_size4
mux_left_track_13
(
.in({ chany_top_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_left_track_13_undriven_sram_inv[0:2]),
.out(chanx_left_out[6])
);
mux_tree_tapbuf_size4
mux_left_track_15
(
.in({ chany_top_in[12], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_left_track_15_undriven_sram_inv[0:2]),
.out(chanx_left_out[7])
);
mux_tree_tapbuf_size4_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_left_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_left_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2])
);
mux_tree_tapbuf_size4_mem
mem_left_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2])
);
mux_tree_tapbuf_size3
mux_left_track_17
(
.in({ chany_top_in[13], chany_bottom_in[13], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:1]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size3
mux_left_track_19
(
.in({ chany_top_in[14], chany_bottom_in[14], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_left_track_19_undriven_sram_inv[0:1]),
.out(chanx_left_out[9])
);
mux_tree_tapbuf_size3
mux_left_track_21
(
.in({ chany_top_in[16], chany_bottom_in[16], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_left_track_21_undriven_sram_inv[0:1]),
.out(chanx_left_out[10])
);
mux_tree_tapbuf_size3
mux_left_track_23
(
.in({ chany_top_in[17], chany_bottom_in[17], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_left_track_23_undriven_sram_inv[0:1]),
.out(chanx_left_out[11])
);
mux_tree_tapbuf_size3
mux_left_track_25
(
.in({ chany_top_in[18], chany_bottom_in[18], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:1]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size3_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_21
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_23
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1])
);
mux_tree_tapbuf_size2
mux_left_track_29
(
.in({ chany_top_in[19], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_left_track_29_undriven_sram_inv[0:1]),
.out(chanx_left_out[14])
);
mux_tree_tapbuf_size2
mux_left_track_31
(
.in({ chany_top_in[15], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_left_track_31_undriven_sram_inv[0:1]),
.out(chanx_left_out[15])
);
mux_tree_tapbuf_size2
mux_left_track_33
(
.in({ chany_top_in[11], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:1]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size2
mux_left_track_35
(
.in({ chany_top_in[7], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_left_track_35_undriven_sram_inv[0:1]),
.out(chanx_left_out[17])
);
mux_tree_tapbuf_size2
mux_left_track_37
(
.in({ chany_top_in[3], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_left_track_37_undriven_sram_inv[0:1]),
.out(chanx_left_out[18])
);
mux_tree_tapbuf_size2
mux_left_track_39
(
.in({ chany_top_in[1], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_left_track_39_undriven_sram_inv[0:1]),
.out(chanx_left_out[19])
);
mux_tree_tapbuf_size2_mem
mem_left_track_29
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_31
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_35
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_37
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_39
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_N_in),
.X(prog_clk_0)
);
endmodule

856
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/routing/sb_2__2_.v Normal file
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@ -0,0 +1,856 @@
module sb_2__2_
( chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_BOT, SC_OUT_BOT, prog_clk_0_S_in );
input [0:19] chany_bottom_in;
input [0:0] bottom_right_grid_pin_1_;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_top_grid_pin_1_;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input SC_IN_BOT;
output SC_OUT_BOT;
input prog_clk_0_S_in;
wire [0:1] mux_bottom_track_11_undriven_sram_inv;
wire [0:1] mux_bottom_track_13_undriven_sram_inv;
wire [0:1] mux_bottom_track_15_undriven_sram_inv;
wire [0:1] mux_bottom_track_17_undriven_sram_inv;
wire [0:1] mux_bottom_track_19_undriven_sram_inv;
wire [0:2] mux_bottom_track_1_undriven_sram_inv;
wire [0:1] mux_bottom_track_21_undriven_sram_inv;
wire [0:1] mux_bottom_track_23_undriven_sram_inv;
wire [0:1] mux_bottom_track_25_undriven_sram_inv;
wire [0:1] mux_bottom_track_27_undriven_sram_inv;
wire [0:1] mux_bottom_track_29_undriven_sram_inv;
wire [0:2] mux_bottom_track_3_undriven_sram_inv;
wire [0:2] mux_bottom_track_5_undriven_sram_inv;
wire [0:2] mux_bottom_track_7_undriven_sram_inv;
wire [0:1] mux_bottom_track_9_undriven_sram_inv;
wire [0:1] mux_left_track_11_undriven_sram_inv;
wire [0:1] mux_left_track_13_undriven_sram_inv;
wire [0:1] mux_left_track_15_undriven_sram_inv;
wire [0:1] mux_left_track_17_undriven_sram_inv;
wire [0:1] mux_left_track_19_undriven_sram_inv;
wire [0:2] mux_left_track_1_undriven_sram_inv;
wire [0:1] mux_left_track_21_undriven_sram_inv;
wire [0:1] mux_left_track_23_undriven_sram_inv;
wire [0:1] mux_left_track_25_undriven_sram_inv;
wire [0:1] mux_left_track_27_undriven_sram_inv;
wire [0:1] mux_left_track_29_undriven_sram_inv;
wire [0:1] mux_left_track_31_undriven_sram_inv;
wire [0:1] mux_left_track_33_undriven_sram_inv;
wire [0:1] mux_left_track_35_undriven_sram_inv;
wire [0:1] mux_left_track_37_undriven_sram_inv;
wire [0:1] mux_left_track_39_undriven_sram_inv;
wire [0:2] mux_left_track_3_undriven_sram_inv;
wire [0:2] mux_left_track_5_undriven_sram_inv;
wire [0:2] mux_left_track_7_undriven_sram_inv;
wire [0:1] mux_left_track_9_undriven_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_18_sram;
wire [0:1] mux_tree_tapbuf_size2_19_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_20_sram;
wire [0:1] mux_tree_tapbuf_size2_21_sram;
wire [0:1] mux_tree_tapbuf_size2_22_sram;
wire [0:1] mux_tree_tapbuf_size2_23_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_1_sram;
wire [0:2] mux_tree_tapbuf_size5_2_sram;
wire [0:2] mux_tree_tapbuf_size5_3_sram;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail;
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
wire prog_clk_0;
wire [0:0] prog_clk;
assign chany_bottom_out[19] = chanx_left_in[0];
assign chany_bottom_out[15] = chanx_left_in[16];
assign chany_bottom_out[16] = chanx_left_in[17];
assign chany_bottom_out[17] = chanx_left_in[18];
assign chany_bottom_out[18] = chanx_left_in[19];
assign SC_OUT_BOT = SC_IN_BOT;
assign prog_clk_0 = prog_clk;
mux_tree_tapbuf_size6
mux_bottom_track_1
(
.in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1] }),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]),
.out(chany_bottom_out[0])
);
mux_tree_tapbuf_size6
mux_bottom_track_5
(
.in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3] }),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]),
.out(chany_bottom_out[2])
);
mux_tree_tapbuf_size6
mux_left_track_1
(
.in({ chany_bottom_in[19], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_left_track_1_undriven_sram_inv[0:2]),
.out(chanx_left_out[0])
);
mux_tree_tapbuf_size6
mux_left_track_5
(
.in({ chany_bottom_in[1], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_left_track_5_undriven_sram_inv[0:2]),
.out(chanx_left_out[2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_bottom_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_left_track_1
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2])
);
mux_tree_tapbuf_size6_mem
mem_left_track_5
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2])
);
mux_tree_tapbuf_size5
mux_bottom_track_3
(
.in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2] }),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]),
.out(chany_bottom_out[1])
);
mux_tree_tapbuf_size5
mux_bottom_track_7
(
.in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[4] }),
.sram(mux_tree_tapbuf_size5_1_sram[0:2]),
.sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]),
.out(chany_bottom_out[3])
);
mux_tree_tapbuf_size5
mux_left_track_3
(
.in({ chany_bottom_in[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size5_2_sram[0:2]),
.sram_inv(mux_left_track_3_undriven_sram_inv[0:2]),
.out(chanx_left_out[1])
);
mux_tree_tapbuf_size5
mux_left_track_7
(
.in({ chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size5_3_sram[0:2]),
.sram_inv(mux_left_track_7_undriven_sram_inv[0:2]),
.out(chanx_left_out[3])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_bottom_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_1_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_left_track_3
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_2_sram[0:2])
);
mux_tree_tapbuf_size5_mem
mem_left_track_7
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size5_3_sram[0:2])
);
mux_tree_tapbuf_size2
mux_bottom_track_9
(
.in({ bottom_right_grid_pin_1_[0], chanx_left_in[5] }),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]),
.out(chany_bottom_out[4])
);
mux_tree_tapbuf_size2
mux_bottom_track_11
(
.in({ bottom_left_grid_pin_42_[0], chanx_left_in[6] }),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_bottom_track_11_undriven_sram_inv[0:1]),
.out(chany_bottom_out[5])
);
mux_tree_tapbuf_size2
mux_bottom_track_13
(
.in({ bottom_left_grid_pin_43_[0], chanx_left_in[7] }),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]),
.out(chany_bottom_out[6])
);
mux_tree_tapbuf_size2
mux_bottom_track_15
(
.in({ bottom_left_grid_pin_44_[0], chanx_left_in[8] }),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]),
.out(chany_bottom_out[7])
);
mux_tree_tapbuf_size2
mux_bottom_track_17
(
.in({ bottom_left_grid_pin_45_[0], chanx_left_in[9] }),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]),
.out(chany_bottom_out[8])
);
mux_tree_tapbuf_size2
mux_bottom_track_19
(
.in({ bottom_left_grid_pin_46_[0], chanx_left_in[10] }),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]),
.out(chany_bottom_out[9])
);
mux_tree_tapbuf_size2
mux_bottom_track_21
(
.in({ bottom_left_grid_pin_47_[0], chanx_left_in[11] }),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]),
.out(chany_bottom_out[10])
);
mux_tree_tapbuf_size2
mux_bottom_track_23
(
.in({ bottom_left_grid_pin_48_[0], chanx_left_in[12] }),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_bottom_track_23_undriven_sram_inv[0:1]),
.out(chany_bottom_out[11])
);
mux_tree_tapbuf_size2
mux_bottom_track_27
(
.in({ bottom_left_grid_pin_42_[0], chanx_left_in[14] }),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_bottom_track_27_undriven_sram_inv[0:1]),
.out(chany_bottom_out[13])
);
mux_tree_tapbuf_size2
mux_bottom_track_29
(
.in({ bottom_left_grid_pin_43_[0], chanx_left_in[15] }),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_bottom_track_29_undriven_sram_inv[0:1]),
.out(chany_bottom_out[14])
);
mux_tree_tapbuf_size2
mux_left_track_11
(
.in({ chany_bottom_in[4], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_left_track_11_undriven_sram_inv[0:1]),
.out(chanx_left_out[5])
);
mux_tree_tapbuf_size2
mux_left_track_13
(
.in({ chany_bottom_in[5], left_bottom_grid_pin_35_[0] }),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_left_track_13_undriven_sram_inv[0:1]),
.out(chanx_left_out[6])
);
mux_tree_tapbuf_size2
mux_left_track_15
(
.in({ chany_bottom_in[6], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_left_track_15_undriven_sram_inv[0:1]),
.out(chanx_left_out[7])
);
mux_tree_tapbuf_size2
mux_left_track_17
(
.in({ chany_bottom_in[7], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_left_track_17_undriven_sram_inv[0:1]),
.out(chanx_left_out[8])
);
mux_tree_tapbuf_size2
mux_left_track_19
(
.in({ chany_bottom_in[8], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_left_track_19_undriven_sram_inv[0:1]),
.out(chanx_left_out[9])
);
mux_tree_tapbuf_size2
mux_left_track_21
(
.in({ chany_bottom_in[9], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_left_track_21_undriven_sram_inv[0:1]),
.out(chanx_left_out[10])
);
mux_tree_tapbuf_size2
mux_left_track_23
(
.in({ chany_bottom_in[10], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_left_track_23_undriven_sram_inv[0:1]),
.out(chanx_left_out[11])
);
mux_tree_tapbuf_size2
mux_left_track_27
(
.in({ chany_bottom_in[12], left_bottom_grid_pin_34_[0] }),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_left_track_27_undriven_sram_inv[0:1]),
.out(chanx_left_out[13])
);
mux_tree_tapbuf_size2
mux_left_track_29
(
.in({ chany_bottom_in[13], left_bottom_grid_pin_35_[0] }),
.sram(mux_tree_tapbuf_size2_18_sram[0:1]),
.sram_inv(mux_left_track_29_undriven_sram_inv[0:1]),
.out(chanx_left_out[14])
);
mux_tree_tapbuf_size2
mux_left_track_31
(
.in({ chany_bottom_in[14], left_bottom_grid_pin_36_[0] }),
.sram(mux_tree_tapbuf_size2_19_sram[0:1]),
.sram_inv(mux_left_track_31_undriven_sram_inv[0:1]),
.out(chanx_left_out[15])
);
mux_tree_tapbuf_size2
mux_left_track_33
(
.in({ chany_bottom_in[15], left_bottom_grid_pin_37_[0] }),
.sram(mux_tree_tapbuf_size2_20_sram[0:1]),
.sram_inv(mux_left_track_33_undriven_sram_inv[0:1]),
.out(chanx_left_out[16])
);
mux_tree_tapbuf_size2
mux_left_track_35
(
.in({ chany_bottom_in[16], left_bottom_grid_pin_38_[0] }),
.sram(mux_tree_tapbuf_size2_21_sram[0:1]),
.sram_inv(mux_left_track_35_undriven_sram_inv[0:1]),
.out(chanx_left_out[17])
);
mux_tree_tapbuf_size2
mux_left_track_37
(
.in({ chany_bottom_in[17], left_bottom_grid_pin_39_[0] }),
.sram(mux_tree_tapbuf_size2_22_sram[0:1]),
.sram_inv(mux_left_track_37_undriven_sram_inv[0:1]),
.out(chanx_left_out[18])
);
mux_tree_tapbuf_size2
mux_left_track_39
(
.in({ chany_bottom_in[18], left_bottom_grid_pin_40_[0] }),
.sram(mux_tree_tapbuf_size2_23_sram[0:1]),
.sram_inv(mux_left_track_39_undriven_sram_inv[0:1]),
.out(chanx_left_out[19])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_21
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_23
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_27
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_bottom_track_29
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_11
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_13
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_15
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_17
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_19
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_21
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_23
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_27
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_29
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_18_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_31
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_19_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_33
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_20_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_35
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_21_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_37
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_22_sram[0:1])
);
mux_tree_tapbuf_size2_mem
mem_left_track_39
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]),
.ccff_tail(ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size2_23_sram[0:1])
);
mux_tree_tapbuf_size3
mux_bottom_track_25
(
.in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_49_[0], chanx_left_in[13] }),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_bottom_track_25_undriven_sram_inv[0:1]),
.out(chany_bottom_out[12])
);
mux_tree_tapbuf_size3
mux_left_track_9
(
.in({ chany_bottom_in[3], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_left_track_9_undriven_sram_inv[0:1]),
.out(chanx_left_out[4])
);
mux_tree_tapbuf_size3
mux_left_track_25
(
.in({ chany_bottom_in[11], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_left_track_25_undriven_sram_inv[0:1]),
.out(chanx_left_out[12])
);
mux_tree_tapbuf_size3_mem
mem_bottom_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_9
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1])
);
mux_tree_tapbuf_size3_mem
mem_left_track_25
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1])
);
sky130_fd_sc_hd__buf_8
prog_clk_0_FTB00
(
.A(prog_clk_0_S_in),
.X(prog_clk_0)
);
endmodule

10
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/sub_module/arch_encoder.v Normal file
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@ -0,0 +1,10 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps

55
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/sub_module/digital_io_hd.v Normal file
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`timescale 1ns/1ps
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
module EMBEDDED_IO_HD (
input SOC_IN, //
output SOC_OUT, //
output SOC_DIR, //
output FPGA_IN, //
input FPGA_OUT, //
input FPGA_DIR, //
input IO_ISOL_N //
);
wire SOC_DIR_N;
//
sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (.B_N(IO_ISOL_N),
.A(FPGA_DIR),
.X(SOC_DIR)
);
//
sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR), .Y(SOC_DIR_N));
sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE (.TE_B(SOC_DIR_N),
.A(SOC_IN),
.Z(FPGA_IN)
);
//
sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE (.TE_B(SOC_DIR),
.A(FPGA_OUT),
.Z(SOC_OUT)
);
endmodule

422
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/sub_module/fpga_top.v Normal file
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/*
*-------------------------------------------------------------
*
* A wrapper for the FPGA IP to fit the I/O interface of Caravel SoC
*
* The wrapper is a technology mapped netlist where the mode-switch
* multiplexers are mapped to the Skywater 130nm
* High-Density (HD) standard cells
*
*-------------------------------------------------------------
*/
module fpga_top (
//
//
inout vdda1, //
inout vdda2, //
inout vssa1, //
inout vssa2, //
inout vccd1, //
inout vccd2, //
inout vssd1, //
inout vssd2, //
//
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
//
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oen,
//
input [37:0] io_in,
output [37:0] io_out,
output [37:0] io_oeb
);
//
//
//
//
//
//
//
//
wire prog_clk;
wire Test_en;
wire io_isol_n;
wire clk;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire ccff_head;
wire ccff_tail;
wire sc_head;
wire sc_tail;
//
wire wb_la_switch;
wire wb_la_switch_b;
//
//
//
//
//
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24];
assign io_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0];
assign io_oeb[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0];
//
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1:9] = io_in[23:15];
assign io_out[23:15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1:9];
assign io_oeb[23:15] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1:9];
//
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10:11] = io_in[14:13];
assign io_out[14:13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10:11];
assign io_oeb[14:13] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10:11];
//
assign ccff_head = io_in[12];
assign io_out[12] = 1'b0;
assign io_oeb[12] = 1'b1;
assign io_out[11] = sc_tail;
assign io_oeb[11] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12:20] = io_in[10:2];
assign io_out[10:2] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12:20];
assign io_oeb[10:2] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12:20];
assign io_isol_n = io_in[1];
assign io_out[1] = 1'b0;
assign io_oeb[1] = 1'b1;
assign Test_en = io_in[0];
assign io_out[0] = 1'b0;
assign io_oeb[0] = 1'b1;
//
//
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX (.S(wb_la_switch), .A1(wb_clk_i), .A0(la_data_in[13]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135]));
assign la_data_out[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX (.S(wb_la_switch), .A1(wb_rst_i), .A0(la_data_in[14]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134]));
assign la_data_out[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[15];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(wbs_ack_o));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(la_data_out[15]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX (.S(wb_la_switch), .A1(wbs_cyc_i), .A0(la_data_in[16]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132]));
assign la_data_out[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX (.S(wb_la_switch), .A1(wbs_stb_i), .A0(la_data_in[17]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131]));
assign la_data_out[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX (.S(wb_la_switch), .A1(wbs_we_i), .A0(la_data_in[18]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130]));
assign la_data_out[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX (.S(wb_la_switch), .A1(wbs_sel_i[0]), .A0(la_data_in[19]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129]));
assign la_data_out[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX (.S(wb_la_switch), .A1(wbs_sel_i[1]), .A0(la_data_in[20]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128]));
assign la_data_out[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX (.S(wb_la_switch), .A1(wbs_sel_i[2]), .A0(la_data_in[21]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127]));
assign la_data_out[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX (.S(wb_la_switch), .A1(wbs_sel_i[3]), .A0(la_data_in[22]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126]));
assign la_data_out[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX (.S(wb_la_switch), .A1(wbs_adr_i[0]), .A0(la_data_in[23]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125]));
assign la_data_out[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX (.S(wb_la_switch), .A1(wbs_adr_i[1]), .A0(la_data_in[24]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124]));
assign la_data_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX (.S(wb_la_switch), .A1(wbs_adr_i[2]), .A0(la_data_in[25]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123]));
assign la_data_out[25] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX (.S(wb_la_switch), .A1(wbs_adr_i[3]), .A0(la_data_in[26]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122]));
assign la_data_out[26] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX (.S(wb_la_switch), .A1(wbs_adr_i[4]), .A0(la_data_in[27]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121]));
assign la_data_out[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX (.S(wb_la_switch), .A1(wbs_adr_i[5]), .A0(la_data_in[28]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120]));
assign la_data_out[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX (.S(wb_la_switch), .A1(wbs_adr_i[6]), .A0(la_data_in[29]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119]));
assign la_data_out[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX (.S(wb_la_switch), .A1(wbs_adr_i[7]), .A0(la_data_in[30]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118]));
assign la_data_out[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX (.S(wb_la_switch), .A1(wbs_adr_i[8]), .A0(la_data_in[31]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117]));
assign la_data_out[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX (.S(wb_la_switch), .A1(wbs_adr_i[9]), .A0(la_data_in[32]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116]));
assign la_data_out[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX (.S(wb_la_switch), .A1(wbs_adr_i[10]), .A0(la_data_in[33]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115]));
assign la_data_out[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX (.S(wb_la_switch), .A1(wbs_adr_i[11]), .A0(la_data_in[34]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114]));
assign la_data_out[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX (.S(wb_la_switch), .A1(wbs_adr_i[12]), .A0(la_data_in[35]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113]));
assign la_data_out[35] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX (.S(wb_la_switch), .A1(wbs_adr_i[13]), .A0(la_data_in[36]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112]));
assign la_data_out[36] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX (.S(wb_la_switch), .A1(wbs_adr_i[14]), .A0(la_data_in[37]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111]));
assign la_data_out[37] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX (.S(wb_la_switch), .A1(wbs_adr_i[15]), .A0(la_data_in[38]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110]));
assign la_data_out[38] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX (.S(wb_la_switch), .A1(wbs_adr_i[16]), .A0(la_data_in[39]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109]));
assign la_data_out[39] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX (.S(wb_la_switch), .A1(wbs_adr_i[17]), .A0(la_data_in[40]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108]));
assign la_data_out[40] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX (.S(wb_la_switch), .A1(wbs_adr_i[18]), .A0(la_data_in[41]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107]));
assign la_data_out[41] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX (.S(wb_la_switch), .A1(wbs_adr_i[19]), .A0(la_data_in[42]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106]));
assign la_data_out[42] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX (.S(wb_la_switch), .A1(wbs_adr_i[20]), .A0(la_data_in[43]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105]));
assign la_data_out[43] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX (.S(wb_la_switch), .A1(wbs_adr_i[21]), .A0(la_data_in[44]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104]));
assign la_data_out[44] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX (.S(wb_la_switch), .A1(wbs_adr_i[22]), .A0(la_data_in[45]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103]));
assign la_data_out[45] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX (.S(wb_la_switch), .A1(wbs_adr_i[23]), .A0(la_data_in[46]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102]));
assign la_data_out[46] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX (.S(wb_la_switch), .A1(wbs_adr_i[24]), .A0(la_data_in[47]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101]));
assign la_data_out[47] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX (.S(wb_la_switch), .A1(wbs_adr_i[25]), .A0(la_data_in[48]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100]));
assign la_data_out[48] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX (.S(wb_la_switch), .A1(wbs_adr_i[26]), .A0(la_data_in[49]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99]));
assign la_data_out[49] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX (.S(wb_la_switch), .A1(wbs_adr_i[27]), .A0(la_data_in[50]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98]));
assign la_data_out[50] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX (.S(wb_la_switch), .A1(wbs_adr_i[28]), .A0(la_data_in[51]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97]));
assign la_data_out[51] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX (.S(wb_la_switch), .A1(wbs_adr_i[29]), .A0(la_data_in[52]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96]));
assign la_data_out[52] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX (.S(wb_la_switch), .A1(wbs_adr_i[30]), .A0(la_data_in[53]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95]));
assign la_data_out[53] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX (.S(wb_la_switch), .A1(wbs_adr_i[31]), .A0(la_data_in[54]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94]));
assign la_data_out[54] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX (.S(wb_la_switch), .A1(wbs_dat_i[0]), .A0(la_data_in[55]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93]));
assign la_data_out[55] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX (.S(wb_la_switch), .A1(wbs_dat_i[1]), .A0(la_data_in[56]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92]));
assign la_data_out[56] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX (.S(wb_la_switch), .A1(wbs_dat_i[2]), .A0(la_data_in[57]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91]));
assign la_data_out[57] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX (.S(wb_la_switch), .A1(wbs_dat_i[3]), .A0(la_data_in[58]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90]));
assign la_data_out[58] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX (.S(wb_la_switch), .A1(wbs_dat_i[4]), .A0(la_data_in[59]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89]));
assign la_data_out[59] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX (.S(wb_la_switch), .A1(wbs_dat_i[5]), .A0(la_data_in[60]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88]));
assign la_data_out[60] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX (.S(wb_la_switch), .A1(wbs_dat_i[6]), .A0(la_data_in[61]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87]));
assign la_data_out[61] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX (.S(wb_la_switch), .A1(wbs_dat_i[7]), .A0(la_data_in[62]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86]));
assign la_data_out[62] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX (.S(wb_la_switch), .A1(wbs_dat_i[8]), .A0(la_data_in[63]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85]));
assign la_data_out[63] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX (.S(wb_la_switch), .A1(wbs_dat_i[9]), .A0(la_data_in[64]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84]));
assign la_data_out[64] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX (.S(wb_la_switch), .A1(wbs_dat_i[10]), .A0(la_data_in[65]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83]));
assign la_data_out[65] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX (.S(wb_la_switch), .A1(wbs_dat_i[11]), .A0(la_data_in[66]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82]));
assign la_data_out[66] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX (.S(wb_la_switch), .A1(wbs_dat_i[12]), .A0(la_data_in[67]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81]));
assign la_data_out[67] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX (.S(wb_la_switch), .A1(wbs_dat_i[13]), .A0(la_data_in[68]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80]));
assign la_data_out[68] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX (.S(wb_la_switch), .A1(wbs_dat_i[14]), .A0(la_data_in[69]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79]));
assign la_data_out[69] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX (.S(wb_la_switch), .A1(wbs_dat_i[15]), .A0(la_data_in[70]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78]));
assign la_data_out[70] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX (.S(wb_la_switch), .A1(wbs_dat_i[16]), .A0(la_data_in[71]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77]));
assign la_data_out[71] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX (.S(wb_la_switch), .A1(wbs_dat_i[17]), .A0(la_data_in[72]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76]));
assign la_data_out[72] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX (.S(wb_la_switch), .A1(wbs_dat_i[18]), .A0(la_data_in[73]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75]));
assign la_data_out[73] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX (.S(wb_la_switch), .A1(wbs_dat_i[19]), .A0(la_data_in[74]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74]));
assign la_data_out[74] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX (.S(wb_la_switch), .A1(wbs_dat_i[20]), .A0(la_data_in[75]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73]));
assign la_data_out[75] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX (.S(wb_la_switch), .A1(wbs_dat_i[21]), .A0(la_data_in[76]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72]));
assign la_data_out[76] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX (.S(wb_la_switch), .A1(wbs_dat_i[22]), .A0(la_data_in[77]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71]));
assign la_data_out[77] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX (.S(wb_la_switch), .A1(wbs_dat_i[23]), .A0(la_data_in[78]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70]));
assign la_data_out[78] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX (.S(wb_la_switch), .A1(wbs_dat_i[24]), .A0(la_data_in[79]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69]));
assign la_data_out[79] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX (.S(wb_la_switch), .A1(wbs_dat_i[25]), .A0(la_data_in[80]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68]));
assign la_data_out[80] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX (.S(wb_la_switch), .A1(wbs_dat_i[26]), .A0(la_data_in[81]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67]));
assign la_data_out[81] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX (.S(wb_la_switch), .A1(wbs_dat_i[27]), .A0(la_data_in[82]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66]));
assign la_data_out[82] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX (.S(wb_la_switch), .A1(wbs_dat_i[28]), .A0(la_data_in[83]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65]));
assign la_data_out[83] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX (.S(wb_la_switch), .A1(wbs_dat_i[29]), .A0(la_data_in[84]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64]));
assign la_data_out[84] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX (.S(wb_la_switch), .A1(wbs_dat_i[30]), .A0(la_data_in[85]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63]));
assign la_data_out[85] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX (.S(wb_la_switch), .A1(wbs_dat_i[31]), .A0(la_data_in[86]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62]));
assign la_data_out[86] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[87];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(wbs_dat_o[0]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(la_data_out[87]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[88];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(wbs_dat_o[1]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(la_data_out[88]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[89];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(wbs_dat_o[2]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(la_data_out[89]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[90];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(wbs_dat_o[3]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(la_data_out[90]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[91];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(wbs_dat_o[4]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(la_data_out[91]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[92];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(wbs_dat_o[5]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(la_data_out[92]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[93];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(wbs_dat_o[6]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(la_data_out[93]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[94];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(wbs_dat_o[7]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(la_data_out[94]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[95];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(wbs_dat_o[8]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(la_data_out[95]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[96];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(wbs_dat_o[9]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(la_data_out[96]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[97];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(wbs_dat_o[10]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(la_data_out[97]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[98];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(wbs_dat_o[11]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(la_data_out[98]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[99];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(wbs_dat_o[12]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(la_data_out[99]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[100];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(wbs_dat_o[13]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(la_data_out[100]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[101];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(wbs_dat_o[14]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(la_data_out[101]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[102];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(wbs_dat_o[15]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(la_data_out[102]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[103];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(wbs_dat_o[16]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(la_data_out[103]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[104];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(wbs_dat_o[17]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(la_data_out[104]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[105];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(wbs_dat_o[18]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(la_data_out[105]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[106];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(wbs_dat_o[19]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(la_data_out[106]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[107];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(wbs_dat_o[20]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(la_data_out[107]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[108];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(wbs_dat_o[21]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(la_data_out[108]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[109];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(wbs_dat_o[22]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(la_data_out[109]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[110];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(wbs_dat_o[23]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(la_data_out[110]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[111];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(wbs_dat_o[24]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(la_data_out[111]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[112];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(wbs_dat_o[25]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(la_data_out[112]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[113];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(wbs_dat_o[26]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(la_data_out[113]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[114];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(wbs_dat_o[27]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(la_data_out[114]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[115];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(wbs_dat_o[28]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(la_data_out[115]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[116];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(wbs_dat_o[29]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(la_data_out[116]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[117];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(wbs_dat_o[30]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(la_data_out[117]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[118];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(wbs_dat_o[31]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(la_data_out[118]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[119];
assign la_data_out[119] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[120];
assign la_data_out[120] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[121];
assign la_data_out[121] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[122];
assign la_data_out[122] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[123];
assign la_data_out[123] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[124];
assign la_data_out[124] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[125];
assign la_data_out[125] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[126];
assign la_data_out[126] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[127];
assign la_data_out[127] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21];
//
//
assign prog_clk = io_in[37];
assign io_out[37] = 1'b0;
assign io_oeb[37] = 1'b1;
//
assign clk = io_in[36];
assign io_out[36] = 1'b0;
assign io_oeb[36] = 1'b1;
assign io_out[35] = ccff_tail;
assign io_oeb[35] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136:143] = io_in[34:27];
assign io_out[34:27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136:143];
assign io_oeb[34:27] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136:143];
assign sc_head = io_in[26];
assign io_out[26] = 1'b0;
assign io_oeb[26] = 1'b1;
//
//
assign wb_la_switch = io_in[25];
assign io_out[25] = 1'b0;
assign io_oeb[25] = 1'b1;
//
fpga_core fpga_core_uut(.prog_clk(prog_clk),
.Test_en(Test_en),
.clk(clk),
.IO_ISOL_N(io_isol_n),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),
.sc_head(sc_head),
.sc_tail(sc_tail)
);
endmodule

42
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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module const0(const0);
//
output [0:0] const0;
//
//
//
//
assign const0[0] = 1'b0;
endmodule
//
//
module const1(const1);
//
output [0:0] const1;
//
//
//
//
assign const1[0] = 1'b1;
endmodule
//

10
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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps

107
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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module frac_lut4(in,
sram,
sram_inv,
mode,
mode_inv,
lut3_out,
lut4_out);
//
input [0:3] in;
//
input [0:15] sram;
//
input [0:15] sram_inv;
//
input [0:0] mode;
//
input [0:0] mode_inv;
//
output [0:1] lut3_out;
//
output [0:0] lut4_out;
//
wire [0:3] in;
wire [0:1] lut3_out;
wire [0:0] lut4_out;
//
//
//
wire [0:0] sky130_fd_sc_hd__buf_2_0_X;
wire [0:0] sky130_fd_sc_hd__buf_2_1_X;
wire [0:0] sky130_fd_sc_hd__buf_2_2_X;
wire [0:0] sky130_fd_sc_hd__buf_2_3_X;
wire [0:0] sky130_fd_sc_hd__inv_1_0_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_1_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_2_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_3_Y;
wire [0:0] sky130_fd_sc_hd__or2_1_0_X;
//
//
//
//
sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_ (
.A(mode[0]),
.B(in[3]),
.X(sky130_fd_sc_hd__or2_1_0_X[0]));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
.A(in[0]),
.Y(sky130_fd_sc_hd__inv_1_0_Y[0]));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ (
.A(in[1]),
.Y(sky130_fd_sc_hd__inv_1_1_Y[0]));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ (
.A(in[2]),
.Y(sky130_fd_sc_hd__inv_1_2_Y[0]));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
.A(sky130_fd_sc_hd__or2_1_0_X[0]),
.Y(sky130_fd_sc_hd__inv_1_3_Y[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ (
.A(in[0]),
.X(sky130_fd_sc_hd__buf_2_0_X[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ (
.A(in[1]),
.X(sky130_fd_sc_hd__buf_2_1_X[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ (
.A(in[2]),
.X(sky130_fd_sc_hd__buf_2_2_X[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ (
.A(sky130_fd_sc_hd__or2_1_0_X[0]),
.X(sky130_fd_sc_hd__buf_2_3_X[0]));
frac_lut4_mux frac_lut4_mux_0_ (
.in(sram[0:15]),
.sram({sky130_fd_sc_hd__buf_2_0_X[0], sky130_fd_sc_hd__buf_2_1_X[0], sky130_fd_sc_hd__buf_2_2_X[0], sky130_fd_sc_hd__buf_2_3_X[0]}),
.sram_inv({sky130_fd_sc_hd__inv_1_0_Y[0], sky130_fd_sc_hd__inv_1_1_Y[0], sky130_fd_sc_hd__inv_1_2_Y[0], sky130_fd_sc_hd__inv_1_3_Y[0]}),
.lut3_out(lut3_out[0:1]),
.lut4_out(lut4_out[0]));
endmodule
//

825
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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
module mux_tree_tapbuf_size10_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule
//
//
module mux_tree_tapbuf_size8_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule
//
//
module mux_tree_tapbuf_size6_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
endmodule
//
//
module mux_tree_tapbuf_size5_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
endmodule
//
//
module mux_tree_tapbuf_size14_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule
//
//
module mux_tree_tapbuf_size3_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:1] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[1];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
endmodule
//
//
module mux_tree_tapbuf_size2_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:1] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[1];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
endmodule
//
//
module mux_tree_tapbuf_size7_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
endmodule
//
//
module mux_tree_tapbuf_size9_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule
//
//
module mux_tree_tapbuf_size12_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:3] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[3];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
endmodule
//
//
module mux_tree_tapbuf_size16_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:4] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[4];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ (
.CLK(prog_clk[0]),
.D(mem_out[3]),
.Q(mem_out[4]));
endmodule
//
//
module mux_tree_tapbuf_size4_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:2] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[2];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
endmodule
//
//
module mux_tree_size2_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:1] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[1];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
endmodule
//
//
module frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:16] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[16];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ (
.CLK(prog_clk[0]),
.D(mem_out[0]),
.Q(mem_out[1]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ (
.CLK(prog_clk[0]),
.D(mem_out[1]),
.Q(mem_out[2]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ (
.CLK(prog_clk[0]),
.D(mem_out[2]),
.Q(mem_out[3]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ (
.CLK(prog_clk[0]),
.D(mem_out[3]),
.Q(mem_out[4]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ (
.CLK(prog_clk[0]),
.D(mem_out[4]),
.Q(mem_out[5]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ (
.CLK(prog_clk[0]),
.D(mem_out[5]),
.Q(mem_out[6]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ (
.CLK(prog_clk[0]),
.D(mem_out[6]),
.Q(mem_out[7]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ (
.CLK(prog_clk[0]),
.D(mem_out[7]),
.Q(mem_out[8]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ (
.CLK(prog_clk[0]),
.D(mem_out[8]),
.Q(mem_out[9]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ (
.CLK(prog_clk[0]),
.D(mem_out[9]),
.Q(mem_out[10]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ (
.CLK(prog_clk[0]),
.D(mem_out[10]),
.Q(mem_out[11]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ (
.CLK(prog_clk[0]),
.D(mem_out[11]),
.Q(mem_out[12]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ (
.CLK(prog_clk[0]),
.D(mem_out[12]),
.Q(mem_out[13]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ (
.CLK(prog_clk[0]),
.D(mem_out[13]),
.Q(mem_out[14]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ (
.CLK(prog_clk[0]),
.D(mem_out[14]),
.Q(mem_out[15]));
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ (
.CLK(prog_clk[0]),
.D(mem_out[15]),
.Q(mem_out[16]));
endmodule
//
//
module EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out);
//
input [0:0] prog_clk;
//
input [0:0] ccff_head;
//
output [0:0] ccff_tail;
//
output [0:0] mem_out;
//
//
//
//
//
//
//
assign ccff_tail[0] = mem_out[0];
//
sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ (
.CLK(prog_clk[0]),
.D(ccff_head[0]),
.Q(mem_out[0]));
endmodule
//

1397
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/sub_module/muxes.v Normal file
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34
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/sub_module/wires.v Normal file
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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module direct_interc(in,
out);
//
input [0:0] in;
//
output [0:0] out;
//
//
//
//
wire [0:0] in;
wire [0:0] out;
assign out[0] = in[0];
endmodule
//
//

31
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/top_include_netlists.v Normal file
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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
`include "./SRC/define_simulation.v"
//
`include "./SRC/fabric_netlists.v"
`ifdef AUTOCHECKED_SIMULATION
`include "top_output_verilog.v"
`endif
`ifdef ENABLE_FORMAL_VERIFICATION
`include "./SRC/top_top_formal_verification.v"
`ifdef FORMAL_SIMULATION
`include "./SRC/top_formal_random_top_tb.v"
`endif
`endif
`ifdef AUTOCHECKED_SIMULATION
`include "./SRC/top_autocheck_top_tb.v"
`endif

1
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/TESTBENCH/top/fabric_bitstream.bit Normal file
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FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/TESTBENCH/top/fabric_bitstream.xml Normal file
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407192
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml Normal file
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67960
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/Testbench_Case/case_top.tcl Normal file
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1362
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/openfpgashell.log Normal file
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13
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/proj_const.tcl Normal file
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set DIE_HEIGHT 2800
set DIE_WIDTH 2800
set DESIGN_NAME fpga_core
set TASK_NAME FPGA1212_FLAT_HD_SKY_task
set VERILOG_PROJ_DIR FPGA1212_FLAT_HD_SKY_Verilog
set FPGA_ROW 12
set FPGA_COL 12
set INIT_DESIGN_INPUT ASCII
set TECHNOLOGY skywater
set DP_BLOCK_REFS [list sb_0__0_ sb_0__1_ sb_0__2_ sb_1__0_ sb_1__1_ sb_1__2_ sb_2__0_ sb_2__1_ sb_2__2_ cbx_1__0_ cbx_1__1_ cbx_1__2_ cby_0__1_ cby_1__1_ cby_2__1_ grid_clb];
set DP_FLOW "hier";
set DESIGN_STYLE "hier";
set STANDARD_CELLS sc_hd;

36
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/cbx_1__0__scandef.def Normal file
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mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_

64
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/cbx_1__1__scandef.def Normal file
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mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_

64
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/cbx_1__2__scandef.def Normal file
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mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_

4
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/cby_0__1__scandef.def Normal file
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@ -0,0 +1,4 @@
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_

64
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/cby_1__1__scandef.def Normal file
View File

@ -0,0 +1,64 @@
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_

64
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/cby_2__1__scandef.def Normal file
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mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_

1152
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/grid_clb_scandef.def Normal file
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File diff suppressed because it is too large Load Diff

52
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/sb_0__0__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_38/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_38/sky130_fd_sc_hd__dfxtp_1_1_

88
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/sb_0__1__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_1_

88
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/sb_0__2__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_1_

85
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/sb_1__0__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_22/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_22/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_38/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_38/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_

112
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/sb_1__1__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_

112
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/sb_1__2__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_

85
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/sb_2__0__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_22/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_22/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_38/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_38/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_

112
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/sb_2__1__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_

112
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/scandef/sb_2__2__scandef.def Normal file
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_4_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_
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mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_3_
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mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_3_
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mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_4_
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mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_0_
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mem_bottom_track_33/sky130_fd_sc_hd__dfxtp_1_2_
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mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_4_
mem_left_track_9/sky130_fd_sc_hd__dfxtp_1_0_
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mem_left_track_17/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_0_
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mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_25/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_33/sky130_fd_sc_hd__dfxtp_1_2_

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FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/arch/fabric_key.xml Normal file
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@ -0,0 +1,678 @@
<?xml version="1.0" ?>
<fabric_key>
<region id="0">
<key id="0" alias="sb_12__12_"/>
<key id="1" alias="cbx_12__12_"/>
<key id="2" alias="grid_io_top_top_12__13_"/>
<key id="3" alias="sb_11__12_"/>
<key id="4" alias="cbx_11__12_"/>
<key id="5" alias="grid_io_top_top_11__13_"/>
<key id="6" alias="sb_10__12_"/>
<key id="7" alias="cbx_10__12_"/>
<key id="8" alias="grid_io_top_top_10__13_"/>
<key id="9" alias="sb_9__12_"/>
<key id="10" alias="cbx_9__12_"/>
<key id="11" alias="grid_io_top_top_9__13_"/>
<key id="12" alias="sb_8__12_"/>
<key id="13" alias="cbx_8__12_"/>
<key id="14" alias="grid_io_top_top_8__13_"/>
<key id="15" alias="sb_7__12_"/>
<key id="16" alias="cbx_7__12_"/>
<key id="17" alias="grid_io_top_top_7__13_"/>
<key id="18" alias="sb_6__12_"/>
<key id="19" alias="cbx_6__12_"/>
<key id="20" alias="grid_io_top_top_6__13_"/>
<key id="21" alias="sb_5__12_"/>
<key id="22" alias="cbx_5__12_"/>
<key id="23" alias="grid_io_top_top_5__13_"/>
<key id="24" alias="sb_4__12_"/>
<key id="25" alias="cbx_4__12_"/>
<key id="26" alias="grid_io_top_top_4__13_"/>
<key id="27" alias="sb_3__12_"/>
<key id="28" alias="cbx_3__12_"/>
<key id="29" alias="grid_io_top_top_3__13_"/>
<key id="30" alias="sb_2__12_"/>
<key id="31" alias="cbx_2__12_"/>
<key id="32" alias="grid_io_top_top_2__13_"/>
<key id="33" alias="sb_1__12_"/>
<key id="34" alias="cbx_1__12_"/>
<key id="35" alias="grid_io_top_top_1__13_"/>
<key id="36" alias="sb_0__12_"/>
<key id="37" alias="cby_0__12_"/>
<key id="38" alias="grid_io_left_left_0__12_"/>
<key id="39" alias="grid_clb_1__12_"/>
<key id="40" alias="cby_1__12_"/>
<key id="41" alias="grid_clb_2__12_"/>
<key id="42" alias="cby_2__12_"/>
<key id="43" alias="grid_clb_3__12_"/>
<key id="44" alias="cby_3__12_"/>
<key id="45" alias="grid_clb_4__12_"/>
<key id="46" alias="cby_4__12_"/>
<key id="47" alias="grid_clb_5__12_"/>
<key id="48" alias="cby_5__12_"/>
<key id="49" alias="grid_clb_6__12_"/>
<key id="50" alias="cby_6__12_"/>
<key id="51" alias="grid_clb_7__12_"/>
<key id="52" alias="cby_7__12_"/>
<key id="53" alias="grid_clb_8__12_"/>
<key id="54" alias="cby_8__12_"/>
<key id="55" alias="grid_clb_9__12_"/>
<key id="56" alias="cby_9__12_"/>
<key id="57" alias="grid_clb_10__12_"/>
<key id="58" alias="cby_10__12_"/>
<key id="59" alias="grid_clb_11__12_"/>
<key id="60" alias="cby_11__12_"/>
<key id="61" alias="grid_clb_12__12_"/>
<key id="62" alias="cby_12__12_"/>
<key id="63" alias="grid_io_right_right_13__12_"/>
<key id="64" alias="sb_12__11_"/>
<key id="65" alias="cbx_12__11_"/>
<key id="66" alias="sb_11__11_"/>
<key id="67" alias="cbx_11__11_"/>
<key id="68" alias="sb_10__11_"/>
<key id="69" alias="cbx_10__11_"/>
<key id="70" alias="sb_9__11_"/>
<key id="71" alias="cbx_9__11_"/>
<key id="72" alias="sb_8__11_"/>
<key id="73" alias="cbx_8__11_"/>
<key id="74" alias="sb_7__11_"/>
<key id="75" alias="cbx_7__11_"/>
<key id="76" alias="sb_6__11_"/>
<key id="77" alias="cbx_6__11_"/>
<key id="78" alias="sb_5__11_"/>
<key id="79" alias="cbx_5__11_"/>
<key id="80" alias="sb_4__11_"/>
<key id="81" alias="cbx_4__11_"/>
<key id="82" alias="sb_3__11_"/>
<key id="83" alias="cbx_3__11_"/>
<key id="84" alias="sb_2__11_"/>
<key id="85" alias="cbx_2__11_"/>
<key id="86" alias="sb_1__11_"/>
<key id="87" alias="cbx_1__11_"/>
<key id="88" alias="sb_0__11_"/>
<key id="89" alias="cby_0__11_"/>
<key id="90" alias="grid_io_left_left_0__11_"/>
<key id="91" alias="grid_clb_1__11_"/>
<key id="92" alias="cby_1__11_"/>
<key id="93" alias="grid_clb_2__11_"/>
<key id="94" alias="cby_2__11_"/>
<key id="95" alias="grid_clb_3__11_"/>
<key id="96" alias="cby_3__11_"/>
<key id="97" alias="grid_clb_4__11_"/>
<key id="98" alias="cby_4__11_"/>
<key id="99" alias="grid_clb_5__11_"/>
<key id="100" alias="cby_5__11_"/>
<key id="101" alias="grid_clb_6__11_"/>
<key id="102" alias="cby_6__11_"/>
<key id="103" alias="grid_clb_7__11_"/>
<key id="104" alias="cby_7__11_"/>
<key id="105" alias="grid_clb_8__11_"/>
<key id="106" alias="cby_8__11_"/>
<key id="107" alias="grid_clb_9__11_"/>
<key id="108" alias="cby_9__11_"/>
<key id="109" alias="grid_clb_10__11_"/>
<key id="110" alias="cby_10__11_"/>
<key id="111" alias="grid_clb_11__11_"/>
<key id="112" alias="cby_11__11_"/>
<key id="113" alias="grid_clb_12__11_"/>
<key id="114" alias="cby_12__11_"/>
<key id="115" alias="grid_io_right_right_13__11_"/>
<key id="116" alias="sb_12__10_"/>
<key id="117" alias="cbx_12__10_"/>
<key id="118" alias="sb_11__10_"/>
<key id="119" alias="cbx_11__10_"/>
<key id="120" alias="sb_10__10_"/>
<key id="121" alias="cbx_10__10_"/>
<key id="122" alias="sb_9__10_"/>
<key id="123" alias="cbx_9__10_"/>
<key id="124" alias="sb_8__10_"/>
<key id="125" alias="cbx_8__10_"/>
<key id="126" alias="sb_7__10_"/>
<key id="127" alias="cbx_7__10_"/>
<key id="128" alias="sb_6__10_"/>
<key id="129" alias="cbx_6__10_"/>
<key id="130" alias="sb_5__10_"/>
<key id="131" alias="cbx_5__10_"/>
<key id="132" alias="sb_4__10_"/>
<key id="133" alias="cbx_4__10_"/>
<key id="134" alias="sb_3__10_"/>
<key id="135" alias="cbx_3__10_"/>
<key id="136" alias="sb_2__10_"/>
<key id="137" alias="cbx_2__10_"/>
<key id="138" alias="sb_1__10_"/>
<key id="139" alias="cbx_1__10_"/>
<key id="140" alias="sb_0__10_"/>
<key id="141" alias="cby_0__10_"/>
<key id="142" alias="grid_io_left_left_0__10_"/>
<key id="143" alias="grid_clb_1__10_"/>
<key id="144" alias="cby_1__10_"/>
<key id="145" alias="grid_clb_2__10_"/>
<key id="146" alias="cby_2__10_"/>
<key id="147" alias="grid_clb_3__10_"/>
<key id="148" alias="cby_3__10_"/>
<key id="149" alias="grid_clb_4__10_"/>
<key id="150" alias="cby_4__10_"/>
<key id="151" alias="grid_clb_5__10_"/>
<key id="152" alias="cby_5__10_"/>
<key id="153" alias="grid_clb_6__10_"/>
<key id="154" alias="cby_6__10_"/>
<key id="155" alias="grid_clb_7__10_"/>
<key id="156" alias="cby_7__10_"/>
<key id="157" alias="grid_clb_8__10_"/>
<key id="158" alias="cby_8__10_"/>
<key id="159" alias="grid_clb_9__10_"/>
<key id="160" alias="cby_9__10_"/>
<key id="161" alias="grid_clb_10__10_"/>
<key id="162" alias="cby_10__10_"/>
<key id="163" alias="grid_clb_11__10_"/>
<key id="164" alias="cby_11__10_"/>
<key id="165" alias="grid_clb_12__10_"/>
<key id="166" alias="cby_12__10_"/>
<key id="167" alias="grid_io_right_right_13__10_"/>
<key id="168" alias="sb_12__9_"/>
<key id="169" alias="cbx_12__9_"/>
<key id="170" alias="sb_11__9_"/>
<key id="171" alias="cbx_11__9_"/>
<key id="172" alias="sb_10__9_"/>
<key id="173" alias="cbx_10__9_"/>
<key id="174" alias="sb_9__9_"/>
<key id="175" alias="cbx_9__9_"/>
<key id="176" alias="sb_8__9_"/>
<key id="177" alias="cbx_8__9_"/>
<key id="178" alias="sb_7__9_"/>
<key id="179" alias="cbx_7__9_"/>
<key id="180" alias="sb_6__9_"/>
<key id="181" alias="cbx_6__9_"/>
<key id="182" alias="sb_5__9_"/>
<key id="183" alias="cbx_5__9_"/>
<key id="184" alias="sb_4__9_"/>
<key id="185" alias="cbx_4__9_"/>
<key id="186" alias="sb_3__9_"/>
<key id="187" alias="cbx_3__9_"/>
<key id="188" alias="sb_2__9_"/>
<key id="189" alias="cbx_2__9_"/>
<key id="190" alias="sb_1__9_"/>
<key id="191" alias="cbx_1__9_"/>
<key id="192" alias="sb_0__9_"/>
<key id="193" alias="cby_0__9_"/>
<key id="194" alias="grid_io_left_left_0__9_"/>
<key id="195" alias="grid_clb_1__9_"/>
<key id="196" alias="cby_1__9_"/>
<key id="197" alias="grid_clb_2__9_"/>
<key id="198" alias="cby_2__9_"/>
<key id="199" alias="grid_clb_3__9_"/>
<key id="200" alias="cby_3__9_"/>
<key id="201" alias="grid_clb_4__9_"/>
<key id="202" alias="cby_4__9_"/>
<key id="203" alias="grid_clb_5__9_"/>
<key id="204" alias="cby_5__9_"/>
<key id="205" alias="grid_clb_6__9_"/>
<key id="206" alias="cby_6__9_"/>
<key id="207" alias="grid_clb_7__9_"/>
<key id="208" alias="cby_7__9_"/>
<key id="209" alias="grid_clb_8__9_"/>
<key id="210" alias="cby_8__9_"/>
<key id="211" alias="grid_clb_9__9_"/>
<key id="212" alias="cby_9__9_"/>
<key id="213" alias="grid_clb_10__9_"/>
<key id="214" alias="cby_10__9_"/>
<key id="215" alias="grid_clb_11__9_"/>
<key id="216" alias="cby_11__9_"/>
<key id="217" alias="grid_clb_12__9_"/>
<key id="218" alias="cby_12__9_"/>
<key id="219" alias="grid_io_right_right_13__9_"/>
<key id="220" alias="sb_12__8_"/>
<key id="221" alias="cbx_12__8_"/>
<key id="222" alias="sb_11__8_"/>
<key id="223" alias="cbx_11__8_"/>
<key id="224" alias="sb_10__8_"/>
<key id="225" alias="cbx_10__8_"/>
<key id="226" alias="sb_9__8_"/>
<key id="227" alias="cbx_9__8_"/>
<key id="228" alias="sb_8__8_"/>
<key id="229" alias="cbx_8__8_"/>
<key id="230" alias="sb_7__8_"/>
<key id="231" alias="cbx_7__8_"/>
<key id="232" alias="sb_6__8_"/>
<key id="233" alias="cbx_6__8_"/>
<key id="234" alias="sb_5__8_"/>
<key id="235" alias="cbx_5__8_"/>
<key id="236" alias="sb_4__8_"/>
<key id="237" alias="cbx_4__8_"/>
<key id="238" alias="sb_3__8_"/>
<key id="239" alias="cbx_3__8_"/>
<key id="240" alias="sb_2__8_"/>
<key id="241" alias="cbx_2__8_"/>
<key id="242" alias="sb_1__8_"/>
<key id="243" alias="cbx_1__8_"/>
<key id="244" alias="sb_0__8_"/>
<key id="245" alias="cby_0__8_"/>
<key id="246" alias="grid_io_left_left_0__8_"/>
<key id="247" alias="grid_clb_1__8_"/>
<key id="248" alias="cby_1__8_"/>
<key id="249" alias="grid_clb_2__8_"/>
<key id="250" alias="cby_2__8_"/>
<key id="251" alias="grid_clb_3__8_"/>
<key id="252" alias="cby_3__8_"/>
<key id="253" alias="grid_clb_4__8_"/>
<key id="254" alias="cby_4__8_"/>
<key id="255" alias="grid_clb_5__8_"/>
<key id="256" alias="cby_5__8_"/>
<key id="257" alias="grid_clb_6__8_"/>
<key id="258" alias="cby_6__8_"/>
<key id="259" alias="grid_clb_7__8_"/>
<key id="260" alias="cby_7__8_"/>
<key id="261" alias="grid_clb_8__8_"/>
<key id="262" alias="cby_8__8_"/>
<key id="263" alias="grid_clb_9__8_"/>
<key id="264" alias="cby_9__8_"/>
<key id="265" alias="grid_clb_10__8_"/>
<key id="266" alias="cby_10__8_"/>
<key id="267" alias="grid_clb_11__8_"/>
<key id="268" alias="cby_11__8_"/>
<key id="269" alias="grid_clb_12__8_"/>
<key id="270" alias="cby_12__8_"/>
<key id="271" alias="grid_io_right_right_13__8_"/>
<key id="272" alias="sb_12__7_"/>
<key id="273" alias="cbx_12__7_"/>
<key id="274" alias="sb_11__7_"/>
<key id="275" alias="cbx_11__7_"/>
<key id="276" alias="sb_10__7_"/>
<key id="277" alias="cbx_10__7_"/>
<key id="278" alias="sb_9__7_"/>
<key id="279" alias="cbx_9__7_"/>
<key id="280" alias="sb_8__7_"/>
<key id="281" alias="cbx_8__7_"/>
<key id="282" alias="sb_7__7_"/>
<key id="283" alias="cbx_7__7_"/>
<key id="284" alias="sb_6__7_"/>
<key id="285" alias="cbx_6__7_"/>
<key id="286" alias="sb_5__7_"/>
<key id="287" alias="cbx_5__7_"/>
<key id="288" alias="sb_4__7_"/>
<key id="289" alias="cbx_4__7_"/>
<key id="290" alias="sb_3__7_"/>
<key id="291" alias="cbx_3__7_"/>
<key id="292" alias="sb_2__7_"/>
<key id="293" alias="cbx_2__7_"/>
<key id="294" alias="sb_1__7_"/>
<key id="295" alias="cbx_1__7_"/>
<key id="296" alias="sb_0__7_"/>
<key id="297" alias="cby_0__7_"/>
<key id="298" alias="grid_io_left_left_0__7_"/>
<key id="299" alias="grid_clb_1__7_"/>
<key id="300" alias="cby_1__7_"/>
<key id="301" alias="grid_clb_2__7_"/>
<key id="302" alias="cby_2__7_"/>
<key id="303" alias="grid_clb_3__7_"/>
<key id="304" alias="cby_3__7_"/>
<key id="305" alias="grid_clb_4__7_"/>
<key id="306" alias="cby_4__7_"/>
<key id="307" alias="grid_clb_5__7_"/>
<key id="308" alias="cby_5__7_"/>
<key id="309" alias="grid_clb_6__7_"/>
<key id="310" alias="cby_6__7_"/>
<key id="311" alias="grid_clb_7__7_"/>
<key id="312" alias="cby_7__7_"/>
<key id="313" alias="grid_clb_8__7_"/>
<key id="314" alias="cby_8__7_"/>
<key id="315" alias="grid_clb_9__7_"/>
<key id="316" alias="cby_9__7_"/>
<key id="317" alias="grid_clb_10__7_"/>
<key id="318" alias="cby_10__7_"/>
<key id="319" alias="grid_clb_11__7_"/>
<key id="320" alias="cby_11__7_"/>
<key id="321" alias="grid_clb_12__7_"/>
<key id="322" alias="cby_12__7_"/>
<key id="323" alias="grid_io_right_right_13__7_"/>
<key id="324" alias="sb_12__6_"/>
<key id="325" alias="cbx_12__6_"/>
<key id="326" alias="sb_11__6_"/>
<key id="327" alias="cbx_11__6_"/>
<key id="328" alias="sb_10__6_"/>
<key id="329" alias="cbx_10__6_"/>
<key id="330" alias="sb_9__6_"/>
<key id="331" alias="cbx_9__6_"/>
<key id="332" alias="sb_8__6_"/>
<key id="333" alias="cbx_8__6_"/>
<key id="334" alias="sb_7__6_"/>
<key id="335" alias="cbx_7__6_"/>
<key id="336" alias="sb_6__6_"/>
<key id="337" alias="cbx_6__6_"/>
<key id="338" alias="sb_5__6_"/>
<key id="339" alias="cbx_5__6_"/>
<key id="340" alias="sb_4__6_"/>
<key id="341" alias="cbx_4__6_"/>
<key id="342" alias="sb_3__6_"/>
<key id="343" alias="cbx_3__6_"/>
<key id="344" alias="sb_2__6_"/>
<key id="345" alias="cbx_2__6_"/>
<key id="346" alias="sb_1__6_"/>
<key id="347" alias="cbx_1__6_"/>
<key id="348" alias="sb_0__6_"/>
<key id="349" alias="cby_0__6_"/>
<key id="350" alias="grid_io_left_left_0__6_"/>
<key id="351" alias="grid_clb_1__6_"/>
<key id="352" alias="cby_1__6_"/>
<key id="353" alias="grid_clb_2__6_"/>
<key id="354" alias="cby_2__6_"/>
<key id="355" alias="grid_clb_3__6_"/>
<key id="356" alias="cby_3__6_"/>
<key id="357" alias="grid_clb_4__6_"/>
<key id="358" alias="cby_4__6_"/>
<key id="359" alias="grid_clb_5__6_"/>
<key id="360" alias="cby_5__6_"/>
<key id="361" alias="grid_clb_6__6_"/>
<key id="362" alias="cby_6__6_"/>
<key id="363" alias="grid_clb_7__6_"/>
<key id="364" alias="cby_7__6_"/>
<key id="365" alias="grid_clb_8__6_"/>
<key id="366" alias="cby_8__6_"/>
<key id="367" alias="grid_clb_9__6_"/>
<key id="368" alias="cby_9__6_"/>
<key id="369" alias="grid_clb_10__6_"/>
<key id="370" alias="cby_10__6_"/>
<key id="371" alias="grid_clb_11__6_"/>
<key id="372" alias="cby_11__6_"/>
<key id="373" alias="grid_clb_12__6_"/>
<key id="374" alias="cby_12__6_"/>
<key id="375" alias="grid_io_right_right_13__6_"/>
<key id="376" alias="sb_12__5_"/>
<key id="377" alias="cbx_12__5_"/>
<key id="378" alias="sb_11__5_"/>
<key id="379" alias="cbx_11__5_"/>
<key id="380" alias="sb_10__5_"/>
<key id="381" alias="cbx_10__5_"/>
<key id="382" alias="sb_9__5_"/>
<key id="383" alias="cbx_9__5_"/>
<key id="384" alias="sb_8__5_"/>
<key id="385" alias="cbx_8__5_"/>
<key id="386" alias="sb_7__5_"/>
<key id="387" alias="cbx_7__5_"/>
<key id="388" alias="sb_6__5_"/>
<key id="389" alias="cbx_6__5_"/>
<key id="390" alias="sb_5__5_"/>
<key id="391" alias="cbx_5__5_"/>
<key id="392" alias="sb_4__5_"/>
<key id="393" alias="cbx_4__5_"/>
<key id="394" alias="sb_3__5_"/>
<key id="395" alias="cbx_3__5_"/>
<key id="396" alias="sb_2__5_"/>
<key id="397" alias="cbx_2__5_"/>
<key id="398" alias="sb_1__5_"/>
<key id="399" alias="cbx_1__5_"/>
<key id="400" alias="sb_0__5_"/>
<key id="401" alias="cby_0__5_"/>
<key id="402" alias="grid_io_left_left_0__5_"/>
<key id="403" alias="grid_clb_1__5_"/>
<key id="404" alias="cby_1__5_"/>
<key id="405" alias="grid_clb_2__5_"/>
<key id="406" alias="cby_2__5_"/>
<key id="407" alias="grid_clb_3__5_"/>
<key id="408" alias="cby_3__5_"/>
<key id="409" alias="grid_clb_4__5_"/>
<key id="410" alias="cby_4__5_"/>
<key id="411" alias="grid_clb_5__5_"/>
<key id="412" alias="cby_5__5_"/>
<key id="413" alias="grid_clb_6__5_"/>
<key id="414" alias="cby_6__5_"/>
<key id="415" alias="grid_clb_7__5_"/>
<key id="416" alias="cby_7__5_"/>
<key id="417" alias="grid_clb_8__5_"/>
<key id="418" alias="cby_8__5_"/>
<key id="419" alias="grid_clb_9__5_"/>
<key id="420" alias="cby_9__5_"/>
<key id="421" alias="grid_clb_10__5_"/>
<key id="422" alias="cby_10__5_"/>
<key id="423" alias="grid_clb_11__5_"/>
<key id="424" alias="cby_11__5_"/>
<key id="425" alias="grid_clb_12__5_"/>
<key id="426" alias="cby_12__5_"/>
<key id="427" alias="grid_io_right_right_13__5_"/>
<key id="428" alias="sb_12__4_"/>
<key id="429" alias="cbx_12__4_"/>
<key id="430" alias="sb_11__4_"/>
<key id="431" alias="cbx_11__4_"/>
<key id="432" alias="sb_10__4_"/>
<key id="433" alias="cbx_10__4_"/>
<key id="434" alias="sb_9__4_"/>
<key id="435" alias="cbx_9__4_"/>
<key id="436" alias="sb_8__4_"/>
<key id="437" alias="cbx_8__4_"/>
<key id="438" alias="sb_7__4_"/>
<key id="439" alias="cbx_7__4_"/>
<key id="440" alias="sb_6__4_"/>
<key id="441" alias="cbx_6__4_"/>
<key id="442" alias="sb_5__4_"/>
<key id="443" alias="cbx_5__4_"/>
<key id="444" alias="sb_4__4_"/>
<key id="445" alias="cbx_4__4_"/>
<key id="446" alias="sb_3__4_"/>
<key id="447" alias="cbx_3__4_"/>
<key id="448" alias="sb_2__4_"/>
<key id="449" alias="cbx_2__4_"/>
<key id="450" alias="sb_1__4_"/>
<key id="451" alias="cbx_1__4_"/>
<key id="452" alias="sb_0__4_"/>
<key id="453" alias="cby_0__4_"/>
<key id="454" alias="grid_io_left_left_0__4_"/>
<key id="455" alias="grid_clb_1__4_"/>
<key id="456" alias="cby_1__4_"/>
<key id="457" alias="grid_clb_2__4_"/>
<key id="458" alias="cby_2__4_"/>
<key id="459" alias="grid_clb_3__4_"/>
<key id="460" alias="cby_3__4_"/>
<key id="461" alias="grid_clb_4__4_"/>
<key id="462" alias="cby_4__4_"/>
<key id="463" alias="grid_clb_5__4_"/>
<key id="464" alias="cby_5__4_"/>
<key id="465" alias="grid_clb_6__4_"/>
<key id="466" alias="cby_6__4_"/>
<key id="467" alias="grid_clb_7__4_"/>
<key id="468" alias="cby_7__4_"/>
<key id="469" alias="grid_clb_8__4_"/>
<key id="470" alias="cby_8__4_"/>
<key id="471" alias="grid_clb_9__4_"/>
<key id="472" alias="cby_9__4_"/>
<key id="473" alias="grid_clb_10__4_"/>
<key id="474" alias="cby_10__4_"/>
<key id="475" alias="grid_clb_11__4_"/>
<key id="476" alias="cby_11__4_"/>
<key id="477" alias="grid_clb_12__4_"/>
<key id="478" alias="cby_12__4_"/>
<key id="479" alias="grid_io_right_right_13__4_"/>
<key id="480" alias="sb_12__3_"/>
<key id="481" alias="cbx_12__3_"/>
<key id="482" alias="sb_11__3_"/>
<key id="483" alias="cbx_11__3_"/>
<key id="484" alias="sb_10__3_"/>
<key id="485" alias="cbx_10__3_"/>
<key id="486" alias="sb_9__3_"/>
<key id="487" alias="cbx_9__3_"/>
<key id="488" alias="sb_8__3_"/>
<key id="489" alias="cbx_8__3_"/>
<key id="490" alias="sb_7__3_"/>
<key id="491" alias="cbx_7__3_"/>
<key id="492" alias="sb_6__3_"/>
<key id="493" alias="cbx_6__3_"/>
<key id="494" alias="sb_5__3_"/>
<key id="495" alias="cbx_5__3_"/>
<key id="496" alias="sb_4__3_"/>
<key id="497" alias="cbx_4__3_"/>
<key id="498" alias="sb_3__3_"/>
<key id="499" alias="cbx_3__3_"/>
<key id="500" alias="sb_2__3_"/>
<key id="501" alias="cbx_2__3_"/>
<key id="502" alias="sb_1__3_"/>
<key id="503" alias="cbx_1__3_"/>
<key id="504" alias="sb_0__3_"/>
<key id="505" alias="cby_0__3_"/>
<key id="506" alias="grid_io_left_left_0__3_"/>
<key id="507" alias="grid_clb_1__3_"/>
<key id="508" alias="cby_1__3_"/>
<key id="509" alias="grid_clb_2__3_"/>
<key id="510" alias="cby_2__3_"/>
<key id="511" alias="grid_clb_3__3_"/>
<key id="512" alias="cby_3__3_"/>
<key id="513" alias="grid_clb_4__3_"/>
<key id="514" alias="cby_4__3_"/>
<key id="515" alias="grid_clb_5__3_"/>
<key id="516" alias="cby_5__3_"/>
<key id="517" alias="grid_clb_6__3_"/>
<key id="518" alias="cby_6__3_"/>
<key id="519" alias="grid_clb_7__3_"/>
<key id="520" alias="cby_7__3_"/>
<key id="521" alias="grid_clb_8__3_"/>
<key id="522" alias="cby_8__3_"/>
<key id="523" alias="grid_clb_9__3_"/>
<key id="524" alias="cby_9__3_"/>
<key id="525" alias="grid_clb_10__3_"/>
<key id="526" alias="cby_10__3_"/>
<key id="527" alias="grid_clb_11__3_"/>
<key id="528" alias="cby_11__3_"/>
<key id="529" alias="grid_clb_12__3_"/>
<key id="530" alias="cby_12__3_"/>
<key id="531" alias="grid_io_right_right_13__3_"/>
<key id="532" alias="sb_12__2_"/>
<key id="533" alias="cbx_12__2_"/>
<key id="534" alias="sb_11__2_"/>
<key id="535" alias="cbx_11__2_"/>
<key id="536" alias="sb_10__2_"/>
<key id="537" alias="cbx_10__2_"/>
<key id="538" alias="sb_9__2_"/>
<key id="539" alias="cbx_9__2_"/>
<key id="540" alias="sb_8__2_"/>
<key id="541" alias="cbx_8__2_"/>
<key id="542" alias="sb_7__2_"/>
<key id="543" alias="cbx_7__2_"/>
<key id="544" alias="sb_6__2_"/>
<key id="545" alias="cbx_6__2_"/>
<key id="546" alias="sb_5__2_"/>
<key id="547" alias="cbx_5__2_"/>
<key id="548" alias="sb_4__2_"/>
<key id="549" alias="cbx_4__2_"/>
<key id="550" alias="sb_3__2_"/>
<key id="551" alias="cbx_3__2_"/>
<key id="552" alias="sb_2__2_"/>
<key id="553" alias="cbx_2__2_"/>
<key id="554" alias="sb_1__2_"/>
<key id="555" alias="cbx_1__2_"/>
<key id="556" alias="sb_0__2_"/>
<key id="557" alias="cby_0__2_"/>
<key id="558" alias="grid_io_left_left_0__2_"/>
<key id="559" alias="grid_clb_1__2_"/>
<key id="560" alias="cby_1__2_"/>
<key id="561" alias="grid_clb_2__2_"/>
<key id="562" alias="cby_2__2_"/>
<key id="563" alias="grid_clb_3__2_"/>
<key id="564" alias="cby_3__2_"/>
<key id="565" alias="grid_clb_4__2_"/>
<key id="566" alias="cby_4__2_"/>
<key id="567" alias="grid_clb_5__2_"/>
<key id="568" alias="cby_5__2_"/>
<key id="569" alias="grid_clb_6__2_"/>
<key id="570" alias="cby_6__2_"/>
<key id="571" alias="grid_clb_7__2_"/>
<key id="572" alias="cby_7__2_"/>
<key id="573" alias="grid_clb_8__2_"/>
<key id="574" alias="cby_8__2_"/>
<key id="575" alias="grid_clb_9__2_"/>
<key id="576" alias="cby_9__2_"/>
<key id="577" alias="grid_clb_10__2_"/>
<key id="578" alias="cby_10__2_"/>
<key id="579" alias="grid_clb_11__2_"/>
<key id="580" alias="cby_11__2_"/>
<key id="581" alias="grid_clb_12__2_"/>
<key id="582" alias="cby_12__2_"/>
<key id="583" alias="grid_io_right_right_13__2_"/>
<key id="584" alias="sb_12__1_"/>
<key id="585" alias="cbx_12__1_"/>
<key id="586" alias="sb_11__1_"/>
<key id="587" alias="cbx_11__1_"/>
<key id="588" alias="sb_10__1_"/>
<key id="589" alias="cbx_10__1_"/>
<key id="590" alias="sb_9__1_"/>
<key id="591" alias="cbx_9__1_"/>
<key id="592" alias="sb_8__1_"/>
<key id="593" alias="cbx_8__1_"/>
<key id="594" alias="sb_7__1_"/>
<key id="595" alias="cbx_7__1_"/>
<key id="596" alias="sb_6__1_"/>
<key id="597" alias="cbx_6__1_"/>
<key id="598" alias="sb_5__1_"/>
<key id="599" alias="cbx_5__1_"/>
<key id="600" alias="sb_4__1_"/>
<key id="601" alias="cbx_4__1_"/>
<key id="602" alias="sb_3__1_"/>
<key id="603" alias="cbx_3__1_"/>
<key id="604" alias="sb_2__1_"/>
<key id="605" alias="cbx_2__1_"/>
<key id="606" alias="sb_1__1_"/>
<key id="607" alias="cbx_1__1_"/>
<key id="608" alias="sb_0__1_"/>
<key id="609" alias="cby_0__1_"/>
<key id="610" alias="grid_io_left_left_0__1_"/>
<key id="611" alias="grid_clb_1__1_"/>
<key id="612" alias="cby_1__1_"/>
<key id="613" alias="grid_clb_2__1_"/>
<key id="614" alias="cby_2__1_"/>
<key id="615" alias="grid_clb_3__1_"/>
<key id="616" alias="cby_3__1_"/>
<key id="617" alias="grid_clb_4__1_"/>
<key id="618" alias="cby_4__1_"/>
<key id="619" alias="grid_clb_5__1_"/>
<key id="620" alias="cby_5__1_"/>
<key id="621" alias="grid_clb_6__1_"/>
<key id="622" alias="cby_6__1_"/>
<key id="623" alias="grid_clb_7__1_"/>
<key id="624" alias="cby_7__1_"/>
<key id="625" alias="grid_clb_8__1_"/>
<key id="626" alias="cby_8__1_"/>
<key id="627" alias="grid_clb_9__1_"/>
<key id="628" alias="cby_9__1_"/>
<key id="629" alias="grid_clb_10__1_"/>
<key id="630" alias="cby_10__1_"/>
<key id="631" alias="grid_clb_11__1_"/>
<key id="632" alias="cby_11__1_"/>
<key id="633" alias="grid_clb_12__1_"/>
<key id="634" alias="cby_12__1_"/>
<key id="635" alias="grid_io_right_right_13__1_"/>
<key id="636" alias="sb_12__0_"/>
<key id="637" alias="cbx_12__0_"/>
<key id="638" alias="grid_io_bottom_bottom_12__0_"/>
<key id="639" alias="sb_11__0_"/>
<key id="640" alias="cbx_11__0_"/>
<key id="641" alias="grid_io_bottom_bottom_11__0_"/>
<key id="642" alias="sb_10__0_"/>
<key id="643" alias="cbx_10__0_"/>
<key id="644" alias="grid_io_bottom_bottom_10__0_"/>
<key id="645" alias="sb_9__0_"/>
<key id="646" alias="cbx_9__0_"/>
<key id="647" alias="grid_io_bottom_bottom_9__0_"/>
<key id="648" alias="sb_8__0_"/>
<key id="649" alias="cbx_8__0_"/>
<key id="650" alias="grid_io_bottom_bottom_8__0_"/>
<key id="651" alias="sb_7__0_"/>
<key id="652" alias="cbx_7__0_"/>
<key id="653" alias="grid_io_bottom_bottom_7__0_"/>
<key id="654" alias="sb_6__0_"/>
<key id="655" alias="cbx_6__0_"/>
<key id="656" alias="grid_io_bottom_bottom_6__0_"/>
<key id="657" alias="sb_5__0_"/>
<key id="658" alias="cbx_5__0_"/>
<key id="659" alias="grid_io_bottom_bottom_5__0_"/>
<key id="660" alias="sb_4__0_"/>
<key id="661" alias="cbx_4__0_"/>
<key id="662" alias="grid_io_bottom_bottom_4__0_"/>
<key id="663" alias="sb_3__0_"/>
<key id="664" alias="cbx_3__0_"/>
<key id="665" alias="grid_io_bottom_bottom_3__0_"/>
<key id="666" alias="sb_2__0_"/>
<key id="667" alias="cbx_2__0_"/>
<key id="668" alias="grid_io_bottom_bottom_2__0_"/>
<key id="669" alias="sb_1__0_"/>
<key id="670" alias="cbx_1__0_"/>
<key id="671" alias="grid_io_bottom_bottom_1__0_"/>
<key id="672" alias="sb_0__0_"/>
</region>
</fabric_key>

253
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/arch/openfpga_arch.xml Normal file
View File

@ -0,0 +1,253 @@
<!-- Architecture annotation for OpenFPGA framework
This annotation supports the k4_frac_cc_sky130nm.xml
- General purpose logic block
- K = 6, N = 10, I = 40
- Single mode
- Routing architecture
- L = 4, fc_in = 0.15, fc_out = 0.1
- Skywater 130nm PDK
- circuit models are binded to the opensource skywater
foundry middle-speed (ms) standard cell library
-->
<openfpga_architecture>
<technology_library>
<device_library>
<device_model name="logic" type="transistor">
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="0.9" pn_ratio="2"/>
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
</device_model>
<device_model name="io" type="transistor">
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="2.5" pn_ratio="3"/>
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
</device_model>
</device_library>
<variation_library>
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
</variation_library>
</technology_library>
<circuit_library>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v">
<design_technology type="cmos" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="Y" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v">
<design_technology type="cmos" topology="buffer" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="Y" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
<design_technology type="cmos" topology="OR"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
</circuit_model>
<!-- Define a circuit model for the standard cell MUX2
OpenFPGA requires the following truth table for the MUX2
When the select signal sel is enabled, the first input, i.e., in0
will be propagated to the output, i.e., out
If your standard cell provider does not offer the exact truth table,
you can simply swap the inputs as shown in the example below
-->
<circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v">
<design_technology type="cmos" topology="MUX2"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in0" lib_name="A1" size="1"/>
<port type="input" prefix="in1" lib_name="A0" size="1"/>
<port type="input" prefix="sel" lib_name="S" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="sky130_fd_sc_hd__sdfxtp_1" prefix="sky130_fd_sc_hd__sdfxtp_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="DI" lib_name="SCD" size="1"/>
<port type="input" prefix="Test_en" lib_name="SCE" size="1" is_global="true" default_val="0"/>
<!-- <port type="input" prefix="reset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_reset="true"/> -->
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="false" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
<lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
<lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="16"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" default_val="1"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="sky130_fd_sc_hd__dfxtp_1" prefix="sky130_fd_sc_hd__dfxtp_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="EMBEDDED_IO_HD" prefix="EMBEDDED_IO_HD" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" default_val="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" num_regions="1"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
</connection_block>
<switch_block>
<switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
<switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
<switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
</switch_block>
<routing_segment>
<segment name="L1" circuit_model_name="chan_segment"/>
<segment name="L2" circuit_model_name="chan_segment"/>
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<direct_connection>
<direct name="shift_register" circuit_model_name="direct_interc"/>
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
</direct_connection>
<tile_annotations>
<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
</tile_annotations>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
<pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO_HD" mode_bits="1"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfxtp_1"/>
<!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
<port name="in" physical_mode_port="in[0:2]"/>
<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
</pb_type>
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<!-- Binding operating pb_types in mode 'ble4' -->
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
<port name="in" physical_mode_port="in[0:3]"/>
<port name="out" physical_mode_port="lut4_out"/>
</pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- Binding operating pb_types in mode 'shift_register' -->
<pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<!-- End physical pb_type binding in complex block IO -->
</pb_type_annotations>
</openfpga_architecture>

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<!--
Low-cost homogeneous FPGA Architecture.
- Skywater 130 nm technology
- General purpose logic block:
K = 4, N = 8, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared)
with optionally registered outputs
- Routing architecture:
- 10% L = 1, fc_in = 0.15, Fc_out = 0.10
- 10% L = 2, fc_in = 0.15, Fc_out = 0.10
- 80% L = 4, fc_in = 0.15, Fc_out = 0.10
- 100 routing tracks per channel
Authors: Xifan Tang
-->
<architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports.
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch)
that describe them.
-->
<models>
<!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io">
<input_ports>
<port name="outpad"/>
</input_ports>
<output_ports>
<port name="inpad"/>
</output_ports>
</model>
<model name="frac_lut4">
<input_ports>
<port name="in"/>
</input_ports>
<output_ports>
<port name="lut3_out"/>
<port name="lut4_out"/>
</output_ports>
</model>
<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
<model name="scff">
<input_ports>
<port name="D" clock="clk"/>
<port name="DI" clock="clk"/>
<port name="clk" is_clock="1"/>
</input_ports>
<output_ports>
<port name="Q" clock="clk"/>
</output_ports>
</model>
</models>
<tiles>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="1" area="0">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</tile>
<!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="1" area="0">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</tile>
<!-- Bottom-side has 9 I/O per tile -->
<tile name="io_bottom" capacity="9" area="0">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</tile>
<!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="1" area="0">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</tile>
<!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
<input name="I0" num_pins="3" equivalent="full"/>
<input name="I0i" num_pins="1" equivalent="none"/>
<input name="I1" num_pins="3" equivalent="full"/>
<input name="I1i" num_pins="1" equivalent="none"/>
<input name="I2" num_pins="3" equivalent="full"/>
<input name="I2i" num_pins="1" equivalent="none"/>
<input name="I3" num_pins="3" equivalent="full"/>
<input name="I3i" num_pins="1" equivalent="none"/>
<input name="I4" num_pins="3" equivalent="full"/>
<input name="I4i" num_pins="1" equivalent="none"/>
<input name="I5" num_pins="3" equivalent="full"/>
<input name="I5i" num_pins="1" equivalent="none"/>
<input name="I6" num_pins="3" equivalent="full"/>
<input name="I6i" num_pins="1" equivalent="none"/>
<input name="I7" num_pins="3" equivalent="full"/>
<input name="I7i" num_pins="1" equivalent="none"/>
<input name="reg_in" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="O" num_pins="16" equivalent="none"/>
<output name="reg_out" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="reg_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="reg_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc>
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="left">clb.clk</loc>
<loc side="top">clb.reg_in clb.sc_in clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i</loc>
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.reg_out clb.sc_out</loc>
</pinlocations>
</tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout tileable="true">
<auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<row type="io_top" starty="H-1" priority="100"/>
<row type="io_bottom" starty="0" priority="100"/>
<col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</auto_layout>
<fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<row type="io_top" starty="H-1" priority="100"/>
<row type="io_bottom" starty="0" priority="100"/>
<col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</fixed_layout>
<fixed_layout name="12x12" width="14" height="14">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<row type="io_top" starty="H-1" priority="100"/>
<row type="io_bottom" starty="0" priority="100"/>
<col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</fixed_layout>
</layout>
<device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
lined up with Stratix IV.
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
by 2.5x when looking up in Jeff's tables.
The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-->
<area grid_logic_tile_area="0"/>
<chan_width_distr>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
<connection_block input_switch_name="ipin_cblock"/>
</device>
<switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="L1_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L2_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<switch type="mux" name="L4_mux" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist>
<segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L1" freq="0.10" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="L1_mux"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
<segment name="L2" freq="0.10" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="L2_mux"/>
<sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb>
</segment>
<segment name="L4" freq="0.80" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="L4_mux"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
</segmentlist>
<directlist>
<direct name="shift_register" from_pin="clb.reg_out" to_pin="clb.reg_in" x_offset="0" y_offset="-1" z_offset="0"/>
<direct name="scan_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0"/>
</directlist>
<complexblocklist>
<!-- Define input pads begin -->
<pb_type name="io">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation
-->
<mode name="physical" disabled_in_pack="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin -->
<!-- -Due to the absence of local routing,
the 4 inputs of fracturable LUT4 are no longer equivalent,
because the 4th input can not be switched when the dual-LUT3 modes are used.
So pin equivalence should be applied to the first 3 inputs only
-->
<pb_type name="clb">
<input name="I0" num_pins="3" equivalent="full"/>
<input name="I0i" num_pins="1" equivalent="none"/>
<input name="I1" num_pins="3" equivalent="full"/>
<input name="I1i" num_pins="1" equivalent="none"/>
<input name="I2" num_pins="3" equivalent="full"/>
<input name="I2i" num_pins="1" equivalent="none"/>
<input name="I3" num_pins="3" equivalent="full"/>
<input name="I3i" num_pins="1" equivalent="none"/>
<input name="I4" num_pins="3" equivalent="full"/>
<input name="I4i" num_pins="1" equivalent="none"/>
<input name="I5" num_pins="3" equivalent="full"/>
<input name="I5i" num_pins="1" equivalent="none"/>
<input name="I6" num_pins="3" equivalent="full"/>
<input name="I6i" num_pins="1" equivalent="none"/>
<input name="I7" num_pins="3" equivalent="full"/>
<input name="I7i" num_pins="1" equivalent="none"/>
<input name="reg_in" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="O" num_pins="16" equivalent="none"/>
<output name="reg_out" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered
-->
<pb_type name="fle" num_pb="8">
<input name="in" num_pins="4"/>
<input name="reg_in" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="out" num_pins="2"/>
<output name="reg_out" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true">
<pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/>
<input name="reg_in" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="out" num_pins="2"/>
<output name="reg_out" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<pb_type name="frac_logic" num_pb="1">
<input name="in" num_pins="4"/>
<output name="out" num_pins="2"/>
<!-- Define LUT -->
<pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
<input name="in" num_pins="4"/>
<output name="lut3_out" num_pins="2"/>
<output name="lut4_out" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
<direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
<mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
</interconnect>
</pb_type>
<!-- Define flip-flop with scan-chain capability, DI is the scan-chain data input -->
<pb_type name="ff" blif_model=".subckt scff" num_pb="2">
<input name="D" num_pins="1"/>
<input name="DI" num_pins="1"/>
<output name="Q" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_setup value="66e-12" port="ff.DI" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="fabric.sc_in" output="ff[0].DI"/>
<direct name="direct3" input="ff[0].Q" output="ff[1].DI"/>
<direct name="direct4" input="ff[1].Q" output="fabric.sc_out"/>
<direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="45e-12" in_port="fabric.reg_in" out_port="ff[0:0].D"/>
</mux>
<mux name="mux2" input="frac_logic.out[1:1] ff[0:0].Q" output="ff[1:1].D">
<delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ff[1:1].D"/>
</mux>
<mux name="mux3" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux>
<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="fabric.in"/>
<direct name="direct3" input="fle.reg_in" output="fabric.reg_in"/>
<direct name="direct4" input="fle.sc_in" output="fabric.sc_in"/>
<direct name="direct5" input="fabric.out" output="fle.out"/>
<direct name="direct7" input="fabric.reg_out" output="fle.reg_out"/>
<direct name="direct8" input="fabric.sc_out" output="fle.sc_out"/>
<direct name="direct9" input="fle.clk" output="fabric.clk"/>
</interconnect>
</mode>
<!-- Physical mode definition end (physical implementation of the fle) -->
<!-- Dual 3-LUT mode definition begin -->
<mode name="n2_lut3">
<pb_type name="lut3inter" num_pb="1">
<input name="in" num_pins="3"/>
<output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/>
<pb_type name="ble3" num_pb="2">
<input name="in" num_pins="3"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define the LUT -->
<pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
-->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12
235e-12
235e-12
</delay_matrix>
</pb_type>
<!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
</direct>
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
<direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
<direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
<complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
<direct name="direct2" input="lut3inter.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
</interconnect>
</mode>
<!-- Dual 3-LUT mode definition end -->
<!-- 4-LUT mode definition begin -->
<mode name="n1_lut4">
<!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results
82e-12
173e-12
261e-12
263e-12
398e-12
397e-12
-->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12
261e-12
261e-12
261e-12
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect>
</mode>
<!-- 4-LUT mode definition end -->
<!-- Define shift register begin -->
<mode name="shift_register">
<pb_type name="shift_reg" num_pb="1">
<input name="reg_in" num_pins="1"/>
<output name="ff_out" num_pins="2"/>
<output name="reg_out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D"/>
<direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
<direct name="direct3" input="ff[1].Q" output="shift_reg.reg_out"/>
<direct name="direct4" input="ff[0].Q" output="shift_reg.ff_out[0:0]"/>
<direct name="direct5" input="ff[1].Q" output="shift_reg.ff_out[1:1]"/>
<complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.reg_in" output="shift_reg.reg_in"/>
<direct name="direct2" input="shift_reg.reg_out" output="fle.reg_out"/>
<direct name="direct3" input="shift_reg.ff_out" output="fle.out"/>
<direct name="direct4" input="fle.clk" output="shift_reg.clk"/>
</interconnect>
</mode>
<!-- Define shift register end -->
</pb_type>
<interconnect>
<!-- We use direct connections to reduce the area to the most
The global local routing is going to compensate the loss in routability
-->
<!-- FIXME: The implicit port definition results in I0[0] connected to
in[2]. Such twisted connection is not expected.
I[0] should be connected to in[0]
-->
<direct name="direct_fle0" input="clb.I0[0:2]" output="fle[0:0].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle0i" input="clb.I0i" output="fle[0:0].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle1" input="clb.I1[0:2]" output="fle[1:1].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle1i" input="clb.I1i" output="fle[1:1].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle2" input="clb.I2[0:2]" output="fle[2:2].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle2i" input="clb.I2i" output="fle[2:2].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle3" input="clb.I3[0:2]" output="fle[3:3].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle3i" input="clb.I3i" output="fle[3:3].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle4" input="clb.I4[0:2]" output="fle[4:4].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle4i" input="clb.I4i" output="fle[4:4].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle5" input="clb.I5[0:2]" output="fle[5:5].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle5i" input="clb.I5i" output="fle[5:5].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle6" input="clb.I6[0:2]" output="fle[6:6].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle6i" input="clb.I6i" output="fle[6:6].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle7" input="clb.I7[0:2]" output="fle[7:7].in[0:2]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<direct name="direct_fle7i" input="clb.I7i" output="fle[7:7].in[3]">
<!-- TODO: Timing should be backannotated from post-PnR results -->
</direct>
<complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification).
-->
<direct name="clbouts1" input="fle[3:0].out[0:1]" output="clb.O[7:0]"/>
<direct name="clbouts2" input="fle[7:4].out[0:1]" output="clb.O[15:8]"/>
<!-- Shift register chain links -->
<direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
</direct>
<direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
<!--pack_pattern name="chain" in_port="fle[7:7].reg_out" out_port="clb.reg_out"/-->
</direct>
<direct name="shift_register_link" input="fle[6:0].reg_out" output="fle[7:1].reg_in">
<!--pack_pattern name="chain" in_port="fle[6:0].reg_out" out_port="fle[7:1].reg_in"/-->
</direct>
<!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.sc_in" out_port="fle[0:0].sc_in"/>
</direct>
<direct name="scan_chain_out" input="fle[7:7].sc_out" output="clb.sc_out">
</direct>
<direct name="scan_chain_link" input="fle[6:0].sc_out" output="fle[7:1].sc_in">
</direct>
</interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column -->
</pb_type>
<!-- Define general purpose logic block (CLB) ends -->
</complexblocklist>
</architecture>

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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=40
[ARCHITECTURES]
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
[SYNTHESIS_PARAM]
bench0_top = top
bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
vpr_fpga_verilog_formal_verification_top_netlist=

39
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/config/task_generation.conf Normal file
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_route_chan_width=40
[ARCHITECTURES]
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
[SYNTHESIS_PARAM]
bench0_top = top
bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
vpr_fpga_verilog_formal_verification_top_netlist=

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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif
[SYNTHESIS_PARAM]
bench0_top = top
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
vpr_fpga_verilog_formal_verification_top_netlist=

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DELAY_VALUE: 12

57
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# This script is designed to generate fabric Verilog netlists
# with a fixed device layout
# It will only output netlists to be used by backend tools,
# i.e., Synopsys ICC2, including
# - Verilog netlists
# - fabric hierarchy description for ICC2's hierarchical flow
# - Timing/Design constraints
#
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE}
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack
build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml
build_fabric_bitstream
write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
write_fabric_bitstream --format xml --file fabric_bitstream.xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

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# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --route_chan_width 200
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup --verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE}
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
build_fabric_bitstream
# Build fabric-dependent bitstream
build_fabric_bitstream
write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
write_fabric_bitstream --format xml --file fabric_bitstream.xml
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

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a 0.5 0.5
b 0.5 0.5
c 0.25 0.25

8
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.model top
.inputs a b
.outputs c
.names a b c
11 1
.end

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FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/micro_benchmark/and.v Normal file
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`timescale 1ns / 1ps
module top(
a,
b,
c);
input wire a;
input wire b;
output wire c;
assign c = a & b;
endmodule

46
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#!/bin/bash
cp user_project_wrapper_template.def user_project_wrapper_empty.def
sed -i '/^SPECIALNETS/,/END SPECIALNETS/d' user_project_wrapper_empty.def
sed -i '/^VIAS/,/END VIAS/d' user_project_wrapper_empty.def
sed -i '/^ROW ROW/d' user_project_wrapper_empty.def
sed -i '/^TRACKS/d' user_project_wrapper_empty.def
sed -i 's/user_project_wrapper/fpga_top/' user_project_wrapper_empty.def
VDD_LINES=$(grep "\- vdda\|vccd" user_project_wrapper_empty.def)
VSS_LINES=$(grep "\- vssa\|vssd" user_project_wrapper_empty.def)
sed -i '/^ - v.*$/d' user_project_wrapper_empty.def
X="2920000"
Y="3520000"
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/\-.*\(FIXED.*\) ;/+ PORT + \1/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/^.*met.*[0-9]\{6,\}.*//")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/\(.*met5\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -5000 -\3 ) ( 5000 \3 )/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/\(.*met4\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -\2 -5000 ) ( \2 5000 )/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 2920000 \2 \3/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \(-[0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 0 \2 \3/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\) )\(.*met4\)/FIXED ( \1 3520000 ) \3/g")
VDD_LINES=$(echo "${VDD_LINES}" | sed "s/FIXED ( \([0-9]*\) \(-[0-9]*\) )\(.*met4\)/FIXED ( \1 0 ) \3/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/\-.*\(FIXED.*\) ;/+ PORT + \1/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/^.*met.*[0-9]\{6,\}.*//")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/\(.*met5\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -5000 -\3 ) ( 5000 \3 )/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/\(.*met4\).*) ( \([0-9]*\) \([0-9]*\) )/\1 ( -\2 -5000 ) ( \2 5000 )/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 2920000 \2 \3/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \(-[0-9]*\) \([0-9]*\)\(.*met5\)/FIXED ( 0 \2 \3/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \([0-9]*\) \([0-9]*\) )\(.*met4\)/FIXED ( \1 3520000 ) \3/g")
VSS_LINES=$(echo "${VSS_LINES}" | sed "s/FIXED ( \([0-9]*\) \(-[0-9]*\) )\(.*met4\)/FIXED ( \1 0 ) \3/g")
sed -i '/END PINS/d' user_project_wrapper_empty.def
sed -i '/END DESIGN/d' user_project_wrapper_empty.def
echo " - VDD + NET VDD + SPECIAL + DIRECTION INPUT + USE POWER" >> user_project_wrapper_empty.def
printf "${VDD_LINES} ;\n" >> user_project_wrapper_empty.def
echo "- VSS + NET VSS + SPECIAL + DIRECTION INPUT + USE GROUND" >> user_project_wrapper_empty.def
printf "${VSS_LINES} ;\n" >> user_project_wrapper_empty.def
echo "END PINS" >> user_project_wrapper_empty.def
echo "END DESIGN" >> user_project_wrapper_empty.def

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`timescale 1ns/1ps
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
module EMBEDDED_IO_HD (
input SOC_IN, //
output SOC_OUT, //
output SOC_DIR, //
output FPGA_IN, //
input FPGA_OUT, //
input FPGA_DIR, //
input IO_ISOL_N //
);
wire SOC_DIR_N;
//
sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (.B_N(IO_ISOL_N),
.A(FPGA_DIR),
.X(SOC_DIR)
);
//
sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR), .Y(SOC_DIR_N));
sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE (.TE_B(SOC_DIR_N),
.A(SOC_IN),
.Z(FPGA_IN)
);
//
sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE (.TE_B(SOC_DIR),
.A(FPGA_OUT),
.Z(SOC_OUT)
);
endmodule

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/*
*-------------------------------------------------------------
*
* A wrapper for the FPGA IP to fit the I/O interface of Caravel SoC
*
* The wrapper is a technology mapped netlist where the mode-switch
* multiplexers are mapped to the Skywater 130nm
* High-Density (HD) standard cells
*
*-------------------------------------------------------------
*/
module fpga_top (
//
//
inout vdda1, //
inout vdda2, //
inout vssa1, //
inout vssa2, //
inout vccd1, //
inout vccd2, //
inout vssd1, //
inout vssd2, //
//
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
//
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oen,
//
input [37:0] io_in,
output [37:0] io_out,
output [37:0] io_oeb
);
//
//
//
//
//
//
//
//
wire prog_clk;
wire Test_en;
wire io_isol_n;
wire clk;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
wire ccff_head;
wire ccff_tail;
wire sc_head;
wire sc_tail;
//
wire wb_la_switch;
wire wb_la_switch_b;
//
//
//
//
//
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24];
assign io_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0];
assign io_oeb[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0];
//
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1:9] = io_in[23:15];
assign io_out[23:15] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1:9];
assign io_oeb[23:15] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1:9];
//
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10:11] = io_in[14:13];
assign io_out[14:13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10:11];
assign io_oeb[14:13] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10:11];
//
assign ccff_head = io_in[12];
assign io_out[12] = 1'b0;
assign io_oeb[12] = 1'b1;
assign io_out[11] = sc_tail;
assign io_oeb[11] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12:20] = io_in[10:2];
assign io_out[10:2] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12:20];
assign io_oeb[10:2] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12:20];
assign io_isol_n = io_in[1];
assign io_out[1] = 1'b0;
assign io_oeb[1] = 1'b1;
assign Test_en = io_in[0];
assign io_out[0] = 1'b0;
assign io_oeb[0] = 1'b1;
//
//
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX (.S(wb_la_switch), .A1(wb_clk_i), .A0(la_data_in[13]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135]));
assign la_data_out[13] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX (.S(wb_la_switch), .A1(wb_rst_i), .A0(la_data_in[14]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134]));
assign la_data_out[14] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[15];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(wbs_ack_o));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133]), .Z(la_data_out[15]));
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX (.S(wb_la_switch), .A1(wbs_cyc_i), .A0(la_data_in[16]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132]));
assign la_data_out[16] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX (.S(wb_la_switch), .A1(wbs_stb_i), .A0(la_data_in[17]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131]));
assign la_data_out[17] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX (.S(wb_la_switch), .A1(wbs_we_i), .A0(la_data_in[18]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130]));
assign la_data_out[18] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX (.S(wb_la_switch), .A1(wbs_sel_i[0]), .A0(la_data_in[19]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129]));
assign la_data_out[19] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX (.S(wb_la_switch), .A1(wbs_sel_i[1]), .A0(la_data_in[20]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128]));
assign la_data_out[20] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX (.S(wb_la_switch), .A1(wbs_sel_i[2]), .A0(la_data_in[21]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127]));
assign la_data_out[21] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX (.S(wb_la_switch), .A1(wbs_sel_i[3]), .A0(la_data_in[22]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126]));
assign la_data_out[22] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX (.S(wb_la_switch), .A1(wbs_adr_i[0]), .A0(la_data_in[23]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125]));
assign la_data_out[23] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX (.S(wb_la_switch), .A1(wbs_adr_i[1]), .A0(la_data_in[24]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124]));
assign la_data_out[24] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX (.S(wb_la_switch), .A1(wbs_adr_i[2]), .A0(la_data_in[25]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123]));
assign la_data_out[25] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX (.S(wb_la_switch), .A1(wbs_adr_i[3]), .A0(la_data_in[26]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122]));
assign la_data_out[26] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX (.S(wb_la_switch), .A1(wbs_adr_i[4]), .A0(la_data_in[27]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121]));
assign la_data_out[27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX (.S(wb_la_switch), .A1(wbs_adr_i[5]), .A0(la_data_in[28]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120]));
assign la_data_out[28] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX (.S(wb_la_switch), .A1(wbs_adr_i[6]), .A0(la_data_in[29]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119]));
assign la_data_out[29] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX (.S(wb_la_switch), .A1(wbs_adr_i[7]), .A0(la_data_in[30]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118]));
assign la_data_out[30] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX (.S(wb_la_switch), .A1(wbs_adr_i[8]), .A0(la_data_in[31]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117]));
assign la_data_out[31] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX (.S(wb_la_switch), .A1(wbs_adr_i[9]), .A0(la_data_in[32]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116]));
assign la_data_out[32] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX (.S(wb_la_switch), .A1(wbs_adr_i[10]), .A0(la_data_in[33]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115]));
assign la_data_out[33] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX (.S(wb_la_switch), .A1(wbs_adr_i[11]), .A0(la_data_in[34]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114]));
assign la_data_out[34] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX (.S(wb_la_switch), .A1(wbs_adr_i[12]), .A0(la_data_in[35]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113]));
assign la_data_out[35] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX (.S(wb_la_switch), .A1(wbs_adr_i[13]), .A0(la_data_in[36]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112]));
assign la_data_out[36] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX (.S(wb_la_switch), .A1(wbs_adr_i[14]), .A0(la_data_in[37]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111]));
assign la_data_out[37] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX (.S(wb_la_switch), .A1(wbs_adr_i[15]), .A0(la_data_in[38]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110]));
assign la_data_out[38] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX (.S(wb_la_switch), .A1(wbs_adr_i[16]), .A0(la_data_in[39]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109]));
assign la_data_out[39] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX (.S(wb_la_switch), .A1(wbs_adr_i[17]), .A0(la_data_in[40]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108]));
assign la_data_out[40] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX (.S(wb_la_switch), .A1(wbs_adr_i[18]), .A0(la_data_in[41]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107]));
assign la_data_out[41] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX (.S(wb_la_switch), .A1(wbs_adr_i[19]), .A0(la_data_in[42]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106]));
assign la_data_out[42] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX (.S(wb_la_switch), .A1(wbs_adr_i[20]), .A0(la_data_in[43]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105]));
assign la_data_out[43] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX (.S(wb_la_switch), .A1(wbs_adr_i[21]), .A0(la_data_in[44]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104]));
assign la_data_out[44] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX (.S(wb_la_switch), .A1(wbs_adr_i[22]), .A0(la_data_in[45]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103]));
assign la_data_out[45] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX (.S(wb_la_switch), .A1(wbs_adr_i[23]), .A0(la_data_in[46]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102]));
assign la_data_out[46] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX (.S(wb_la_switch), .A1(wbs_adr_i[24]), .A0(la_data_in[47]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101]));
assign la_data_out[47] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX (.S(wb_la_switch), .A1(wbs_adr_i[25]), .A0(la_data_in[48]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100]));
assign la_data_out[48] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX (.S(wb_la_switch), .A1(wbs_adr_i[26]), .A0(la_data_in[49]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99]));
assign la_data_out[49] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX (.S(wb_la_switch), .A1(wbs_adr_i[27]), .A0(la_data_in[50]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98]));
assign la_data_out[50] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX (.S(wb_la_switch), .A1(wbs_adr_i[28]), .A0(la_data_in[51]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97]));
assign la_data_out[51] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX (.S(wb_la_switch), .A1(wbs_adr_i[29]), .A0(la_data_in[52]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96]));
assign la_data_out[52] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX (.S(wb_la_switch), .A1(wbs_adr_i[30]), .A0(la_data_in[53]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95]));
assign la_data_out[53] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX (.S(wb_la_switch), .A1(wbs_adr_i[31]), .A0(la_data_in[54]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94]));
assign la_data_out[54] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX (.S(wb_la_switch), .A1(wbs_dat_i[0]), .A0(la_data_in[55]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93]));
assign la_data_out[55] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX (.S(wb_la_switch), .A1(wbs_dat_i[1]), .A0(la_data_in[56]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92]));
assign la_data_out[56] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX (.S(wb_la_switch), .A1(wbs_dat_i[2]), .A0(la_data_in[57]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91]));
assign la_data_out[57] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX (.S(wb_la_switch), .A1(wbs_dat_i[3]), .A0(la_data_in[58]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90]));
assign la_data_out[58] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX (.S(wb_la_switch), .A1(wbs_dat_i[4]), .A0(la_data_in[59]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89]));
assign la_data_out[59] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX (.S(wb_la_switch), .A1(wbs_dat_i[5]), .A0(la_data_in[60]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88]));
assign la_data_out[60] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX (.S(wb_la_switch), .A1(wbs_dat_i[6]), .A0(la_data_in[61]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87]));
assign la_data_out[61] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX (.S(wb_la_switch), .A1(wbs_dat_i[7]), .A0(la_data_in[62]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86]));
assign la_data_out[62] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX (.S(wb_la_switch), .A1(wbs_dat_i[8]), .A0(la_data_in[63]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85]));
assign la_data_out[63] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX (.S(wb_la_switch), .A1(wbs_dat_i[9]), .A0(la_data_in[64]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84]));
assign la_data_out[64] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX (.S(wb_la_switch), .A1(wbs_dat_i[10]), .A0(la_data_in[65]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83]));
assign la_data_out[65] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX (.S(wb_la_switch), .A1(wbs_dat_i[11]), .A0(la_data_in[66]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82]));
assign la_data_out[66] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX (.S(wb_la_switch), .A1(wbs_dat_i[12]), .A0(la_data_in[67]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81]));
assign la_data_out[67] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX (.S(wb_la_switch), .A1(wbs_dat_i[13]), .A0(la_data_in[68]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80]));
assign la_data_out[68] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX (.S(wb_la_switch), .A1(wbs_dat_i[14]), .A0(la_data_in[69]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79]));
assign la_data_out[69] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX (.S(wb_la_switch), .A1(wbs_dat_i[15]), .A0(la_data_in[70]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78]));
assign la_data_out[70] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX (.S(wb_la_switch), .A1(wbs_dat_i[16]), .A0(la_data_in[71]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77]));
assign la_data_out[71] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX (.S(wb_la_switch), .A1(wbs_dat_i[17]), .A0(la_data_in[72]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76]));
assign la_data_out[72] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX (.S(wb_la_switch), .A1(wbs_dat_i[18]), .A0(la_data_in[73]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75]));
assign la_data_out[73] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX (.S(wb_la_switch), .A1(wbs_dat_i[19]), .A0(la_data_in[74]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74]));
assign la_data_out[74] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX (.S(wb_la_switch), .A1(wbs_dat_i[20]), .A0(la_data_in[75]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73]));
assign la_data_out[75] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX (.S(wb_la_switch), .A1(wbs_dat_i[21]), .A0(la_data_in[76]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72]));
assign la_data_out[76] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX (.S(wb_la_switch), .A1(wbs_dat_i[22]), .A0(la_data_in[77]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71]));
assign la_data_out[77] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX (.S(wb_la_switch), .A1(wbs_dat_i[23]), .A0(la_data_in[78]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70]));
assign la_data_out[78] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX (.S(wb_la_switch), .A1(wbs_dat_i[24]), .A0(la_data_in[79]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69]));
assign la_data_out[79] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX (.S(wb_la_switch), .A1(wbs_dat_i[25]), .A0(la_data_in[80]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68]));
assign la_data_out[80] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX (.S(wb_la_switch), .A1(wbs_dat_i[26]), .A0(la_data_in[81]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67]));
assign la_data_out[81] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX (.S(wb_la_switch), .A1(wbs_dat_i[27]), .A0(la_data_in[82]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66]));
assign la_data_out[82] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX (.S(wb_la_switch), .A1(wbs_dat_i[28]), .A0(la_data_in[83]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65]));
assign la_data_out[83] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX (.S(wb_la_switch), .A1(wbs_dat_i[29]), .A0(la_data_in[84]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64]));
assign la_data_out[84] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX (.S(wb_la_switch), .A1(wbs_dat_i[30]), .A0(la_data_in[85]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63]));
assign la_data_out[85] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63];
sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX (.S(wb_la_switch), .A1(wbs_dat_i[31]), .A0(la_data_in[86]), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62]));
assign la_data_out[86] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[87];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(wbs_dat_o[0]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61]), .Z(la_data_out[87]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[88];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(wbs_dat_o[1]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60]), .Z(la_data_out[88]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[89];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(wbs_dat_o[2]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59]), .Z(la_data_out[89]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[90];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(wbs_dat_o[3]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58]), .Z(la_data_out[90]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[91];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(wbs_dat_o[4]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57]), .Z(la_data_out[91]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[92];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(wbs_dat_o[5]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56]), .Z(la_data_out[92]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[93];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(wbs_dat_o[6]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55]), .Z(la_data_out[93]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[94];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(wbs_dat_o[7]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54]), .Z(la_data_out[94]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[95];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(wbs_dat_o[8]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53]), .Z(la_data_out[95]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[96];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(wbs_dat_o[9]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52]), .Z(la_data_out[96]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[97];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(wbs_dat_o[10]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51]), .Z(la_data_out[97]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[98];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(wbs_dat_o[11]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50]), .Z(la_data_out[98]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[99];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(wbs_dat_o[12]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49]), .Z(la_data_out[99]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[100];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(wbs_dat_o[13]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48]), .Z(la_data_out[100]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[101];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(wbs_dat_o[14]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47]), .Z(la_data_out[101]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[102];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(wbs_dat_o[15]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46]), .Z(la_data_out[102]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[103];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(wbs_dat_o[16]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45]), .Z(la_data_out[103]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[104];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(wbs_dat_o[17]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44]), .Z(la_data_out[104]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[105];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(wbs_dat_o[18]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43]), .Z(la_data_out[105]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[106];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(wbs_dat_o[19]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42]), .Z(la_data_out[106]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[107];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(wbs_dat_o[20]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41]), .Z(la_data_out[107]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[108];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(wbs_dat_o[21]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40]), .Z(la_data_out[108]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[109];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(wbs_dat_o[22]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39]), .Z(la_data_out[109]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[110];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(wbs_dat_o[23]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38]), .Z(la_data_out[110]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[111];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(wbs_dat_o[24]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37]), .Z(la_data_out[111]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[112];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(wbs_dat_o[25]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36]), .Z(la_data_out[112]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[113];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(wbs_dat_o[26]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35]), .Z(la_data_out[113]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[114];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(wbs_dat_o[27]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34]), .Z(la_data_out[114]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[115];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(wbs_dat_o[28]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33]), .Z(la_data_out[115]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[116];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(wbs_dat_o[29]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32]), .Z(la_data_out[116]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[117];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(wbs_dat_o[30]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31]), .Z(la_data_out[117]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[118];
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB (.TE_B(wb_la_switch_b), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(wbs_dat_o[31]));
sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA (.TE_B(wb_la_switch), .A(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30]), .Z(la_data_out[118]));
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[119];
assign la_data_out[119] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[120];
assign la_data_out[120] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[121];
assign la_data_out[121] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[122];
assign la_data_out[122] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[123];
assign la_data_out[123] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[124];
assign la_data_out[124] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[125];
assign la_data_out[125] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[126];
assign la_data_out[126] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22];
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[127];
assign la_data_out[127] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21];
//
//
assign prog_clk = io_in[37];
assign io_out[37] = 1'b0;
assign io_oeb[37] = 1'b1;
//
assign clk = io_in[36];
assign io_out[36] = 1'b0;
assign io_oeb[36] = 1'b1;
assign io_out[35] = ccff_tail;
assign io_oeb[35] = 1'b0;
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136:143] = io_in[34:27];
assign io_out[34:27] = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136:143];
assign io_oeb[34:27] = gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136:143];
assign sc_head = io_in[26];
assign io_out[26] = 1'b0;
assign io_oeb[26] = 1'b1;
//
//
assign wb_la_switch = io_in[25];
assign io_out[25] = 1'b0;
assign io_oeb[25] = 1'b1;
//
fpga_core fpga_core_uut(.prog_clk(prog_clk),
.Test_en(Test_en),
.clk(clk),
.IO_ISOL_N(io_isol_n),
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN),
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT),
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),
.sc_head(sc_head),
.sc_tail(sc_tail)
);
endmodule

1219
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/user_project_wrapper_empty.def Normal file
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3768
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/user_project_wrapper_template.def Normal file
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1
FPGA1212_SOFA_HD_PNR/config.sh
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@ -30,6 +30,7 @@ export VERILOG_PROJ_DIR=${PROJ_NAME}_Verilog
export SPY_HACK_FILE=${TASK_DIR_NAME}/spy_hack.txt
export POST_OPENFPGA_SCRIPT=./PostOpenFPGAScript.sh
export RESTRUCT_NETLIST=../utils/RestructureNetlistSkywater.py
export POST_GENERATION_SCRIPT=./generate_scandef_and_case_analysis.sh
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Restructure Netlist Varaibles