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correct the VPR binding for netlist generation

This commit is contained in:
Tarachand Pagarani 2020-12-08 07:12:13 -08:00
parent a90528544d
commit 053afc7c45
4 changed files with 5 additions and 5 deletions
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4
ARCH/openfpga_arch_template/ql_ap3_8x8_arch_vpr_routing_skywater130nm_fdhd_cc_openfpga.xml
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@ -86,7 +86,7 @@
If your standard cell provider does not offer the exact truth table,
you can simply swap the inputs as shown in the example below
-->
<circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
<circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
<design_technology type="cmos" topology="OR"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
@ -238,7 +238,7 @@
<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
<pb_type name="IO[PHYSICAL].iopad.macro" circuit_model_name="EMBEDDED_IO_HD" mode_bits="1"/>
<pb_type name="IO[INPUT].INPUT.i_pad" physical_pb_type_name="IO[PHYSICAL].iopad.macro" mode_bits="1"/>
<pb_type name="IO[OUTPUT].OUTPUT.o_pad" physical_pb_type_name="IO[PHYSICAL].iopad.macro" mode_bits="0"/>
<pb_type name="IO[OUTPUT].OUTPUT.o_pad" physical_pb_type_name="IO[PHYSICAL].iopad.macro" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->

2
SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
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@ -21,7 +21,7 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
build_fabric --compress_routing --duplicate_grid_pin --generate_random_fabric_key #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows

2
SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
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@ -30,7 +30,7 @@ lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
build_fabric --compress_routing --duplicate_grid_pin --generate_random_fabric_key #--verbose
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation

2
SCRIPT/skywater_openfpga_task/ql_ap3_vpr_routing_caravel_cc_fdhd_8x8/generate_testbench/config/task_template.conf
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@ -19,7 +19,7 @@ fpga_flow=yosys_vpr
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/ql_ap3_8x8_arch_vpr_routing_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
openfpga_vpr_device_layout=12x12
openfpga_vpr_device_layout=8x8
openfpga_vpr_route_chan_width=40
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/ql_ap3_vpr_routing_caravel_io_FPGA_8x8_fdhd_cc/prepnr
openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/ql_ap3_vpr_routing_caravel_io_FPGA_8x8_fdhd_cc/SRC/fabric_netlists.v