[QLSOFA_HD] Updated QLSOFA_HD postPnr Netlist + Caravel DRC clean
Ganesh Gore
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Before Width: | Height: | Size: 178 KiB |
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After Width: | Height: | Size: 1.6 MiB |
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Before Width: | Height: | Size: 101 KiB |
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After Width: | Height: | Size: 509 KiB |
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Before Width: | Height: | Size: 178 KiB |
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After Width: | Height: | Size: 2.4 MiB |
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Before Width: | Height: | Size: 105 KiB |
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After Width: | Height: | Size: 570 KiB |
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Before Width: | Height: | Size: 164 KiB |
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After Width: | Height: | Size: 1.7 MiB |
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Before Width: | Height: | Size: 148 KiB |
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After Width: | Height: | Size: 1.2 MiB |
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Before Width: | Height: | Size: 153 KiB |
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After Width: | Height: | Size: 1.6 MiB |
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Before Width: | Height: | Size: 147 KiB |
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After Width: | Height: | Size: 1.4 MiB |
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Before Width: | Height: | Size: 166 KiB |
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After Width: | Height: | Size: 973 KiB |
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Before Width: | Height: | Size: 74 KiB |
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After Width: | Height: | Size: 415 KiB |
BIN
FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef (Stored with Git LFS)
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@ -0,0 +1,18 @@
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| Module | Util| Area| Sites| Insts| Std_Cells
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|--------------------|----------|-----------------|-------|-------|-------
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|fpga_core_uut/sb_0__0_ | 45.82 | 8718.361600 | 6968 | 1 | 1003
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|fpga_core_uut/sb_0__11_ | 75.59 | 9519.129600 | 7608 | 11 | 855
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|fpga_core_uut/sb_0__12_ | 45.97 | 8718.361600 | 6968 | 1 | 1006
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|fpga_core_uut/sb_11__0_ | 71.29 | 11030.579200 | 8816 | 11 | 1078
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|fpga_core_uut/sb_11__11_ | 90.88 | 11831.347200 | 9456 | 121 | 533
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|fpga_core_uut/sb_11__12_ | 70.54 | 11030.579200 | 8816 | 11 | 1089
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|fpga_core_uut/sb_12__0_ | 64.08 | 8718.361600 | 6968 | 1 | 955
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|fpga_core_uut/sb_12__11_ | 82.83 | 9519.129600 | 7608 | 11 | 624
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|fpga_core_uut/sb_12__12_ | 65.1 | 8718.361600 | 6968 | 1 | 943
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|fpga_core_uut/cbx_12__0_ | 74.63 | 5745.510400 | 4592 | 12 | 439
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|fpga_core_uut/cbx_12__11_ | 88.39 | 5745.510400 | 4592 | 132 | 382
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|fpga_core_uut/cbx_12__12_ | 90.81 | 5745.510400 | 4592 | 12 | 267
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|fpga_core_uut/cby_0__12_ | 23.46 | 6406.144000 | 5120 | 12 | 815
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|fpga_core_uut/cby_11__12_ | 82.05 | 6406.144000 | 5120 | 132 | 444
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|fpga_core_uut/cby_12__12_ | 82.64 | 6406.144000 | 5120 | 12 | 486
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|fpga_core_uut/grid_clb_12__12_ | 68.26 | 14814.208000 | 11840 | 144 | 1370
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Ref Name Total Area Utilization_% Instance Count
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----------------------------------------------------------------------------------------------------
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sky130_fd_sc_hd__dfrtp_1 1971015.360000 19.18 78765
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sky130_fd_sc_hd__mux2_1 1591488.864000 15.49 141330
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sky130_fd_sc_hd__buf_8 452744.217600 4.41 30154
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sky130_fd_sc_hd__buf_6 150252.854400 1.46 13343
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sky130_fd_sc_hd__buf_1 88960.320000 0.87 23700
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sky130_fd_sc_hd__inv_8 76584.700800 0.75 6801
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sky130_fd_sc_hd__sdfrtp_1 72069.120000 0.70 2304
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sky130_fd_sc_hd__dlygate4sd3_1 56293.990400 0.55 5624
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sky130_fd_sc_hd__mux2_2 44311.248000 0.43 3935
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sky130_fd_sc_hd__inv_1 42156.681600 0.41 11231
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sky130_fd_sc_hd__buf_4 39112.512000 0.38 5210
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sky130_fd_sc_hd__bufbuf_16 36239.756800 0.35 1114
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sky130_fd_sc_hd__conb_1 25592.044800 0.25 6818
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sky130_fd_sc_hd__inv_2 13696.886400 0.13 3649
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sky130_fd_sc_hd__or2_0 7206.912000 0.07 1152
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sky130_fd_sc_hd__inv_6 6235.980800 0.06 712
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sky130_fd_sc_hd__ebufn_4 5758.022400 0.06 354
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sky130_fd_sc_hd__clkbuf_1 2747.635200 0.03 732
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sky130_fd_sc_hd__dlygate4sd2_1 2417.318400 0.02 276
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sky130_fd_sc_hd__buf_2 1436.377600 0.01 287
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sky130_fd_sc_hd__dlygate4sd1_1 1366.310400 0.01 156
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sky130_fd_sc_hd__nand2b_1 825.792000 0.01 132
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sky130_fd_sc_hd__buf_16 633.107200 0.01 23
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sky130_fd_sc_hd__inv_4 450.432000 0.00 72
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sky130_fd_sc_hd__buf_12 220.211200 0.00 11
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sky130_fd_sc_hd__clkbuf_8 165.158400 0.00 12
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sky130_fd_sc_hd__or2b_4 135.129600 0.00 12
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FPGA_BBOX_AREA 6714279.5264
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CORE_BBOX_AREA 10276128.1216
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FPGA_BBOX_UTIL 65.3386124321
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Can't render this file because it has a wrong number of fields in line 2.
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@ -0,0 +1,75 @@
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****************************************
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Report : clock timing
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-type latency
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-launch
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-nworst 1
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-setup
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Design : fpga_top
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Version: P-2019.03-SP4
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Date : Mon Dec 14 01:56:02 2020
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****************************************
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Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
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Mode: full_chip
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Clock: PROG_CLK
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--- Latency ---
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Clock Pin Trans Source Offset Network Total Corner
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---------------------------------------------------------------------------------------------------
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fpga_core_uut/sb_11__11_/mem_right_track_2/sky130_fd_sc_hd__dfrtp_1_3_/CLK 6.164 0.000 -- 11.143 11.143 rp-+ nominal
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---------------------------------------------------------------------------------------------------
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Mode: full_chip
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Clock: CLK
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--- Latency ---
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Clock Pin Trans Source Offset Network Total Corner
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---------------------------------------------------------------------------------------------------
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fpga_core_uut/grid_clb_11__12_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 0.710 0.000 -- 6.927 6.927 rp-+ nominal
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---------------------------------------------------------------------------------------------------
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****************************************
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Report : clock timing
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-type skew
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-nworst 1
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-setup
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Design : fpga_top
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Version: P-2019.03-SP4
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Date : Mon Dec 14 01:56:02 2020
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****************************************
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Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
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Mode: full_chip
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Clock: PROG_CLK
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Clock Pin Latency Skew Corner
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---------------------------------------------------------------------------------------------------
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fpga_core_uut/sb_10__8_/mem_left_track_53/sky130_fd_sc_hd__dfrtp_1_2_/CLK 9.828 rp-+ nominal
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fpga_core_uut/cbx_10__8_/mem_top_ipin_0/sky130_fd_sc_hd__dfrtp_1_0_/CLK 5.994 3.835 rp-+ nominal
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---------------------------------------------------------------------------------------------------
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Mode: full_chip
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Clock: CLK
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Clock Pin Latency Skew Corner
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---------------------------------------------------------------------------------------------------
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fpga_core_uut/grid_clb_6__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 6.115 rp-+ nominal
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fpga_core_uut/grid_clb_6__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 5.386 0.729 rp-+ nominal
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---------------------------------------------------------------------------------------------------
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Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
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****************************************
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Report : global timing
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-format { narrow }
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Design : fpga_top
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Version: P-2019.03-SP4
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Date : Mon Dec 14 01:56:04 2020
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****************************************
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No setup violations found.
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No hold violations found.
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1
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